1a47a12beSStefan Roese /* 2689f00fcSPrabhakar Kushwaha * Copyright 2009-2012 Freescale Semiconductor, Inc 3a47a12beSStefan Roese * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 7a47a12beSStefan Roese #include <common.h> 8a47a12beSStefan Roese #include <asm/processor.h> 9a47a12beSStefan Roese #include <asm/mmu.h> 10a47a12beSStefan Roese #include <asm/fsl_law.h> 11e8e6197aSPoonam Aggrwal #include <asm/io.h> 12a47a12beSStefan Roese 13a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 14a47a12beSStefan Roese 1574fa22edSPrabhakar Kushwaha #ifdef CONFIG_A003399_NOR_WORKAROUND 16bc6bbd6bSPoonam Aggrwal void setup_ifc(void) 17bc6bbd6bSPoonam Aggrwal { 18bc6bbd6bSPoonam Aggrwal struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; 19bc6bbd6bSPoonam Aggrwal u32 _mas0, _mas1, _mas2, _mas3, _mas7; 20bc6bbd6bSPoonam Aggrwal phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; 21bc6bbd6bSPoonam Aggrwal 22bc6bbd6bSPoonam Aggrwal /* 23bc6bbd6bSPoonam Aggrwal * Adjust the TLB we were running out of to match the phys addr of the 24bc6bbd6bSPoonam Aggrwal * chip select we are adjusting and will return to. 25bc6bbd6bSPoonam Aggrwal */ 26bc6bbd6bSPoonam Aggrwal flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; 27bc6bbd6bSPoonam Aggrwal 28bc6bbd6bSPoonam Aggrwal _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); 29bc6bbd6bSPoonam Aggrwal _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | 30bc6bbd6bSPoonam Aggrwal MAS1_TSIZE(BOOKE_PAGESZ_4M); 31bc6bbd6bSPoonam Aggrwal _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); 32bc6bbd6bSPoonam Aggrwal _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); 33bc6bbd6bSPoonam Aggrwal _mas7 = FSL_BOOKE_MAS7(flash_phys); 34bc6bbd6bSPoonam Aggrwal 35bc6bbd6bSPoonam Aggrwal mtspr(MAS0, _mas0); 36bc6bbd6bSPoonam Aggrwal mtspr(MAS1, _mas1); 37bc6bbd6bSPoonam Aggrwal mtspr(MAS2, _mas2); 38bc6bbd6bSPoonam Aggrwal mtspr(MAS3, _mas3); 39bc6bbd6bSPoonam Aggrwal mtspr(MAS7, _mas7); 40bc6bbd6bSPoonam Aggrwal 41bc6bbd6bSPoonam Aggrwal asm volatile("isync;msync;tlbwe;isync"); 42bc6bbd6bSPoonam Aggrwal 43689f00fcSPrabhakar Kushwaha #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) 44689f00fcSPrabhakar Kushwaha /* 45689f00fcSPrabhakar Kushwaha * TLB entry for debuggging in AS1 46689f00fcSPrabhakar Kushwaha * Create temporary TLB entry in AS0 to handle debug exception 47689f00fcSPrabhakar Kushwaha * As on debug exception MSR is cleared i.e. Address space is changed 48689f00fcSPrabhakar Kushwaha * to 0. A TLB entry (in AS0) is required to handle debug exception generated 49689f00fcSPrabhakar Kushwaha * in AS1. 50689f00fcSPrabhakar Kushwaha * 51689f00fcSPrabhakar Kushwaha * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 52689f00fcSPrabhakar Kushwaha * bacause flash's physical address is going to change as 53689f00fcSPrabhakar Kushwaha * CONFIG_SYS_FLASH_BASE_PHYS. 54689f00fcSPrabhakar Kushwaha */ 55689f00fcSPrabhakar Kushwaha _mas0 = MAS0_TLBSEL(1) | 56689f00fcSPrabhakar Kushwaha MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); 57689f00fcSPrabhakar Kushwaha _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | 58689f00fcSPrabhakar Kushwaha MAS1_TSIZE(BOOKE_PAGESZ_4M); 59689f00fcSPrabhakar Kushwaha _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); 60689f00fcSPrabhakar Kushwaha _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); 61689f00fcSPrabhakar Kushwaha _mas7 = FSL_BOOKE_MAS7(flash_phys); 62689f00fcSPrabhakar Kushwaha 63689f00fcSPrabhakar Kushwaha mtspr(MAS0, _mas0); 64689f00fcSPrabhakar Kushwaha mtspr(MAS1, _mas1); 65689f00fcSPrabhakar Kushwaha mtspr(MAS2, _mas2); 66689f00fcSPrabhakar Kushwaha mtspr(MAS3, _mas3); 67689f00fcSPrabhakar Kushwaha mtspr(MAS7, _mas7); 68689f00fcSPrabhakar Kushwaha 69689f00fcSPrabhakar Kushwaha asm volatile("isync;msync;tlbwe;isync"); 70689f00fcSPrabhakar Kushwaha #endif 71689f00fcSPrabhakar Kushwaha 72689f00fcSPrabhakar Kushwaha /* Change flash's physical address */ 73bc6bbd6bSPoonam Aggrwal out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); 74bc6bbd6bSPoonam Aggrwal out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); 75bc6bbd6bSPoonam Aggrwal out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); 76bc6bbd6bSPoonam Aggrwal 77bc6bbd6bSPoonam Aggrwal return ; 78bc6bbd6bSPoonam Aggrwal } 79bc6bbd6bSPoonam Aggrwal #endif 80bc6bbd6bSPoonam Aggrwal 81a47a12beSStefan Roese /* We run cpu_init_early_f in AS = 1 */ 82a47a12beSStefan Roese void cpu_init_early_f(void) 83a47a12beSStefan Roese { 84a47a12beSStefan Roese u32 mas0, mas1, mas2, mas3, mas7; 85a47a12beSStefan Roese int i; 86fb855f43SPoonam Aggrwal #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 87fb855f43SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 88fb855f43SPoonam Aggrwal #endif 8974fa22edSPrabhakar Kushwaha #ifdef CONFIG_A003399_NOR_WORKAROUND 90bc6bbd6bSPoonam Aggrwal ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 91cfee584eSPoonam Aggrwal u32 *dst, *src; 92bc6bbd6bSPoonam Aggrwal void (*setup_ifc_sram)(void); 93bc6bbd6bSPoonam Aggrwal #endif 94a47a12beSStefan Roese 95a47a12beSStefan Roese /* Pointer is writable since we allocated a register for it */ 96a47a12beSStefan Roese gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 97a47a12beSStefan Roese 98a47a12beSStefan Roese /* 99a47a12beSStefan Roese * Clear initial global data 100a47a12beSStefan Roese * we don't use memset so we can share this code with NAND_SPL 101a47a12beSStefan Roese */ 102a47a12beSStefan Roese for (i = 0; i < sizeof(gd_t); i++) 103a47a12beSStefan Roese ((char *)gd)[i] = 0; 104a47a12beSStefan Roese 105e8e6197aSPoonam Aggrwal mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); 106e8e6197aSPoonam Aggrwal mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); 107a47a12beSStefan Roese mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); 108a47a12beSStefan Roese mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); 109a47a12beSStefan Roese mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); 110a47a12beSStefan Roese 111a47a12beSStefan Roese write_tlb(mas0, mas1, mas2, mas3, mas7); 112a47a12beSStefan Roese 113fb855f43SPoonam Aggrwal /* 114fb855f43SPoonam Aggrwal * Work Around for IFC Erratum A-003549. This issue is P1010 115fb855f43SPoonam Aggrwal * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC 116fb855f43SPoonam Aggrwal * Hence specifically selecting CS3. 117fb855f43SPoonam Aggrwal */ 118fb855f43SPoonam Aggrwal #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 119fb855f43SPoonam Aggrwal setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); 120fb855f43SPoonam Aggrwal #endif 121fb855f43SPoonam Aggrwal 122a47a12beSStefan Roese init_laws(); 123bc6bbd6bSPoonam Aggrwal 124bc6bbd6bSPoonam Aggrwal /* 125bc6bbd6bSPoonam Aggrwal * Work Around for IFC Erratum A003399, issue will hit only when execution 126bc6bbd6bSPoonam Aggrwal * from NOR Flash 127bc6bbd6bSPoonam Aggrwal */ 12874fa22edSPrabhakar Kushwaha #ifdef CONFIG_A003399_NOR_WORKAROUND 129bc6bbd6bSPoonam Aggrwal #define SRAM_BASE_ADDR (0x00000000) 130bc6bbd6bSPoonam Aggrwal /* TLB for SRAM */ 131bc6bbd6bSPoonam Aggrwal mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); 132bc6bbd6bSPoonam Aggrwal mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | 133bc6bbd6bSPoonam Aggrwal MAS1_TSIZE(BOOKE_PAGESZ_1M); 134bc6bbd6bSPoonam Aggrwal mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); 135bc6bbd6bSPoonam Aggrwal mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); 136bc6bbd6bSPoonam Aggrwal mas7 = FSL_BOOKE_MAS7(0); 137bc6bbd6bSPoonam Aggrwal 138bc6bbd6bSPoonam Aggrwal write_tlb(mas0, mas1, mas2, mas3, mas7); 139bc6bbd6bSPoonam Aggrwal 140bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); 141bc6bbd6bSPoonam Aggrwal 142bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2errdis, 143bc6bbd6bSPoonam Aggrwal (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); 144bc6bbd6bSPoonam Aggrwal 145bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2ctl, 146bc6bbd6bSPoonam Aggrwal (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); 147bc6bbd6bSPoonam Aggrwal 148bc6bbd6bSPoonam Aggrwal /* 149bc6bbd6bSPoonam Aggrwal * Copy the code in setup_ifc to L2SRAM. Do a word copy 150bc6bbd6bSPoonam Aggrwal * because NOR Flash on P1010 does not support byte 151bc6bbd6bSPoonam Aggrwal * access (Erratum IFC-A002769) 152bc6bbd6bSPoonam Aggrwal */ 153bc6bbd6bSPoonam Aggrwal setup_ifc_sram = (void *)SRAM_BASE_ADDR; 154bc6bbd6bSPoonam Aggrwal dst = (u32 *) SRAM_BASE_ADDR; 155bc6bbd6bSPoonam Aggrwal src = (u32 *) setup_ifc; 156bc6bbd6bSPoonam Aggrwal for (i = 0; i < 1024; i++) 157cfee584eSPoonam Aggrwal *dst++ = *src++; 158bc6bbd6bSPoonam Aggrwal 159bc6bbd6bSPoonam Aggrwal setup_ifc_sram(); 160bc6bbd6bSPoonam Aggrwal 161bc6bbd6bSPoonam Aggrwal /* CLEANUP */ 162bc6bbd6bSPoonam Aggrwal clrbits_be32(&l2cache->l2ctl, 163bc6bbd6bSPoonam Aggrwal (MPC85xx_L2CTL_L2E | 164bc6bbd6bSPoonam Aggrwal MPC85xx_L2CTL_L2SRAM_ENTIRE)); 165bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2srbar0, 0x0); 166bc6bbd6bSPoonam Aggrwal #endif 167bc6bbd6bSPoonam Aggrwal 168e8e6197aSPoonam Aggrwal invalidate_tlb(1); 1697065b7d4SRuchika Gupta 1702a693605SPrabhakar Kushwaha #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \ 1712a693605SPrabhakar Kushwaha !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ 1722a693605SPrabhakar Kushwaha !defined(CONFIG_NAND_SPL) 173bd7c023eSPrabhakar Kushwaha disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); 174bd7c023eSPrabhakar Kushwaha #endif 175bd7c023eSPrabhakar Kushwaha 176a47a12beSStefan Roese init_tlbs(); 177a47a12beSStefan Roese } 178