1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <fm_eth.h> 35 #include <asm/io.h> 36 #include <asm/cache.h> 37 #include <asm/mmu.h> 38 #include <asm/fsl_law.h> 39 #include <asm/fsl_serdes.h> 40 #include <asm/fsl_srio.h> 41 #include <hwconfig.h> 42 #include <linux/compiler.h> 43 #include "mp.h" 44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 45 #include <nand.h> 46 #include <errno.h> 47 #endif 48 49 #include "../../../../drivers/block/fsl_sata.h" 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 #ifdef CONFIG_QE 54 extern qe_iop_conf_t qe_iop_conf_tab[]; 55 extern void qe_config_iopin(u8 port, u8 pin, int dir, 56 int open_drain, int assign); 57 extern void qe_init(uint qe_base); 58 extern void qe_reset(void); 59 60 static void config_qe_ioports(void) 61 { 62 u8 port, pin; 63 int dir, open_drain, assign; 64 int i; 65 66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 67 port = qe_iop_conf_tab[i].port; 68 pin = qe_iop_conf_tab[i].pin; 69 dir = qe_iop_conf_tab[i].dir; 70 open_drain = qe_iop_conf_tab[i].open_drain; 71 assign = qe_iop_conf_tab[i].assign; 72 qe_config_iopin(port, pin, dir, open_drain, assign); 73 } 74 } 75 #endif 76 77 #ifdef CONFIG_CPM2 78 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 79 { 80 int portnum; 81 82 for (portnum = 0; portnum < 4; portnum++) { 83 uint pmsk = 0, 84 ppar = 0, 85 psor = 0, 86 pdir = 0, 87 podr = 0, 88 pdat = 0; 89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 90 iop_conf_t *eiopc = iopc + 32; 91 uint msk = 1; 92 93 /* 94 * NOTE: 95 * index 0 refers to pin 31, 96 * index 31 refers to pin 0 97 */ 98 while (iopc < eiopc) { 99 if (iopc->conf) { 100 pmsk |= msk; 101 if (iopc->ppar) 102 ppar |= msk; 103 if (iopc->psor) 104 psor |= msk; 105 if (iopc->pdir) 106 pdir |= msk; 107 if (iopc->podr) 108 podr |= msk; 109 if (iopc->pdat) 110 pdat |= msk; 111 } 112 113 msk <<= 1; 114 iopc++; 115 } 116 117 if (pmsk != 0) { 118 volatile ioport_t *iop = ioport_addr (cpm, portnum); 119 uint tpmsk = ~pmsk; 120 121 /* 122 * the (somewhat confused) paragraph at the 123 * bottom of page 35-5 warns that there might 124 * be "unknown behaviour" when programming 125 * PSORx and PDIRx, if PPARx = 1, so I 126 * decided this meant I had to disable the 127 * dedicated function first, and enable it 128 * last. 129 */ 130 iop->ppar &= tpmsk; 131 iop->psor = (iop->psor & tpmsk) | psor; 132 iop->podr = (iop->podr & tpmsk) | podr; 133 iop->pdat = (iop->pdat & tpmsk) | pdat; 134 iop->pdir = (iop->pdir & tpmsk) | pdir; 135 iop->ppar |= ppar; 136 } 137 } 138 } 139 #endif 140 141 #ifdef CONFIG_SYS_FSL_CPC 142 static void enable_cpc(void) 143 { 144 int i; 145 u32 size = 0; 146 147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 148 149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 150 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 151 size += CPC_CFG0_SZ_K(cpccfg0); 152 #ifdef CONFIG_RAMBOOT_PBL 153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 154 /* find and disable LAW of SRAM */ 155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 156 157 if (law.index == -1) { 158 printf("\nFatal error happened\n"); 159 return; 160 } 161 disable_law(law.index); 162 163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 164 out_be32(&cpc->cpccsr0, 0); 165 out_be32(&cpc->cpcsrcr0, 0); 166 } 167 #endif 168 169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 171 #endif 172 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 174 #endif 175 176 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 177 /* Read back to sync write */ 178 in_be32(&cpc->cpccsr0); 179 180 } 181 182 printf("Corenet Platform Cache: %d KB enabled\n", size); 183 } 184 185 static void invalidate_cpc(void) 186 { 187 int i; 188 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 189 190 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 191 /* skip CPC when it used as all SRAM */ 192 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 193 continue; 194 /* Flash invalidate the CPC and clear all the locks */ 195 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 196 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 197 ; 198 } 199 } 200 #else 201 #define enable_cpc() 202 #define invalidate_cpc() 203 #endif /* CONFIG_SYS_FSL_CPC */ 204 205 /* 206 * Breathe some life into the CPU... 207 * 208 * Set up the memory map 209 * initialize a bunch of registers 210 */ 211 212 #ifdef CONFIG_FSL_CORENET 213 static void corenet_tb_init(void) 214 { 215 volatile ccsr_rcpm_t *rcpm = 216 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 217 volatile ccsr_pic_t *pic = 218 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 219 u32 whoami = in_be32(&pic->whoami); 220 221 /* Enable the timebase register for this core */ 222 out_be32(&rcpm->ctbenrl, (1 << whoami)); 223 } 224 #endif 225 226 void cpu_init_f (void) 227 { 228 extern void m8560_cpm_reset (void); 229 #ifdef CONFIG_SYS_DCSRBAR_PHYS 230 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 231 #endif 232 #if defined(CONFIG_SECURE_BOOT) 233 struct law_entry law; 234 #endif 235 #ifdef CONFIG_MPC8548 236 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 237 uint svr = get_svr(); 238 239 /* 240 * CPU2 errata workaround: A core hang possible while executing 241 * a msync instruction and a snoopable transaction from an I/O 242 * master tagged to make quick forward progress is present. 243 * Fixed in silicon rev 2.1. 244 */ 245 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 246 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 247 #endif 248 249 disable_tlb(14); 250 disable_tlb(15); 251 252 #if defined(CONFIG_SECURE_BOOT) 253 /* Disable the LAW created for NOR flash by the PBI commands */ 254 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 255 if (law.index != -1) 256 disable_law(law.index); 257 #endif 258 259 #ifdef CONFIG_CPM2 260 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 261 #endif 262 263 init_early_memctl_regs(); 264 265 #if defined(CONFIG_CPM2) 266 m8560_cpm_reset(); 267 #endif 268 #ifdef CONFIG_QE 269 /* Config QE ioports */ 270 config_qe_ioports(); 271 #endif 272 #if defined(CONFIG_FSL_DMA) 273 dma_init(); 274 #endif 275 #ifdef CONFIG_FSL_CORENET 276 corenet_tb_init(); 277 #endif 278 init_used_tlb_cams(); 279 280 /* Invalidate the CPC before DDR gets enabled */ 281 invalidate_cpc(); 282 283 #ifdef CONFIG_SYS_DCSRBAR_PHYS 284 /* set DCSRCR so that DCSR space is 1G */ 285 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 286 in_be32(&gur->dcsrcr); 287 #endif 288 289 } 290 291 /* Implement a dummy function for those platforms w/o SERDES */ 292 static void __fsl_serdes__init(void) 293 { 294 return ; 295 } 296 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 297 298 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 299 int enable_cluster_l2(void) 300 { 301 int i = 0; 302 u32 cluster; 303 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 304 struct ccsr_cluster_l2 __iomem *l2cache; 305 306 cluster = in_be32(&gur->tp_cluster[i].lower); 307 if (cluster & TP_CLUSTER_EOC) 308 return 0; 309 310 /* The first cache has already been set up, so skip it */ 311 i++; 312 313 /* Look through the remaining clusters, and set up their caches */ 314 do { 315 int j, cluster_valid = 0; 316 317 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 318 319 cluster = in_be32(&gur->tp_cluster[i].lower); 320 321 /* check that at least one core/accel is enabled in cluster */ 322 for (j = 0; j < 4; j++) { 323 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 324 u32 type = in_be32(&gur->tp_ityp[idx]); 325 326 if (type & TP_ITYP_AV) 327 cluster_valid = 1; 328 } 329 330 if (cluster_valid) { 331 /* set stash ID to (cluster) * 2 + 32 + 1 */ 332 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 333 334 printf("enable l2 for cluster %d %p\n", i, l2cache); 335 336 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 337 while ((in_be32(&l2cache->l2csr0) 338 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 339 ; 340 out_be32(&l2cache->l2csr0, L2CSR0_L2E); 341 } 342 i++; 343 } while (!(cluster & TP_CLUSTER_EOC)); 344 345 return 0; 346 } 347 #endif 348 349 /* 350 * Initialize L2 as cache. 351 * 352 * The newer 8548, etc, parts have twice as much cache, but 353 * use the same bit-encoding as the older 8555, etc, parts. 354 * 355 */ 356 int cpu_init_r(void) 357 { 358 __maybe_unused u32 svr = get_svr(); 359 #ifdef CONFIG_SYS_LBC_LCRR 360 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 361 #endif 362 #ifdef CONFIG_L2_CACHE 363 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 364 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 365 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 366 #endif 367 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 368 extern int spin_table_compat; 369 const char *spin; 370 #endif 371 372 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 373 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 374 /* 375 * CPU22 and NMG_CPU_A011 share the same workaround. 376 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 377 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 378 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 379 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 380 * be disabled by hwconfig with syntax: 381 * 382 * fsl_cpu_a011:disable 383 */ 384 extern int enable_cpu_a011_workaround; 385 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 386 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 387 #else 388 char buffer[HWCONFIG_BUFFER_SIZE]; 389 char *buf = NULL; 390 int n, res; 391 392 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 393 if (n > 0) 394 buf = buffer; 395 396 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 397 if (res > 0) 398 enable_cpu_a011_workaround = 0; 399 else { 400 if (n >= HWCONFIG_BUFFER_SIZE) { 401 printf("fsl_cpu_a011 was not found. hwconfig variable " 402 "may be too long\n"); 403 } 404 enable_cpu_a011_workaround = 405 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 406 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 407 } 408 #endif 409 if (enable_cpu_a011_workaround) { 410 flush_dcache(); 411 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 412 sync(); 413 } 414 #endif 415 416 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 417 spin = getenv("spin_table_compat"); 418 if (spin && (*spin == 'n')) 419 spin_table_compat = 0; 420 else 421 spin_table_compat = 1; 422 #endif 423 424 puts ("L2: "); 425 426 #if defined(CONFIG_L2_CACHE) 427 volatile uint cache_ctl; 428 uint ver; 429 u32 l2siz_field; 430 431 ver = SVR_SOC_VER(svr); 432 433 asm("msync;isync"); 434 cache_ctl = l2cache->l2ctl; 435 436 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 437 if (cache_ctl & MPC85xx_L2CTL_L2E) { 438 /* Clear L2 SRAM memory-mapped base address */ 439 out_be32(&l2cache->l2srbar0, 0x0); 440 out_be32(&l2cache->l2srbar1, 0x0); 441 442 /* set MBECCDIS=0, SBECCDIS=0 */ 443 clrbits_be32(&l2cache->l2errdis, 444 (MPC85xx_L2ERRDIS_MBECC | 445 MPC85xx_L2ERRDIS_SBECC)); 446 447 /* set L2E=0, L2SRAM=0 */ 448 clrbits_be32(&l2cache->l2ctl, 449 (MPC85xx_L2CTL_L2E | 450 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 451 } 452 #endif 453 454 l2siz_field = (cache_ctl >> 28) & 0x3; 455 456 switch (l2siz_field) { 457 case 0x0: 458 printf(" unknown size (0x%08x)\n", cache_ctl); 459 return -1; 460 break; 461 case 0x1: 462 if (ver == SVR_8540 || ver == SVR_8560 || 463 ver == SVR_8541 || ver == SVR_8555) { 464 puts("128 KB "); 465 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 466 cache_ctl = 0xc4000000; 467 } else { 468 puts("256 KB "); 469 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 470 } 471 break; 472 case 0x2: 473 if (ver == SVR_8540 || ver == SVR_8560 || 474 ver == SVR_8541 || ver == SVR_8555) { 475 puts("256 KB "); 476 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 477 cache_ctl = 0xc8000000; 478 } else { 479 puts ("512 KB "); 480 /* set L2E=1, L2I=1, & L2SRAM=0 */ 481 cache_ctl = 0xc0000000; 482 } 483 break; 484 case 0x3: 485 puts("1024 KB "); 486 /* set L2E=1, L2I=1, & L2SRAM=0 */ 487 cache_ctl = 0xc0000000; 488 break; 489 } 490 491 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 492 puts("already enabled"); 493 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 494 u32 l2srbar = l2cache->l2srbar0; 495 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 496 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 497 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 498 l2cache->l2srbar0 = l2srbar; 499 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 500 } 501 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 502 puts("\n"); 503 } else { 504 asm("msync;isync"); 505 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 506 asm("msync;isync"); 507 puts("enabled\n"); 508 } 509 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 510 if (SVR_SOC_VER(svr) == SVR_P2040) { 511 puts("N/A\n"); 512 goto skip_l2; 513 } 514 515 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 516 517 /* invalidate the L2 cache */ 518 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 519 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 520 ; 521 522 #ifdef CONFIG_SYS_CACHE_STASHING 523 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 524 mtspr(SPRN_L2CSR1, (32 + 1)); 525 #endif 526 527 /* enable the cache */ 528 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 529 530 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 531 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 532 ; 533 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 534 } 535 536 skip_l2: 537 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 538 if (l2cache->l2csr0 & L2CSR0_L2E) 539 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); 540 541 enable_cluster_l2(); 542 #else 543 puts("disabled\n"); 544 #endif 545 546 enable_cpc(); 547 548 /* needs to be in ram since code uses global static vars */ 549 fsl_serdes_init(); 550 551 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 552 if (IS_SVR_REV(svr, 1, 0)) { 553 int i; 554 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 555 556 for (i = 0; i < 12; i++) { 557 p += i + (i > 5 ? 11 : 0); 558 out_be32(p, 0x2); 559 } 560 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 561 out_be32(p, 0x34); 562 } 563 #endif 564 565 #ifdef CONFIG_SYS_SRIO 566 srio_init(); 567 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 568 char *s = getenv("bootmaster"); 569 if (s) { 570 if (!strcmp(s, "SRIO1")) { 571 srio_boot_master(1); 572 srio_boot_master_release_slave(1); 573 } 574 if (!strcmp(s, "SRIO2")) { 575 srio_boot_master(2); 576 srio_boot_master_release_slave(2); 577 } 578 } 579 #endif 580 #endif 581 582 #if defined(CONFIG_MP) 583 setup_mp(); 584 #endif 585 586 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 587 { 588 if (SVR_MAJ(svr) < 3) { 589 void *p; 590 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 591 setbits_be32(p, 1 << (31 - 14)); 592 } 593 } 594 #endif 595 596 #ifdef CONFIG_SYS_LBC_LCRR 597 /* 598 * Modify the CLKDIV field of LCRR register to improve the writing 599 * speed for NOR flash. 600 */ 601 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 602 __raw_readl(&lbc->lcrr); 603 isync(); 604 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 605 udelay(100); 606 #endif 607 #endif 608 609 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 610 { 611 ccsr_usb_phy_t *usb_phy1 = 612 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 613 out_be32(&usb_phy1->usb_enable_override, 614 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 615 } 616 #endif 617 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 618 { 619 ccsr_usb_phy_t *usb_phy2 = 620 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 621 out_be32(&usb_phy2->usb_enable_override, 622 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 623 } 624 #endif 625 626 #ifdef CONFIG_FMAN_ENET 627 fman_enet_init(); 628 #endif 629 630 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 631 /* 632 * For P1022/1013 Rev1.0 silicon, after power on SATA host 633 * controller is configured in legacy mode instead of the 634 * expected enterprise mode. Software needs to clear bit[28] 635 * of HControl register to change to enterprise mode from 636 * legacy mode. We assume that the controller is offline. 637 */ 638 if (IS_SVR_REV(svr, 1, 0) && 639 ((SVR_SOC_VER(svr) == SVR_P1022) || 640 (SVR_SOC_VER(svr) == SVR_P1013))) { 641 fsl_sata_reg_t *reg; 642 643 /* first SATA controller */ 644 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 645 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 646 647 /* second SATA controller */ 648 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 649 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 650 } 651 #endif 652 653 654 return 0; 655 } 656 657 extern void setup_ivors(void); 658 659 void arch_preboot_os(void) 660 { 661 u32 msr; 662 663 /* 664 * We are changing interrupt offsets and are about to boot the OS so 665 * we need to make sure we disable all async interrupts. EE is already 666 * disabled by the time we get called. 667 */ 668 msr = mfmsr(); 669 msr &= ~(MSR_ME|MSR_CE); 670 mtmsr(msr); 671 672 setup_ivors(); 673 } 674 675 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 676 int sata_initialize(void) 677 { 678 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 679 return __sata_initialize(); 680 681 return 1; 682 } 683 #endif 684 685 void cpu_secondary_init_r(void) 686 { 687 #ifdef CONFIG_QE 688 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 689 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 690 int ret; 691 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 692 693 /* load QE firmware from NAND flash to DDR first */ 694 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 695 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 696 697 if (ret && ret == -EUCLEAN) { 698 printf ("NAND read for QE firmware at offset %x failed %d\n", 699 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 700 } 701 #endif 702 qe_init(qe_base); 703 qe_reset(); 704 #endif 705 } 706