1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 31 #include <nand.h> 32 #include <errno.h> 33 #endif 34 35 #include "../../../../drivers/block/fsl_sata.h" 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 #ifdef CONFIG_QE 40 extern qe_iop_conf_t qe_iop_conf_tab[]; 41 extern void qe_config_iopin(u8 port, u8 pin, int dir, 42 int open_drain, int assign); 43 extern void qe_init(uint qe_base); 44 extern void qe_reset(void); 45 46 static void config_qe_ioports(void) 47 { 48 u8 port, pin; 49 int dir, open_drain, assign; 50 int i; 51 52 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 53 port = qe_iop_conf_tab[i].port; 54 pin = qe_iop_conf_tab[i].pin; 55 dir = qe_iop_conf_tab[i].dir; 56 open_drain = qe_iop_conf_tab[i].open_drain; 57 assign = qe_iop_conf_tab[i].assign; 58 qe_config_iopin(port, pin, dir, open_drain, assign); 59 } 60 } 61 #endif 62 63 #ifdef CONFIG_CPM2 64 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 65 { 66 int portnum; 67 68 for (portnum = 0; portnum < 4; portnum++) { 69 uint pmsk = 0, 70 ppar = 0, 71 psor = 0, 72 pdir = 0, 73 podr = 0, 74 pdat = 0; 75 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 76 iop_conf_t *eiopc = iopc + 32; 77 uint msk = 1; 78 79 /* 80 * NOTE: 81 * index 0 refers to pin 31, 82 * index 31 refers to pin 0 83 */ 84 while (iopc < eiopc) { 85 if (iopc->conf) { 86 pmsk |= msk; 87 if (iopc->ppar) 88 ppar |= msk; 89 if (iopc->psor) 90 psor |= msk; 91 if (iopc->pdir) 92 pdir |= msk; 93 if (iopc->podr) 94 podr |= msk; 95 if (iopc->pdat) 96 pdat |= msk; 97 } 98 99 msk <<= 1; 100 iopc++; 101 } 102 103 if (pmsk != 0) { 104 volatile ioport_t *iop = ioport_addr (cpm, portnum); 105 uint tpmsk = ~pmsk; 106 107 /* 108 * the (somewhat confused) paragraph at the 109 * bottom of page 35-5 warns that there might 110 * be "unknown behaviour" when programming 111 * PSORx and PDIRx, if PPARx = 1, so I 112 * decided this meant I had to disable the 113 * dedicated function first, and enable it 114 * last. 115 */ 116 iop->ppar &= tpmsk; 117 iop->psor = (iop->psor & tpmsk) | psor; 118 iop->podr = (iop->podr & tpmsk) | podr; 119 iop->pdat = (iop->pdat & tpmsk) | pdat; 120 iop->pdir = (iop->pdir & tpmsk) | pdir; 121 iop->ppar |= ppar; 122 } 123 } 124 } 125 #endif 126 127 #ifdef CONFIG_SYS_FSL_CPC 128 static void enable_cpc(void) 129 { 130 int i; 131 u32 size = 0; 132 133 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 134 135 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 136 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 137 size += CPC_CFG0_SZ_K(cpccfg0); 138 #ifdef CONFIG_RAMBOOT_PBL 139 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 140 /* find and disable LAW of SRAM */ 141 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 142 143 if (law.index == -1) { 144 printf("\nFatal error happened\n"); 145 return; 146 } 147 disable_law(law.index); 148 149 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 150 out_be32(&cpc->cpccsr0, 0); 151 out_be32(&cpc->cpcsrcr0, 0); 152 } 153 #endif 154 155 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 156 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 157 #endif 158 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 159 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 160 #endif 161 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 162 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 163 #endif 164 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 165 if (has_erratum_a006379()) { 166 setbits_be32(&cpc->cpchdbcr0, 167 CPC_HDBCR0_SPLRU_LEVEL_EN); 168 } 169 #endif 170 171 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 172 /* Read back to sync write */ 173 in_be32(&cpc->cpccsr0); 174 175 } 176 177 puts("Corenet Platform Cache: "); 178 print_size(size * 1024, " enabled\n"); 179 } 180 181 static void invalidate_cpc(void) 182 { 183 int i; 184 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 185 186 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 187 /* skip CPC when it used as all SRAM */ 188 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 189 continue; 190 /* Flash invalidate the CPC and clear all the locks */ 191 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 192 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 193 ; 194 } 195 } 196 #else 197 #define enable_cpc() 198 #define invalidate_cpc() 199 #endif /* CONFIG_SYS_FSL_CPC */ 200 201 /* 202 * Breathe some life into the CPU... 203 * 204 * Set up the memory map 205 * initialize a bunch of registers 206 */ 207 208 #ifdef CONFIG_FSL_CORENET 209 static void corenet_tb_init(void) 210 { 211 volatile ccsr_rcpm_t *rcpm = 212 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 213 volatile ccsr_pic_t *pic = 214 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 215 u32 whoami = in_be32(&pic->whoami); 216 217 /* Enable the timebase register for this core */ 218 out_be32(&rcpm->ctbenrl, (1 << whoami)); 219 } 220 #endif 221 222 void cpu_init_f (void) 223 { 224 extern void m8560_cpm_reset (void); 225 #ifdef CONFIG_SYS_DCSRBAR_PHYS 226 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 227 #endif 228 #if defined(CONFIG_SECURE_BOOT) 229 struct law_entry law; 230 #endif 231 #ifdef CONFIG_MPC8548 232 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 233 uint svr = get_svr(); 234 235 /* 236 * CPU2 errata workaround: A core hang possible while executing 237 * a msync instruction and a snoopable transaction from an I/O 238 * master tagged to make quick forward progress is present. 239 * Fixed in silicon rev 2.1. 240 */ 241 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 242 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 243 #endif 244 245 disable_tlb(14); 246 disable_tlb(15); 247 248 #if defined(CONFIG_SECURE_BOOT) 249 /* Disable the LAW created for NOR flash by the PBI commands */ 250 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 251 if (law.index != -1) 252 disable_law(law.index); 253 #endif 254 255 #ifdef CONFIG_CPM2 256 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 257 #endif 258 259 init_early_memctl_regs(); 260 261 #if defined(CONFIG_CPM2) 262 m8560_cpm_reset(); 263 #endif 264 #ifdef CONFIG_QE 265 /* Config QE ioports */ 266 config_qe_ioports(); 267 #endif 268 #if defined(CONFIG_FSL_DMA) 269 dma_init(); 270 #endif 271 #ifdef CONFIG_FSL_CORENET 272 corenet_tb_init(); 273 #endif 274 init_used_tlb_cams(); 275 276 /* Invalidate the CPC before DDR gets enabled */ 277 invalidate_cpc(); 278 279 #ifdef CONFIG_SYS_DCSRBAR_PHYS 280 /* set DCSRCR so that DCSR space is 1G */ 281 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 282 in_be32(&gur->dcsrcr); 283 #endif 284 285 } 286 287 /* Implement a dummy function for those platforms w/o SERDES */ 288 static void __fsl_serdes__init(void) 289 { 290 return ; 291 } 292 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 293 294 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 295 int enable_cluster_l2(void) 296 { 297 int i = 0; 298 u32 cluster; 299 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 300 struct ccsr_cluster_l2 __iomem *l2cache; 301 302 cluster = in_be32(&gur->tp_cluster[i].lower); 303 if (cluster & TP_CLUSTER_EOC) 304 return 0; 305 306 /* The first cache has already been set up, so skip it */ 307 i++; 308 309 /* Look through the remaining clusters, and set up their caches */ 310 do { 311 int j, cluster_valid = 0; 312 313 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 314 315 cluster = in_be32(&gur->tp_cluster[i].lower); 316 317 /* check that at least one core/accel is enabled in cluster */ 318 for (j = 0; j < 4; j++) { 319 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 320 u32 type = in_be32(&gur->tp_ityp[idx]); 321 322 if (type & TP_ITYP_AV) 323 cluster_valid = 1; 324 } 325 326 if (cluster_valid) { 327 /* set stash ID to (cluster) * 2 + 32 + 1 */ 328 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 329 330 printf("enable l2 for cluster %d %p\n", i, l2cache); 331 332 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 333 while ((in_be32(&l2cache->l2csr0) 334 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 335 ; 336 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 337 } 338 i++; 339 } while (!(cluster & TP_CLUSTER_EOC)); 340 341 return 0; 342 } 343 #endif 344 345 /* 346 * Initialize L2 as cache. 347 * 348 * The newer 8548, etc, parts have twice as much cache, but 349 * use the same bit-encoding as the older 8555, etc, parts. 350 * 351 */ 352 int cpu_init_r(void) 353 { 354 __maybe_unused u32 svr = get_svr(); 355 #ifdef CONFIG_SYS_LBC_LCRR 356 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 357 #endif 358 #ifdef CONFIG_L2_CACHE 359 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 360 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 361 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 362 #endif 363 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 364 extern int spin_table_compat; 365 const char *spin; 366 #endif 367 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 368 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 369 #endif 370 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 371 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 372 /* 373 * CPU22 and NMG_CPU_A011 share the same workaround. 374 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 375 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 376 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 377 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 378 * be disabled by hwconfig with syntax: 379 * 380 * fsl_cpu_a011:disable 381 */ 382 extern int enable_cpu_a011_workaround; 383 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 384 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 385 #else 386 char buffer[HWCONFIG_BUFFER_SIZE]; 387 char *buf = NULL; 388 int n, res; 389 390 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 391 if (n > 0) 392 buf = buffer; 393 394 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 395 if (res > 0) 396 enable_cpu_a011_workaround = 0; 397 else { 398 if (n >= HWCONFIG_BUFFER_SIZE) { 399 printf("fsl_cpu_a011 was not found. hwconfig variable " 400 "may be too long\n"); 401 } 402 enable_cpu_a011_workaround = 403 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 404 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 405 } 406 #endif 407 if (enable_cpu_a011_workaround) { 408 flush_dcache(); 409 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 410 sync(); 411 } 412 #endif 413 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 414 /* 415 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 416 * in write shadow mode. Checking DCWS before setting SPR 976. 417 */ 418 if (mfspr(L1CSR2) & L1CSR2_DCWS) 419 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 420 #endif 421 422 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 423 spin = getenv("spin_table_compat"); 424 if (spin && (*spin == 'n')) 425 spin_table_compat = 0; 426 else 427 spin_table_compat = 1; 428 #endif 429 430 puts ("L2: "); 431 432 #if defined(CONFIG_L2_CACHE) 433 volatile uint cache_ctl; 434 uint ver; 435 u32 l2siz_field; 436 437 ver = SVR_SOC_VER(svr); 438 439 asm("msync;isync"); 440 cache_ctl = l2cache->l2ctl; 441 442 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 443 if (cache_ctl & MPC85xx_L2CTL_L2E) { 444 /* Clear L2 SRAM memory-mapped base address */ 445 out_be32(&l2cache->l2srbar0, 0x0); 446 out_be32(&l2cache->l2srbar1, 0x0); 447 448 /* set MBECCDIS=0, SBECCDIS=0 */ 449 clrbits_be32(&l2cache->l2errdis, 450 (MPC85xx_L2ERRDIS_MBECC | 451 MPC85xx_L2ERRDIS_SBECC)); 452 453 /* set L2E=0, L2SRAM=0 */ 454 clrbits_be32(&l2cache->l2ctl, 455 (MPC85xx_L2CTL_L2E | 456 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 457 } 458 #endif 459 460 l2siz_field = (cache_ctl >> 28) & 0x3; 461 462 switch (l2siz_field) { 463 case 0x0: 464 printf(" unknown size (0x%08x)\n", cache_ctl); 465 return -1; 466 break; 467 case 0x1: 468 if (ver == SVR_8540 || ver == SVR_8560 || 469 ver == SVR_8541 || ver == SVR_8555) { 470 puts("128 KiB "); 471 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 472 cache_ctl = 0xc4000000; 473 } else { 474 puts("256 KiB "); 475 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 476 } 477 break; 478 case 0x2: 479 if (ver == SVR_8540 || ver == SVR_8560 || 480 ver == SVR_8541 || ver == SVR_8555) { 481 puts("256 KiB "); 482 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 483 cache_ctl = 0xc8000000; 484 } else { 485 puts("512 KiB "); 486 /* set L2E=1, L2I=1, & L2SRAM=0 */ 487 cache_ctl = 0xc0000000; 488 } 489 break; 490 case 0x3: 491 puts("1024 KiB "); 492 /* set L2E=1, L2I=1, & L2SRAM=0 */ 493 cache_ctl = 0xc0000000; 494 break; 495 } 496 497 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 498 puts("already enabled"); 499 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 500 u32 l2srbar = l2cache->l2srbar0; 501 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 502 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 503 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 504 l2cache->l2srbar0 = l2srbar; 505 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 506 } 507 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 508 puts("\n"); 509 } else { 510 asm("msync;isync"); 511 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 512 asm("msync;isync"); 513 puts("enabled\n"); 514 } 515 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 516 if (SVR_SOC_VER(svr) == SVR_P2040) { 517 puts("N/A\n"); 518 goto skip_l2; 519 } 520 521 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 522 523 /* invalidate the L2 cache */ 524 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 525 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 526 ; 527 528 #ifdef CONFIG_SYS_CACHE_STASHING 529 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 530 mtspr(SPRN_L2CSR1, (32 + 1)); 531 #endif 532 533 /* enable the cache */ 534 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 535 536 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 537 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 538 ; 539 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 540 } 541 542 skip_l2: 543 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 544 if (l2cache->l2csr0 & L2CSR0_L2E) 545 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 546 " enabled\n"); 547 548 enable_cluster_l2(); 549 #else 550 puts("disabled\n"); 551 #endif 552 553 enable_cpc(); 554 555 #ifndef CONFIG_SYS_FSL_NO_SERDES 556 /* needs to be in ram since code uses global static vars */ 557 fsl_serdes_init(); 558 #endif 559 560 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 561 #define MCFGR_AXIPIPE 0x000000f0 562 if (IS_SVR_REV(svr, 1, 0)) 563 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 564 #endif 565 566 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 567 if (IS_SVR_REV(svr, 1, 0)) { 568 int i; 569 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 570 571 for (i = 0; i < 12; i++) { 572 p += i + (i > 5 ? 11 : 0); 573 out_be32(p, 0x2); 574 } 575 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 576 out_be32(p, 0x34); 577 } 578 #endif 579 580 #ifdef CONFIG_SYS_SRIO 581 srio_init(); 582 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 583 char *s = getenv("bootmaster"); 584 if (s) { 585 if (!strcmp(s, "SRIO1")) { 586 srio_boot_master(1); 587 srio_boot_master_release_slave(1); 588 } 589 if (!strcmp(s, "SRIO2")) { 590 srio_boot_master(2); 591 srio_boot_master_release_slave(2); 592 } 593 } 594 #endif 595 #endif 596 597 #if defined(CONFIG_MP) 598 setup_mp(); 599 #endif 600 601 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 602 { 603 if (SVR_MAJ(svr) < 3) { 604 void *p; 605 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 606 setbits_be32(p, 1 << (31 - 14)); 607 } 608 } 609 #endif 610 611 #ifdef CONFIG_SYS_LBC_LCRR 612 /* 613 * Modify the CLKDIV field of LCRR register to improve the writing 614 * speed for NOR flash. 615 */ 616 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 617 __raw_readl(&lbc->lcrr); 618 isync(); 619 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 620 udelay(100); 621 #endif 622 #endif 623 624 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 625 { 626 struct ccsr_usb_phy __iomem *usb_phy1 = 627 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 628 out_be32(&usb_phy1->usb_enable_override, 629 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 630 } 631 #endif 632 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 633 { 634 struct ccsr_usb_phy __iomem *usb_phy2 = 635 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 636 out_be32(&usb_phy2->usb_enable_override, 637 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 638 } 639 #endif 640 641 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 642 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 643 * multi-bit ECC errors which has impact on performance, so software 644 * should disable all ECC reporting from USB1 and USB2. 645 */ 646 if (IS_SVR_REV(get_svr(), 1, 0)) { 647 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 648 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 649 setbits_be32(&dcfg->ecccr1, 650 (DCSR_DCFG_ECC_DISABLE_USB1 | 651 DCSR_DCFG_ECC_DISABLE_USB2)); 652 } 653 #endif 654 655 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 656 struct ccsr_usb_phy __iomem *usb_phy = 657 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 658 setbits_be32(&usb_phy->pllprg[1], 659 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 660 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 661 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 662 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 663 setbits_be32(&usb_phy->port1.ctrl, 664 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 665 setbits_be32(&usb_phy->port1.drvvbuscfg, 666 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 667 setbits_be32(&usb_phy->port1.pwrfltcfg, 668 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 669 setbits_be32(&usb_phy->port2.ctrl, 670 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 671 setbits_be32(&usb_phy->port2.drvvbuscfg, 672 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 673 setbits_be32(&usb_phy->port2.pwrfltcfg, 674 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 675 #endif 676 677 #ifdef CONFIG_FMAN_ENET 678 fman_enet_init(); 679 #endif 680 681 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 682 /* 683 * For P1022/1013 Rev1.0 silicon, after power on SATA host 684 * controller is configured in legacy mode instead of the 685 * expected enterprise mode. Software needs to clear bit[28] 686 * of HControl register to change to enterprise mode from 687 * legacy mode. We assume that the controller is offline. 688 */ 689 if (IS_SVR_REV(svr, 1, 0) && 690 ((SVR_SOC_VER(svr) == SVR_P1022) || 691 (SVR_SOC_VER(svr) == SVR_P1013))) { 692 fsl_sata_reg_t *reg; 693 694 /* first SATA controller */ 695 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 696 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 697 698 /* second SATA controller */ 699 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 700 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 701 } 702 #endif 703 704 705 return 0; 706 } 707 708 extern void setup_ivors(void); 709 710 void arch_preboot_os(void) 711 { 712 u32 msr; 713 714 /* 715 * We are changing interrupt offsets and are about to boot the OS so 716 * we need to make sure we disable all async interrupts. EE is already 717 * disabled by the time we get called. 718 */ 719 msr = mfmsr(); 720 msr &= ~(MSR_ME|MSR_CE); 721 mtmsr(msr); 722 723 setup_ivors(); 724 } 725 726 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 727 int sata_initialize(void) 728 { 729 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 730 return __sata_initialize(); 731 732 return 1; 733 } 734 #endif 735 736 void cpu_secondary_init_r(void) 737 { 738 #ifdef CONFIG_QE 739 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 740 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 741 int ret; 742 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 743 744 /* load QE firmware from NAND flash to DDR first */ 745 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 746 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 747 748 if (ret && ret == -EUCLEAN) { 749 printf ("NAND read for QE firmware at offset %x failed %d\n", 750 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 751 } 752 #endif 753 qe_init(qe_base); 754 qe_reset(); 755 #endif 756 } 757