1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 31 #include <nand.h> 32 #include <errno.h> 33 #endif 34 35 #include "../../../../drivers/block/fsl_sata.h" 36 #ifdef CONFIG_U_QE 37 #include "../../../../drivers/qe/qe.h" 38 #endif 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 43 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 44 { 45 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 46 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 47 48 /* Increase Disconnect Threshold by 50mV */ 49 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 50 INC_DCNT_THRESHOLD_50MV; 51 /* Enable programming of USB High speed Disconnect threshold */ 52 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 53 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 54 55 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 56 /* Increase Disconnect Threshold by 50mV */ 57 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 58 INC_DCNT_THRESHOLD_50MV; 59 /* Enable programming of USB High speed Disconnect threshold */ 60 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 61 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 62 #else 63 64 u32 temp = 0; 65 u32 status = in_be32(&usb_phy->status1); 66 67 u32 squelch_prog_rd_0_2 = 68 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 69 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 70 71 u32 squelch_prog_rd_3_5 = 72 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 73 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 74 75 setbits_be32(&usb_phy->config1, 76 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 77 setbits_be32(&usb_phy->config2, 78 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 79 80 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 81 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 82 83 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 84 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 85 #endif 86 } 87 #endif 88 89 90 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 91 extern qe_iop_conf_t qe_iop_conf_tab[]; 92 extern void qe_config_iopin(u8 port, u8 pin, int dir, 93 int open_drain, int assign); 94 extern void qe_init(uint qe_base); 95 extern void qe_reset(void); 96 97 static void config_qe_ioports(void) 98 { 99 u8 port, pin; 100 int dir, open_drain, assign; 101 int i; 102 103 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 104 port = qe_iop_conf_tab[i].port; 105 pin = qe_iop_conf_tab[i].pin; 106 dir = qe_iop_conf_tab[i].dir; 107 open_drain = qe_iop_conf_tab[i].open_drain; 108 assign = qe_iop_conf_tab[i].assign; 109 qe_config_iopin(port, pin, dir, open_drain, assign); 110 } 111 } 112 #endif 113 114 #ifdef CONFIG_CPM2 115 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 116 { 117 int portnum; 118 119 for (portnum = 0; portnum < 4; portnum++) { 120 uint pmsk = 0, 121 ppar = 0, 122 psor = 0, 123 pdir = 0, 124 podr = 0, 125 pdat = 0; 126 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 127 iop_conf_t *eiopc = iopc + 32; 128 uint msk = 1; 129 130 /* 131 * NOTE: 132 * index 0 refers to pin 31, 133 * index 31 refers to pin 0 134 */ 135 while (iopc < eiopc) { 136 if (iopc->conf) { 137 pmsk |= msk; 138 if (iopc->ppar) 139 ppar |= msk; 140 if (iopc->psor) 141 psor |= msk; 142 if (iopc->pdir) 143 pdir |= msk; 144 if (iopc->podr) 145 podr |= msk; 146 if (iopc->pdat) 147 pdat |= msk; 148 } 149 150 msk <<= 1; 151 iopc++; 152 } 153 154 if (pmsk != 0) { 155 volatile ioport_t *iop = ioport_addr (cpm, portnum); 156 uint tpmsk = ~pmsk; 157 158 /* 159 * the (somewhat confused) paragraph at the 160 * bottom of page 35-5 warns that there might 161 * be "unknown behaviour" when programming 162 * PSORx and PDIRx, if PPARx = 1, so I 163 * decided this meant I had to disable the 164 * dedicated function first, and enable it 165 * last. 166 */ 167 iop->ppar &= tpmsk; 168 iop->psor = (iop->psor & tpmsk) | psor; 169 iop->podr = (iop->podr & tpmsk) | podr; 170 iop->pdat = (iop->pdat & tpmsk) | pdat; 171 iop->pdir = (iop->pdir & tpmsk) | pdir; 172 iop->ppar |= ppar; 173 } 174 } 175 } 176 #endif 177 178 #ifdef CONFIG_SYS_FSL_CPC 179 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 180 static void disable_cpc_sram(void) 181 { 182 int i; 183 184 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 185 186 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 187 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 188 /* find and disable LAW of SRAM */ 189 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 190 191 if (law.index == -1) { 192 printf("\nFatal error happened\n"); 193 return; 194 } 195 disable_law(law.index); 196 197 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 198 out_be32(&cpc->cpccsr0, 0); 199 out_be32(&cpc->cpcsrcr0, 0); 200 } 201 } 202 } 203 #endif 204 205 static void enable_cpc(void) 206 { 207 int i; 208 u32 size = 0; 209 210 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 211 212 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 213 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 214 size += CPC_CFG0_SZ_K(cpccfg0); 215 216 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 217 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 218 #endif 219 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 220 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 221 #endif 222 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 223 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 224 #endif 225 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 226 if (has_erratum_a006379()) { 227 setbits_be32(&cpc->cpchdbcr0, 228 CPC_HDBCR0_SPLRU_LEVEL_EN); 229 } 230 #endif 231 232 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 233 /* Read back to sync write */ 234 in_be32(&cpc->cpccsr0); 235 236 } 237 238 puts("Corenet Platform Cache: "); 239 print_size(size * 1024, " enabled\n"); 240 } 241 242 static void invalidate_cpc(void) 243 { 244 int i; 245 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 246 247 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 248 /* skip CPC when it used as all SRAM */ 249 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 250 continue; 251 /* Flash invalidate the CPC and clear all the locks */ 252 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 253 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 254 ; 255 } 256 } 257 #else 258 #define enable_cpc() 259 #define invalidate_cpc() 260 #endif /* CONFIG_SYS_FSL_CPC */ 261 262 /* 263 * Breathe some life into the CPU... 264 * 265 * Set up the memory map 266 * initialize a bunch of registers 267 */ 268 269 #ifdef CONFIG_FSL_CORENET 270 static void corenet_tb_init(void) 271 { 272 volatile ccsr_rcpm_t *rcpm = 273 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 274 volatile ccsr_pic_t *pic = 275 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 276 u32 whoami = in_be32(&pic->whoami); 277 278 /* Enable the timebase register for this core */ 279 out_be32(&rcpm->ctbenrl, (1 << whoami)); 280 } 281 #endif 282 283 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 284 void fsl_erratum_a007212_workaround(void) 285 { 286 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 287 u32 ddr_pll_ratio; 288 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 289 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 290 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 291 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 292 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 293 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 294 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 295 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 296 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 297 #endif 298 #endif 299 /* 300 * Even this workaround applies to selected version of SoCs, it is 301 * safe to apply to all versions, with the limitation of odd ratios. 302 * If RCW has disabled DDR PLL, we have to apply this workaround, 303 * otherwise DDR will not work. 304 */ 305 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 306 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 307 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 308 /* check if RCW sets ratio to 0, required by this workaround */ 309 if (ddr_pll_ratio != 0) 310 return; 311 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 312 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 313 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 314 /* check if reserved bits have the desired ratio */ 315 if (ddr_pll_ratio == 0) { 316 printf("Error: Unknown DDR PLL ratio!\n"); 317 return; 318 } 319 ddr_pll_ratio >>= 1; 320 321 setbits_be32(plldadcr1, 0x02000001); 322 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 323 setbits_be32(plldadcr2, 0x02000001); 324 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 325 setbits_be32(plldadcr3, 0x02000001); 326 #endif 327 #endif 328 setbits_be32(dpdovrcr4, 0xe0000000); 329 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 330 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 331 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 332 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 333 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 334 #endif 335 #endif 336 udelay(100); 337 clrbits_be32(plldadcr1, 0x02000001); 338 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 339 clrbits_be32(plldadcr2, 0x02000001); 340 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 341 clrbits_be32(plldadcr3, 0x02000001); 342 #endif 343 #endif 344 clrbits_be32(dpdovrcr4, 0xe0000000); 345 } 346 #endif 347 348 void cpu_init_f (void) 349 { 350 extern void m8560_cpm_reset (void); 351 #ifdef CONFIG_SYS_DCSRBAR_PHYS 352 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 353 gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 354 #endif 355 #if defined(CONFIG_SECURE_BOOT) 356 struct law_entry law; 357 #endif 358 #ifdef CONFIG_MPC8548 359 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 360 uint svr = get_svr(); 361 362 /* 363 * CPU2 errata workaround: A core hang possible while executing 364 * a msync instruction and a snoopable transaction from an I/O 365 * master tagged to make quick forward progress is present. 366 * Fixed in silicon rev 2.1. 367 */ 368 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 369 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 370 #endif 371 372 disable_tlb(14); 373 disable_tlb(15); 374 375 #if defined(CONFIG_SECURE_BOOT) 376 /* Disable the LAW created for NOR flash by the PBI commands */ 377 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 378 if (law.index != -1) 379 disable_law(law.index); 380 381 #if defined(CONFIG_SYS_CPC_REINIT_F) 382 disable_cpc_sram(); 383 #endif 384 #endif 385 386 #ifdef CONFIG_CPM2 387 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 388 #endif 389 390 init_early_memctl_regs(); 391 392 #if defined(CONFIG_CPM2) 393 m8560_cpm_reset(); 394 #endif 395 396 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 397 /* Config QE ioports */ 398 config_qe_ioports(); 399 #endif 400 401 #if defined(CONFIG_FSL_DMA) 402 dma_init(); 403 #endif 404 #ifdef CONFIG_FSL_CORENET 405 corenet_tb_init(); 406 #endif 407 init_used_tlb_cams(); 408 409 /* Invalidate the CPC before DDR gets enabled */ 410 invalidate_cpc(); 411 412 #ifdef CONFIG_SYS_DCSRBAR_PHYS 413 /* set DCSRCR so that DCSR space is 1G */ 414 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 415 in_be32(&gur->dcsrcr); 416 #endif 417 418 #ifdef CONFIG_SYS_DCSRBAR_PHYS 419 #ifdef CONFIG_DEEP_SLEEP 420 /* disable the console if boot from deep sleep */ 421 if (in_be32(&gur->scrtsr[0]) & (1 << 3)) 422 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 423 #endif 424 #endif 425 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 426 fsl_erratum_a007212_workaround(); 427 #endif 428 429 } 430 431 /* Implement a dummy function for those platforms w/o SERDES */ 432 static void __fsl_serdes__init(void) 433 { 434 return ; 435 } 436 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 437 438 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 439 int enable_cluster_l2(void) 440 { 441 int i = 0; 442 u32 cluster; 443 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 444 struct ccsr_cluster_l2 __iomem *l2cache; 445 446 cluster = in_be32(&gur->tp_cluster[i].lower); 447 if (cluster & TP_CLUSTER_EOC) 448 return 0; 449 450 /* The first cache has already been set up, so skip it */ 451 i++; 452 453 /* Look through the remaining clusters, and set up their caches */ 454 do { 455 int j, cluster_valid = 0; 456 457 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 458 459 cluster = in_be32(&gur->tp_cluster[i].lower); 460 461 /* check that at least one core/accel is enabled in cluster */ 462 for (j = 0; j < 4; j++) { 463 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 464 u32 type = in_be32(&gur->tp_ityp[idx]); 465 466 if (type & TP_ITYP_AV) 467 cluster_valid = 1; 468 } 469 470 if (cluster_valid) { 471 /* set stash ID to (cluster) * 2 + 32 + 1 */ 472 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 473 474 printf("enable l2 for cluster %d %p\n", i, l2cache); 475 476 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 477 while ((in_be32(&l2cache->l2csr0) 478 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 479 ; 480 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 481 } 482 i++; 483 } while (!(cluster & TP_CLUSTER_EOC)); 484 485 return 0; 486 } 487 #endif 488 489 /* 490 * Initialize L2 as cache. 491 * 492 * The newer 8548, etc, parts have twice as much cache, but 493 * use the same bit-encoding as the older 8555, etc, parts. 494 * 495 */ 496 int cpu_init_r(void) 497 { 498 __maybe_unused u32 svr = get_svr(); 499 #ifdef CONFIG_SYS_LBC_LCRR 500 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 501 #endif 502 #ifdef CONFIG_L2_CACHE 503 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 504 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 505 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 506 #endif 507 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 508 extern int spin_table_compat; 509 const char *spin; 510 #endif 511 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 512 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 513 #endif 514 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 515 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 516 /* 517 * CPU22 and NMG_CPU_A011 share the same workaround. 518 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 519 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 520 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 521 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 522 * be disabled by hwconfig with syntax: 523 * 524 * fsl_cpu_a011:disable 525 */ 526 extern int enable_cpu_a011_workaround; 527 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 528 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 529 #else 530 char buffer[HWCONFIG_BUFFER_SIZE]; 531 char *buf = NULL; 532 int n, res; 533 534 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 535 if (n > 0) 536 buf = buffer; 537 538 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 539 if (res > 0) 540 enable_cpu_a011_workaround = 0; 541 else { 542 if (n >= HWCONFIG_BUFFER_SIZE) { 543 printf("fsl_cpu_a011 was not found. hwconfig variable " 544 "may be too long\n"); 545 } 546 enable_cpu_a011_workaround = 547 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 548 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 549 } 550 #endif 551 if (enable_cpu_a011_workaround) { 552 flush_dcache(); 553 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 554 sync(); 555 } 556 #endif 557 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 558 /* 559 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 560 * in write shadow mode. Checking DCWS before setting SPR 976. 561 */ 562 if (mfspr(L1CSR2) & L1CSR2_DCWS) 563 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 564 #endif 565 566 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 567 spin = getenv("spin_table_compat"); 568 if (spin && (*spin == 'n')) 569 spin_table_compat = 0; 570 else 571 spin_table_compat = 1; 572 #endif 573 574 puts ("L2: "); 575 576 #if defined(CONFIG_L2_CACHE) 577 volatile uint cache_ctl; 578 uint ver; 579 u32 l2siz_field; 580 581 ver = SVR_SOC_VER(svr); 582 583 asm("msync;isync"); 584 cache_ctl = l2cache->l2ctl; 585 586 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 587 if (cache_ctl & MPC85xx_L2CTL_L2E) { 588 /* Clear L2 SRAM memory-mapped base address */ 589 out_be32(&l2cache->l2srbar0, 0x0); 590 out_be32(&l2cache->l2srbar1, 0x0); 591 592 /* set MBECCDIS=0, SBECCDIS=0 */ 593 clrbits_be32(&l2cache->l2errdis, 594 (MPC85xx_L2ERRDIS_MBECC | 595 MPC85xx_L2ERRDIS_SBECC)); 596 597 /* set L2E=0, L2SRAM=0 */ 598 clrbits_be32(&l2cache->l2ctl, 599 (MPC85xx_L2CTL_L2E | 600 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 601 } 602 #endif 603 604 l2siz_field = (cache_ctl >> 28) & 0x3; 605 606 switch (l2siz_field) { 607 case 0x0: 608 printf(" unknown size (0x%08x)\n", cache_ctl); 609 return -1; 610 break; 611 case 0x1: 612 if (ver == SVR_8540 || ver == SVR_8560 || 613 ver == SVR_8541 || ver == SVR_8555) { 614 puts("128 KiB "); 615 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 616 cache_ctl = 0xc4000000; 617 } else { 618 puts("256 KiB "); 619 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 620 } 621 break; 622 case 0x2: 623 if (ver == SVR_8540 || ver == SVR_8560 || 624 ver == SVR_8541 || ver == SVR_8555) { 625 puts("256 KiB "); 626 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 627 cache_ctl = 0xc8000000; 628 } else { 629 puts("512 KiB "); 630 /* set L2E=1, L2I=1, & L2SRAM=0 */ 631 cache_ctl = 0xc0000000; 632 } 633 break; 634 case 0x3: 635 puts("1024 KiB "); 636 /* set L2E=1, L2I=1, & L2SRAM=0 */ 637 cache_ctl = 0xc0000000; 638 break; 639 } 640 641 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 642 puts("already enabled"); 643 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 644 u32 l2srbar = l2cache->l2srbar0; 645 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 646 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 647 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 648 l2cache->l2srbar0 = l2srbar; 649 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 650 } 651 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 652 puts("\n"); 653 } else { 654 asm("msync;isync"); 655 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 656 asm("msync;isync"); 657 puts("enabled\n"); 658 } 659 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 660 if (SVR_SOC_VER(svr) == SVR_P2040) { 661 puts("N/A\n"); 662 goto skip_l2; 663 } 664 665 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 666 667 /* invalidate the L2 cache */ 668 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 669 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 670 ; 671 672 #ifdef CONFIG_SYS_CACHE_STASHING 673 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 674 mtspr(SPRN_L2CSR1, (32 + 1)); 675 #endif 676 677 /* enable the cache */ 678 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 679 680 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 681 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 682 ; 683 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 684 } 685 686 skip_l2: 687 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 688 if (l2cache->l2csr0 & L2CSR0_L2E) 689 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 690 " enabled\n"); 691 692 enable_cluster_l2(); 693 #else 694 puts("disabled\n"); 695 #endif 696 697 #if defined(CONFIG_RAMBOOT_PBL) 698 disable_cpc_sram(); 699 #endif 700 enable_cpc(); 701 702 #ifndef CONFIG_SYS_FSL_NO_SERDES 703 /* needs to be in ram since code uses global static vars */ 704 fsl_serdes_init(); 705 #endif 706 707 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 708 #define MCFGR_AXIPIPE 0x000000f0 709 if (IS_SVR_REV(svr, 1, 0)) 710 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 711 #endif 712 713 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 714 if (IS_SVR_REV(svr, 1, 0)) { 715 int i; 716 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 717 718 for (i = 0; i < 12; i++) { 719 p += i + (i > 5 ? 11 : 0); 720 out_be32(p, 0x2); 721 } 722 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 723 out_be32(p, 0x34); 724 } 725 #endif 726 727 #ifdef CONFIG_SYS_SRIO 728 srio_init(); 729 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 730 char *s = getenv("bootmaster"); 731 if (s) { 732 if (!strcmp(s, "SRIO1")) { 733 srio_boot_master(1); 734 srio_boot_master_release_slave(1); 735 } 736 if (!strcmp(s, "SRIO2")) { 737 srio_boot_master(2); 738 srio_boot_master_release_slave(2); 739 } 740 } 741 #endif 742 #endif 743 744 #if defined(CONFIG_MP) 745 setup_mp(); 746 #endif 747 748 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 749 { 750 if (SVR_MAJ(svr) < 3) { 751 void *p; 752 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 753 setbits_be32(p, 1 << (31 - 14)); 754 } 755 } 756 #endif 757 758 #ifdef CONFIG_SYS_LBC_LCRR 759 /* 760 * Modify the CLKDIV field of LCRR register to improve the writing 761 * speed for NOR flash. 762 */ 763 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 764 __raw_readl(&lbc->lcrr); 765 isync(); 766 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 767 udelay(100); 768 #endif 769 #endif 770 771 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 772 { 773 struct ccsr_usb_phy __iomem *usb_phy1 = 774 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 775 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 776 if (has_erratum_a006261()) 777 fsl_erratum_a006261_workaround(usb_phy1); 778 #endif 779 out_be32(&usb_phy1->usb_enable_override, 780 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 781 } 782 #endif 783 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 784 { 785 struct ccsr_usb_phy __iomem *usb_phy2 = 786 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 787 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 788 if (has_erratum_a006261()) 789 fsl_erratum_a006261_workaround(usb_phy2); 790 #endif 791 out_be32(&usb_phy2->usb_enable_override, 792 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 793 } 794 #endif 795 796 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 797 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 798 * multi-bit ECC errors which has impact on performance, so software 799 * should disable all ECC reporting from USB1 and USB2. 800 */ 801 if (IS_SVR_REV(get_svr(), 1, 0)) { 802 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 803 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 804 setbits_be32(&dcfg->ecccr1, 805 (DCSR_DCFG_ECC_DISABLE_USB1 | 806 DCSR_DCFG_ECC_DISABLE_USB2)); 807 } 808 #endif 809 810 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 811 struct ccsr_usb_phy __iomem *usb_phy = 812 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 813 setbits_be32(&usb_phy->pllprg[1], 814 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 815 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 816 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 817 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 818 setbits_be32(&usb_phy->port1.ctrl, 819 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 820 setbits_be32(&usb_phy->port1.drvvbuscfg, 821 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 822 setbits_be32(&usb_phy->port1.pwrfltcfg, 823 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 824 setbits_be32(&usb_phy->port2.ctrl, 825 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 826 setbits_be32(&usb_phy->port2.drvvbuscfg, 827 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 828 setbits_be32(&usb_phy->port2.pwrfltcfg, 829 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 830 831 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 832 if (has_erratum_a006261()) 833 fsl_erratum_a006261_workaround(usb_phy); 834 #endif 835 836 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 837 838 #ifdef CONFIG_FMAN_ENET 839 fman_enet_init(); 840 #endif 841 842 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 843 /* 844 * For P1022/1013 Rev1.0 silicon, after power on SATA host 845 * controller is configured in legacy mode instead of the 846 * expected enterprise mode. Software needs to clear bit[28] 847 * of HControl register to change to enterprise mode from 848 * legacy mode. We assume that the controller is offline. 849 */ 850 if (IS_SVR_REV(svr, 1, 0) && 851 ((SVR_SOC_VER(svr) == SVR_P1022) || 852 (SVR_SOC_VER(svr) == SVR_P1013))) { 853 fsl_sata_reg_t *reg; 854 855 /* first SATA controller */ 856 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 857 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 858 859 /* second SATA controller */ 860 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 861 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 862 } 863 #endif 864 865 866 return 0; 867 } 868 869 void arch_preboot_os(void) 870 { 871 u32 msr; 872 873 /* 874 * We are changing interrupt offsets and are about to boot the OS so 875 * we need to make sure we disable all async interrupts. EE is already 876 * disabled by the time we get called. 877 */ 878 msr = mfmsr(); 879 msr &= ~(MSR_ME|MSR_CE); 880 mtmsr(msr); 881 } 882 883 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 884 int sata_initialize(void) 885 { 886 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 887 return __sata_initialize(); 888 889 return 1; 890 } 891 #endif 892 893 void cpu_secondary_init_r(void) 894 { 895 #ifdef CONFIG_U_QE 896 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 897 #elif defined CONFIG_QE 898 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 899 #endif 900 901 #ifdef CONFIG_QE 902 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 903 int ret; 904 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 905 906 /* load QE firmware from NAND flash to DDR first */ 907 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 908 &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); 909 910 if (ret && ret == -EUCLEAN) { 911 printf ("NAND read for QE firmware at offset %x failed %d\n", 912 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 913 } 914 #endif 915 qe_init(qe_base); 916 qe_reset(); 917 #endif 918 } 919