1 /* 2 * Copyright 2007-2009 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <asm/io.h> 34 #include <asm/mmu.h> 35 #include <asm/fsl_law.h> 36 #include "mp.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 #ifdef CONFIG_MPC8536 41 extern void fsl_serdes_init(void); 42 #endif 43 44 #ifdef CONFIG_QE 45 extern qe_iop_conf_t qe_iop_conf_tab[]; 46 extern void qe_config_iopin(u8 port, u8 pin, int dir, 47 int open_drain, int assign); 48 extern void qe_init(uint qe_base); 49 extern void qe_reset(void); 50 51 static void config_qe_ioports(void) 52 { 53 u8 port, pin; 54 int dir, open_drain, assign; 55 int i; 56 57 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 58 port = qe_iop_conf_tab[i].port; 59 pin = qe_iop_conf_tab[i].pin; 60 dir = qe_iop_conf_tab[i].dir; 61 open_drain = qe_iop_conf_tab[i].open_drain; 62 assign = qe_iop_conf_tab[i].assign; 63 qe_config_iopin(port, pin, dir, open_drain, assign); 64 } 65 } 66 #endif 67 68 #ifdef CONFIG_CPM2 69 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 70 { 71 int portnum; 72 73 for (portnum = 0; portnum < 4; portnum++) { 74 uint pmsk = 0, 75 ppar = 0, 76 psor = 0, 77 pdir = 0, 78 podr = 0, 79 pdat = 0; 80 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 81 iop_conf_t *eiopc = iopc + 32; 82 uint msk = 1; 83 84 /* 85 * NOTE: 86 * index 0 refers to pin 31, 87 * index 31 refers to pin 0 88 */ 89 while (iopc < eiopc) { 90 if (iopc->conf) { 91 pmsk |= msk; 92 if (iopc->ppar) 93 ppar |= msk; 94 if (iopc->psor) 95 psor |= msk; 96 if (iopc->pdir) 97 pdir |= msk; 98 if (iopc->podr) 99 podr |= msk; 100 if (iopc->pdat) 101 pdat |= msk; 102 } 103 104 msk <<= 1; 105 iopc++; 106 } 107 108 if (pmsk != 0) { 109 volatile ioport_t *iop = ioport_addr (cpm, portnum); 110 uint tpmsk = ~pmsk; 111 112 /* 113 * the (somewhat confused) paragraph at the 114 * bottom of page 35-5 warns that there might 115 * be "unknown behaviour" when programming 116 * PSORx and PDIRx, if PPARx = 1, so I 117 * decided this meant I had to disable the 118 * dedicated function first, and enable it 119 * last. 120 */ 121 iop->ppar &= tpmsk; 122 iop->psor = (iop->psor & tpmsk) | psor; 123 iop->podr = (iop->podr & tpmsk) | podr; 124 iop->pdat = (iop->pdat & tpmsk) | pdat; 125 iop->pdir = (iop->pdir & tpmsk) | pdir; 126 iop->ppar |= ppar; 127 } 128 } 129 } 130 #endif 131 132 /* 133 * Breathe some life into the CPU... 134 * 135 * Set up the memory map 136 * initialize a bunch of registers 137 */ 138 139 #ifdef CONFIG_FSL_CORENET 140 static void corenet_tb_init(void) 141 { 142 volatile ccsr_rcpm_t *rcpm = 143 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 144 volatile ccsr_pic_t *pic = 145 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 146 u32 whoami = in_be32(&pic->whoami); 147 148 /* Enable the timebase register for this core */ 149 out_be32(&rcpm->ctbenrl, (1 << whoami)); 150 } 151 #endif 152 153 void cpu_init_f (void) 154 { 155 volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 156 extern void m8560_cpm_reset (void); 157 #ifdef CONFIG_MPC8548 158 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 159 uint svr = get_svr(); 160 161 /* 162 * CPU2 errata workaround: A core hang possible while executing 163 * a msync instruction and a snoopable transaction from an I/O 164 * master tagged to make quick forward progress is present. 165 * Fixed in silicon rev 2.1. 166 */ 167 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 168 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 169 #endif 170 171 disable_tlb(14); 172 disable_tlb(15); 173 174 #ifdef CONFIG_CPM2 175 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 176 #endif 177 178 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary 179 * addresses - these have to be modified later when FLASH size 180 * has been determined 181 */ 182 #if defined(CONFIG_SYS_OR0_REMAP) 183 memctl->or0 = CONFIG_SYS_OR0_REMAP; 184 #endif 185 #if defined(CONFIG_SYS_OR1_REMAP) 186 memctl->or1 = CONFIG_SYS_OR1_REMAP; 187 #endif 188 189 /* now restrict to preliminary range */ 190 /* if cs1 is already set via debugger, leave cs0/cs1 alone */ 191 if (! memctl->br1 & 1) { 192 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) 193 memctl->br0 = CONFIG_SYS_BR0_PRELIM; 194 memctl->or0 = CONFIG_SYS_OR0_PRELIM; 195 #endif 196 197 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) 198 memctl->or1 = CONFIG_SYS_OR1_PRELIM; 199 memctl->br1 = CONFIG_SYS_BR1_PRELIM; 200 #endif 201 } 202 203 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) 204 memctl->or2 = CONFIG_SYS_OR2_PRELIM; 205 memctl->br2 = CONFIG_SYS_BR2_PRELIM; 206 #endif 207 208 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) 209 memctl->or3 = CONFIG_SYS_OR3_PRELIM; 210 memctl->br3 = CONFIG_SYS_BR3_PRELIM; 211 #endif 212 213 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) 214 memctl->or4 = CONFIG_SYS_OR4_PRELIM; 215 memctl->br4 = CONFIG_SYS_BR4_PRELIM; 216 #endif 217 218 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) 219 memctl->or5 = CONFIG_SYS_OR5_PRELIM; 220 memctl->br5 = CONFIG_SYS_BR5_PRELIM; 221 #endif 222 223 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) 224 memctl->or6 = CONFIG_SYS_OR6_PRELIM; 225 memctl->br6 = CONFIG_SYS_BR6_PRELIM; 226 #endif 227 228 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) 229 memctl->or7 = CONFIG_SYS_OR7_PRELIM; 230 memctl->br7 = CONFIG_SYS_BR7_PRELIM; 231 #endif 232 233 #if defined(CONFIG_CPM2) 234 m8560_cpm_reset(); 235 #endif 236 #ifdef CONFIG_QE 237 /* Config QE ioports */ 238 config_qe_ioports(); 239 #endif 240 #if defined(CONFIG_MPC8536) 241 fsl_serdes_init(); 242 #endif 243 #if defined(CONFIG_FSL_DMA) 244 dma_init(); 245 #endif 246 #ifdef CONFIG_FSL_CORENET 247 corenet_tb_init(); 248 #endif 249 init_used_tlb_cams(); 250 } 251 252 253 /* 254 * Initialize L2 as cache. 255 * 256 * The newer 8548, etc, parts have twice as much cache, but 257 * use the same bit-encoding as the older 8555, etc, parts. 258 * 259 */ 260 261 int cpu_init_r(void) 262 { 263 puts ("L2: "); 264 265 #if defined(CONFIG_L2_CACHE) 266 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 267 volatile uint cache_ctl; 268 uint svr, ver; 269 uint l2srbar; 270 u32 l2siz_field; 271 272 svr = get_svr(); 273 ver = SVR_SOC_VER(svr); 274 275 asm("msync;isync"); 276 cache_ctl = l2cache->l2ctl; 277 278 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 279 if (cache_ctl & MPC85xx_L2CTL_L2E) { 280 /* Clear L2 SRAM memory-mapped base address */ 281 out_be32(&l2cache->l2srbar0, 0x0); 282 out_be32(&l2cache->l2srbar1, 0x0); 283 284 /* set MBECCDIS=0, SBECCDIS=0 */ 285 clrbits_be32(&l2cache->l2errdis, 286 (MPC85xx_L2ERRDIS_MBECC | 287 MPC85xx_L2ERRDIS_SBECC)); 288 289 /* set L2E=0, L2SRAM=0 */ 290 clrbits_be32(&l2cache->l2ctl, 291 (MPC85xx_L2CTL_L2E | 292 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 293 } 294 #endif 295 296 l2siz_field = (cache_ctl >> 28) & 0x3; 297 298 switch (l2siz_field) { 299 case 0x0: 300 printf(" unknown size (0x%08x)\n", cache_ctl); 301 return -1; 302 break; 303 case 0x1: 304 if (ver == SVR_8540 || ver == SVR_8560 || 305 ver == SVR_8541 || ver == SVR_8541_E || 306 ver == SVR_8555 || ver == SVR_8555_E) { 307 puts("128 KB "); 308 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 309 cache_ctl = 0xc4000000; 310 } else { 311 puts("256 KB "); 312 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 313 } 314 break; 315 case 0x2: 316 if (ver == SVR_8540 || ver == SVR_8560 || 317 ver == SVR_8541 || ver == SVR_8541_E || 318 ver == SVR_8555 || ver == SVR_8555_E) { 319 puts("256 KB "); 320 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 321 cache_ctl = 0xc8000000; 322 } else { 323 puts ("512 KB "); 324 /* set L2E=1, L2I=1, & L2SRAM=0 */ 325 cache_ctl = 0xc0000000; 326 } 327 break; 328 case 0x3: 329 puts("1024 KB "); 330 /* set L2E=1, L2I=1, & L2SRAM=0 */ 331 cache_ctl = 0xc0000000; 332 break; 333 } 334 335 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 336 puts("already enabled"); 337 l2srbar = l2cache->l2srbar0; 338 #ifdef CONFIG_SYS_INIT_L2_ADDR 339 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 340 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 341 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 342 l2cache->l2srbar0 = l2srbar; 343 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 344 } 345 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 346 puts("\n"); 347 } else { 348 asm("msync;isync"); 349 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 350 asm("msync;isync"); 351 puts("enabled\n"); 352 } 353 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 354 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 355 356 /* invalidate the L2 cache */ 357 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 358 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 359 ; 360 361 #ifdef CONFIG_SYS_CACHE_STASHING 362 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 363 mtspr(SPRN_L2CSR1, (32 + 1)); 364 #endif 365 366 /* enable the cache */ 367 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 368 369 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 370 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 371 ; 372 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 373 } 374 #else 375 puts("disabled\n"); 376 #endif 377 #ifdef CONFIG_QE 378 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 379 qe_init(qe_base); 380 qe_reset(); 381 #endif 382 383 #if defined(CONFIG_MP) 384 setup_mp(); 385 #endif 386 return 0; 387 } 388 389 extern void setup_ivors(void); 390 391 void arch_preboot_os(void) 392 { 393 u32 msr; 394 395 /* 396 * We are changing interrupt offsets and are about to boot the OS so 397 * we need to make sure we disable all async interrupts. EE is already 398 * disabled by the time we get called. 399 */ 400 msr = mfmsr(); 401 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 402 mtmsr(msr); 403 404 setup_ivors(); 405 } 406