1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #ifdef CONFIG_FSL_CORENET 27 #include <asm/fsl_portals.h> 28 #include <asm/fsl_liodn.h> 29 #endif 30 #include <fsl_usb.h> 31 #include <hwconfig.h> 32 #include <linux/compiler.h> 33 #include "mp.h" 34 #ifdef CONFIG_FSL_CAAM 35 #include <fsl_sec.h> 36 #endif 37 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 38 #include <nand.h> 39 #include <errno.h> 40 #endif 41 42 #include "../../../../drivers/block/fsl_sata.h" 43 #ifdef CONFIG_U_QE 44 #include "../../../../drivers/qe/qe.h" 45 #endif 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 50 /* 51 * For deriving usb clock from 100MHz sysclk, reference divisor is set 52 * to a value of 5, which gives an intermediate value 20(100/5). The 53 * multiplication factor integer is set to 24, which when multiplied to 54 * above intermediate value provides clock for usb ip. 55 */ 56 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 57 { 58 sys_info_t sysinfo; 59 60 get_sys_info(&sysinfo); 61 if (sysinfo.diff_sysclk == 1) { 62 clrbits_be32(&usb_phy->pllprg[1], 63 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 64 setbits_be32(&usb_phy->pllprg[1], 65 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 66 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 67 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 68 } 69 } 70 #endif 71 72 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 73 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 74 { 75 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 76 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 77 78 /* Increase Disconnect Threshold by 50mV */ 79 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 80 INC_DCNT_THRESHOLD_50MV; 81 /* Enable programming of USB High speed Disconnect threshold */ 82 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 83 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 84 85 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 86 /* Increase Disconnect Threshold by 50mV */ 87 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 88 INC_DCNT_THRESHOLD_50MV; 89 /* Enable programming of USB High speed Disconnect threshold */ 90 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 91 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 92 #else 93 94 u32 temp = 0; 95 u32 status = in_be32(&usb_phy->status1); 96 97 u32 squelch_prog_rd_0_2 = 98 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 99 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 100 101 u32 squelch_prog_rd_3_5 = 102 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 103 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 104 105 setbits_be32(&usb_phy->config1, 106 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 107 setbits_be32(&usb_phy->config2, 108 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 109 110 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 111 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 112 113 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 114 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 115 #endif 116 } 117 #endif 118 119 120 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 121 extern qe_iop_conf_t qe_iop_conf_tab[]; 122 extern void qe_config_iopin(u8 port, u8 pin, int dir, 123 int open_drain, int assign); 124 extern void qe_init(uint qe_base); 125 extern void qe_reset(void); 126 127 static void config_qe_ioports(void) 128 { 129 u8 port, pin; 130 int dir, open_drain, assign; 131 int i; 132 133 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 134 port = qe_iop_conf_tab[i].port; 135 pin = qe_iop_conf_tab[i].pin; 136 dir = qe_iop_conf_tab[i].dir; 137 open_drain = qe_iop_conf_tab[i].open_drain; 138 assign = qe_iop_conf_tab[i].assign; 139 qe_config_iopin(port, pin, dir, open_drain, assign); 140 } 141 } 142 #endif 143 144 #ifdef CONFIG_CPM2 145 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 146 { 147 int portnum; 148 149 for (portnum = 0; portnum < 4; portnum++) { 150 uint pmsk = 0, 151 ppar = 0, 152 psor = 0, 153 pdir = 0, 154 podr = 0, 155 pdat = 0; 156 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 157 iop_conf_t *eiopc = iopc + 32; 158 uint msk = 1; 159 160 /* 161 * NOTE: 162 * index 0 refers to pin 31, 163 * index 31 refers to pin 0 164 */ 165 while (iopc < eiopc) { 166 if (iopc->conf) { 167 pmsk |= msk; 168 if (iopc->ppar) 169 ppar |= msk; 170 if (iopc->psor) 171 psor |= msk; 172 if (iopc->pdir) 173 pdir |= msk; 174 if (iopc->podr) 175 podr |= msk; 176 if (iopc->pdat) 177 pdat |= msk; 178 } 179 180 msk <<= 1; 181 iopc++; 182 } 183 184 if (pmsk != 0) { 185 volatile ioport_t *iop = ioport_addr (cpm, portnum); 186 uint tpmsk = ~pmsk; 187 188 /* 189 * the (somewhat confused) paragraph at the 190 * bottom of page 35-5 warns that there might 191 * be "unknown behaviour" when programming 192 * PSORx and PDIRx, if PPARx = 1, so I 193 * decided this meant I had to disable the 194 * dedicated function first, and enable it 195 * last. 196 */ 197 iop->ppar &= tpmsk; 198 iop->psor = (iop->psor & tpmsk) | psor; 199 iop->podr = (iop->podr & tpmsk) | podr; 200 iop->pdat = (iop->pdat & tpmsk) | pdat; 201 iop->pdir = (iop->pdir & tpmsk) | pdir; 202 iop->ppar |= ppar; 203 } 204 } 205 } 206 #endif 207 208 #ifdef CONFIG_SYS_FSL_CPC 209 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 210 void disable_cpc_sram(void) 211 { 212 int i; 213 214 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 215 216 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 217 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 218 /* find and disable LAW of SRAM */ 219 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 220 221 if (law.index == -1) { 222 printf("\nFatal error happened\n"); 223 return; 224 } 225 disable_law(law.index); 226 227 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 228 out_be32(&cpc->cpccsr0, 0); 229 out_be32(&cpc->cpcsrcr0, 0); 230 } 231 } 232 } 233 #endif 234 235 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 236 #ifdef CONFIG_POST 237 #error POST memory test cannot be enabled with TDM 238 #endif 239 static void enable_tdm_law(void) 240 { 241 int ret; 242 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 243 int tdm_hwconfig_enabled = 0; 244 245 /* 246 * Extract hwconfig from environment since environment 247 * is not setup properly yet. Search for tdm entry in 248 * hwconfig. 249 */ 250 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 251 if (ret > 0) { 252 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 253 /* If tdm is defined in hwconfig, set law for tdm workaround */ 254 if (tdm_hwconfig_enabled) 255 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 256 LAW_TRGT_IF_CCSR); 257 } 258 } 259 #endif 260 261 void enable_cpc(void) 262 { 263 int i; 264 int ret; 265 u32 size = 0; 266 u32 cpccfg0; 267 char buffer[HWCONFIG_BUFFER_SIZE]; 268 char cpc_subarg[16]; 269 bool have_hwconfig = false; 270 int cpc_args = 0; 271 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 272 273 /* Extract hwconfig from environment */ 274 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 275 if (ret > 0) { 276 /* 277 * If "en_cpc" is not defined in hwconfig then by default all 278 * cpcs are enable. If this config is defined then individual 279 * cpcs which have to be enabled should also be defined. 280 * e.g en_cpc:cpc1,cpc2; 281 */ 282 if (hwconfig_f("en_cpc", buffer)) 283 have_hwconfig = true; 284 } 285 286 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 287 if (have_hwconfig) { 288 sprintf(cpc_subarg, "cpc%u", i + 1); 289 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); 290 if (cpc_args == 0) 291 continue; 292 } 293 cpccfg0 = in_be32(&cpc->cpccfg0); 294 size += CPC_CFG0_SZ_K(cpccfg0); 295 296 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 297 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 298 #endif 299 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 300 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 301 #endif 302 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 303 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 304 #endif 305 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 306 if (has_erratum_a006379()) { 307 setbits_be32(&cpc->cpchdbcr0, 308 CPC_HDBCR0_SPLRU_LEVEL_EN); 309 } 310 #endif 311 312 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 313 /* Read back to sync write */ 314 in_be32(&cpc->cpccsr0); 315 316 } 317 318 puts("Corenet Platform Cache: "); 319 print_size(size * 1024, " enabled\n"); 320 } 321 322 static void invalidate_cpc(void) 323 { 324 int i; 325 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 326 327 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 328 /* skip CPC when it used as all SRAM */ 329 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 330 continue; 331 /* Flash invalidate the CPC and clear all the locks */ 332 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 333 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 334 ; 335 } 336 } 337 #else 338 #define enable_cpc() 339 #define invalidate_cpc() 340 #define disable_cpc_sram() 341 #endif /* CONFIG_SYS_FSL_CPC */ 342 343 /* 344 * Breathe some life into the CPU... 345 * 346 * Set up the memory map 347 * initialize a bunch of registers 348 */ 349 350 #ifdef CONFIG_FSL_CORENET 351 static void corenet_tb_init(void) 352 { 353 volatile ccsr_rcpm_t *rcpm = 354 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 355 volatile ccsr_pic_t *pic = 356 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 357 u32 whoami = in_be32(&pic->whoami); 358 359 /* Enable the timebase register for this core */ 360 out_be32(&rcpm->ctbenrl, (1 << whoami)); 361 } 362 #endif 363 364 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 365 void fsl_erratum_a007212_workaround(void) 366 { 367 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 368 u32 ddr_pll_ratio; 369 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 370 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 371 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 372 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 373 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 374 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 375 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 376 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 377 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 378 #endif 379 #endif 380 /* 381 * Even this workaround applies to selected version of SoCs, it is 382 * safe to apply to all versions, with the limitation of odd ratios. 383 * If RCW has disabled DDR PLL, we have to apply this workaround, 384 * otherwise DDR will not work. 385 */ 386 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 387 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 388 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 389 /* check if RCW sets ratio to 0, required by this workaround */ 390 if (ddr_pll_ratio != 0) 391 return; 392 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 393 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 394 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 395 /* check if reserved bits have the desired ratio */ 396 if (ddr_pll_ratio == 0) { 397 printf("Error: Unknown DDR PLL ratio!\n"); 398 return; 399 } 400 ddr_pll_ratio >>= 1; 401 402 setbits_be32(plldadcr1, 0x02000001); 403 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 404 setbits_be32(plldadcr2, 0x02000001); 405 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 406 setbits_be32(plldadcr3, 0x02000001); 407 #endif 408 #endif 409 setbits_be32(dpdovrcr4, 0xe0000000); 410 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 411 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 412 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 413 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 414 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 415 #endif 416 #endif 417 udelay(100); 418 clrbits_be32(plldadcr1, 0x02000001); 419 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 420 clrbits_be32(plldadcr2, 0x02000001); 421 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 422 clrbits_be32(plldadcr3, 0x02000001); 423 #endif 424 #endif 425 clrbits_be32(dpdovrcr4, 0xe0000000); 426 } 427 #endif 428 429 ulong cpu_init_f(void) 430 { 431 extern void m8560_cpm_reset (void); 432 #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ 433 (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) 434 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 435 #endif 436 #if defined(CONFIG_SECURE_BOOT) 437 struct law_entry law; 438 #endif 439 #ifdef CONFIG_MPC8548 440 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 441 uint svr = get_svr(); 442 443 /* 444 * CPU2 errata workaround: A core hang possible while executing 445 * a msync instruction and a snoopable transaction from an I/O 446 * master tagged to make quick forward progress is present. 447 * Fixed in silicon rev 2.1. 448 */ 449 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 450 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 451 #endif 452 453 disable_tlb(14); 454 disable_tlb(15); 455 456 #if defined(CONFIG_SECURE_BOOT) 457 /* Disable the LAW created for NOR flash by the PBI commands */ 458 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 459 if (law.index != -1) 460 disable_law(law.index); 461 462 #if defined(CONFIG_SYS_CPC_REINIT_F) 463 disable_cpc_sram(); 464 #endif 465 466 #if defined(CONFIG_FSL_CORENET) 467 /* Put PAMU in bypass mode */ 468 out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS); 469 #endif 470 471 #endif 472 473 #ifdef CONFIG_CPM2 474 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 475 #endif 476 477 init_early_memctl_regs(); 478 479 #if defined(CONFIG_CPM2) 480 m8560_cpm_reset(); 481 #endif 482 483 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 484 /* Config QE ioports */ 485 config_qe_ioports(); 486 #endif 487 488 #if defined(CONFIG_FSL_DMA) 489 dma_init(); 490 #endif 491 #ifdef CONFIG_FSL_CORENET 492 corenet_tb_init(); 493 #endif 494 init_used_tlb_cams(); 495 496 /* Invalidate the CPC before DDR gets enabled */ 497 invalidate_cpc(); 498 499 #ifdef CONFIG_SYS_DCSRBAR_PHYS 500 /* set DCSRCR so that DCSR space is 1G */ 501 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 502 in_be32(&gur->dcsrcr); 503 #endif 504 505 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 506 fsl_erratum_a007212_workaround(); 507 #endif 508 509 return 0; 510 } 511 512 /* Implement a dummy function for those platforms w/o SERDES */ 513 static void __fsl_serdes__init(void) 514 { 515 return ; 516 } 517 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 518 519 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 520 int enable_cluster_l2(void) 521 { 522 int i = 0; 523 u32 cluster, svr = get_svr(); 524 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 525 struct ccsr_cluster_l2 __iomem *l2cache; 526 527 /* only the L2 of first cluster should be enabled as expected on T4080, 528 * but there is no EOC in the first cluster as HW sake, so return here 529 * to skip enabling L2 cache of the 2nd cluster. 530 */ 531 if (SVR_SOC_VER(svr) == SVR_T4080) 532 return 0; 533 534 cluster = in_be32(&gur->tp_cluster[i].lower); 535 if (cluster & TP_CLUSTER_EOC) 536 return 0; 537 538 /* The first cache has already been set up, so skip it */ 539 i++; 540 541 /* Look through the remaining clusters, and set up their caches */ 542 do { 543 int j, cluster_valid = 0; 544 545 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 546 547 cluster = in_be32(&gur->tp_cluster[i].lower); 548 549 /* check that at least one core/accel is enabled in cluster */ 550 for (j = 0; j < 4; j++) { 551 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 552 u32 type = in_be32(&gur->tp_ityp[idx]); 553 554 if ((type & TP_ITYP_AV) && 555 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 556 cluster_valid = 1; 557 } 558 559 if (cluster_valid) { 560 /* set stash ID to (cluster) * 2 + 32 + 1 */ 561 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 562 563 printf("enable l2 for cluster %d %p\n", i, l2cache); 564 565 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 566 while ((in_be32(&l2cache->l2csr0) 567 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 568 ; 569 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 570 } 571 i++; 572 } while (!(cluster & TP_CLUSTER_EOC)); 573 574 return 0; 575 } 576 #endif 577 578 /* 579 * Initialize L2 as cache. 580 */ 581 int l2cache_init(void) 582 { 583 __maybe_unused u32 svr = get_svr(); 584 #ifdef CONFIG_L2_CACHE 585 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 586 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 587 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 588 #endif 589 590 puts ("L2: "); 591 592 #if defined(CONFIG_L2_CACHE) 593 volatile uint cache_ctl; 594 uint ver; 595 u32 l2siz_field; 596 597 ver = SVR_SOC_VER(svr); 598 599 asm("msync;isync"); 600 cache_ctl = l2cache->l2ctl; 601 602 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 603 if (cache_ctl & MPC85xx_L2CTL_L2E) { 604 /* Clear L2 SRAM memory-mapped base address */ 605 out_be32(&l2cache->l2srbar0, 0x0); 606 out_be32(&l2cache->l2srbar1, 0x0); 607 608 /* set MBECCDIS=0, SBECCDIS=0 */ 609 clrbits_be32(&l2cache->l2errdis, 610 (MPC85xx_L2ERRDIS_MBECC | 611 MPC85xx_L2ERRDIS_SBECC)); 612 613 /* set L2E=0, L2SRAM=0 */ 614 clrbits_be32(&l2cache->l2ctl, 615 (MPC85xx_L2CTL_L2E | 616 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 617 } 618 #endif 619 620 l2siz_field = (cache_ctl >> 28) & 0x3; 621 622 switch (l2siz_field) { 623 case 0x0: 624 printf(" unknown size (0x%08x)\n", cache_ctl); 625 return -1; 626 break; 627 case 0x1: 628 if (ver == SVR_8540 || ver == SVR_8560 || 629 ver == SVR_8541 || ver == SVR_8555) { 630 puts("128 KiB "); 631 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 632 cache_ctl = 0xc4000000; 633 } else { 634 puts("256 KiB "); 635 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 636 } 637 break; 638 case 0x2: 639 if (ver == SVR_8540 || ver == SVR_8560 || 640 ver == SVR_8541 || ver == SVR_8555) { 641 puts("256 KiB "); 642 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 643 cache_ctl = 0xc8000000; 644 } else { 645 puts("512 KiB "); 646 /* set L2E=1, L2I=1, & L2SRAM=0 */ 647 cache_ctl = 0xc0000000; 648 } 649 break; 650 case 0x3: 651 puts("1024 KiB "); 652 /* set L2E=1, L2I=1, & L2SRAM=0 */ 653 cache_ctl = 0xc0000000; 654 break; 655 } 656 657 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 658 puts("already enabled"); 659 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 660 u32 l2srbar = l2cache->l2srbar0; 661 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 662 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 663 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 664 l2cache->l2srbar0 = l2srbar; 665 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 666 } 667 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 668 puts("\n"); 669 } else { 670 asm("msync;isync"); 671 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 672 asm("msync;isync"); 673 puts("enabled\n"); 674 } 675 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 676 if (SVR_SOC_VER(svr) == SVR_P2040) { 677 puts("N/A\n"); 678 goto skip_l2; 679 } 680 681 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 682 683 /* invalidate the L2 cache */ 684 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 685 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 686 ; 687 688 #ifdef CONFIG_SYS_CACHE_STASHING 689 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 690 mtspr(SPRN_L2CSR1, (32 + 1)); 691 #endif 692 693 /* enable the cache */ 694 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 695 696 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 697 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 698 ; 699 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 700 } 701 702 skip_l2: 703 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 704 if (l2cache->l2csr0 & L2CSR0_L2E) 705 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 706 " enabled\n"); 707 708 enable_cluster_l2(); 709 #else 710 puts("disabled\n"); 711 #endif 712 713 return 0; 714 } 715 716 /* 717 * 718 * The newer 8548, etc, parts have twice as much cache, but 719 * use the same bit-encoding as the older 8555, etc, parts. 720 * 721 */ 722 int cpu_init_r(void) 723 { 724 __maybe_unused u32 svr = get_svr(); 725 #ifdef CONFIG_SYS_LBC_LCRR 726 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 727 #endif 728 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 729 extern int spin_table_compat; 730 const char *spin; 731 #endif 732 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 733 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 734 #endif 735 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 736 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 737 /* 738 * CPU22 and NMG_CPU_A011 share the same workaround. 739 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 740 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 741 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 742 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 743 * be disabled by hwconfig with syntax: 744 * 745 * fsl_cpu_a011:disable 746 */ 747 extern int enable_cpu_a011_workaround; 748 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 749 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 750 #else 751 char buffer[HWCONFIG_BUFFER_SIZE]; 752 char *buf = NULL; 753 int n, res; 754 755 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 756 if (n > 0) 757 buf = buffer; 758 759 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 760 if (res > 0) { 761 enable_cpu_a011_workaround = 0; 762 } else { 763 if (n >= HWCONFIG_BUFFER_SIZE) { 764 printf("fsl_cpu_a011 was not found. hwconfig variable " 765 "may be too long\n"); 766 } 767 enable_cpu_a011_workaround = 768 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 769 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 770 } 771 #endif 772 if (enable_cpu_a011_workaround) { 773 flush_dcache(); 774 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 775 sync(); 776 } 777 #endif 778 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 779 /* 780 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 781 * in write shadow mode. Checking DCWS before setting SPR 976. 782 */ 783 if (mfspr(L1CSR2) & L1CSR2_DCWS) 784 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 785 #endif 786 787 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 788 spin = getenv("spin_table_compat"); 789 if (spin && (*spin == 'n')) 790 spin_table_compat = 0; 791 else 792 spin_table_compat = 1; 793 #endif 794 795 #ifdef CONFIG_FSL_CORENET 796 set_liodns(); 797 #ifdef CONFIG_SYS_DPAA_QBMAN 798 setup_portals(); 799 #endif 800 #endif 801 802 l2cache_init(); 803 #if defined(CONFIG_RAMBOOT_PBL) 804 disable_cpc_sram(); 805 #endif 806 enable_cpc(); 807 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 808 enable_tdm_law(); 809 #endif 810 811 #ifndef CONFIG_SYS_FSL_NO_SERDES 812 /* needs to be in ram since code uses global static vars */ 813 fsl_serdes_init(); 814 #endif 815 816 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 817 #define MCFGR_AXIPIPE 0x000000f0 818 if (IS_SVR_REV(svr, 1, 0)) 819 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); 820 #endif 821 822 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 823 if (IS_SVR_REV(svr, 1, 0)) { 824 int i; 825 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 826 827 for (i = 0; i < 12; i++) { 828 p += i + (i > 5 ? 11 : 0); 829 out_be32(p, 0x2); 830 } 831 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 832 out_be32(p, 0x34); 833 } 834 #endif 835 836 #ifdef CONFIG_SYS_SRIO 837 srio_init(); 838 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 839 char *s = getenv("bootmaster"); 840 if (s) { 841 if (!strcmp(s, "SRIO1")) { 842 srio_boot_master(1); 843 srio_boot_master_release_slave(1); 844 } 845 if (!strcmp(s, "SRIO2")) { 846 srio_boot_master(2); 847 srio_boot_master_release_slave(2); 848 } 849 } 850 #endif 851 #endif 852 853 #if defined(CONFIG_MP) 854 setup_mp(); 855 #endif 856 857 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 858 { 859 if (SVR_MAJ(svr) < 3) { 860 void *p; 861 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 862 setbits_be32(p, 1 << (31 - 14)); 863 } 864 } 865 #endif 866 867 #ifdef CONFIG_SYS_LBC_LCRR 868 /* 869 * Modify the CLKDIV field of LCRR register to improve the writing 870 * speed for NOR flash. 871 */ 872 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 873 __raw_readl(&lbc->lcrr); 874 isync(); 875 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 876 udelay(100); 877 #endif 878 #endif 879 880 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 881 { 882 struct ccsr_usb_phy __iomem *usb_phy1 = 883 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 884 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 885 if (has_erratum_a006261()) 886 fsl_erratum_a006261_workaround(usb_phy1); 887 #endif 888 out_be32(&usb_phy1->usb_enable_override, 889 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 890 } 891 #endif 892 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 893 { 894 struct ccsr_usb_phy __iomem *usb_phy2 = 895 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 896 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 897 if (has_erratum_a006261()) 898 fsl_erratum_a006261_workaround(usb_phy2); 899 #endif 900 out_be32(&usb_phy2->usb_enable_override, 901 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 902 } 903 #endif 904 905 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 906 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 907 * multi-bit ECC errors which has impact on performance, so software 908 * should disable all ECC reporting from USB1 and USB2. 909 */ 910 if (IS_SVR_REV(get_svr(), 1, 0)) { 911 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 912 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 913 setbits_be32(&dcfg->ecccr1, 914 (DCSR_DCFG_ECC_DISABLE_USB1 | 915 DCSR_DCFG_ECC_DISABLE_USB2)); 916 } 917 #endif 918 919 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 920 struct ccsr_usb_phy __iomem *usb_phy = 921 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 922 setbits_be32(&usb_phy->pllprg[1], 923 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 924 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 925 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 926 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 927 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 928 usb_single_source_clk_configure(usb_phy); 929 #endif 930 setbits_be32(&usb_phy->port1.ctrl, 931 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 932 setbits_be32(&usb_phy->port1.drvvbuscfg, 933 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 934 setbits_be32(&usb_phy->port1.pwrfltcfg, 935 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 936 setbits_be32(&usb_phy->port2.ctrl, 937 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 938 setbits_be32(&usb_phy->port2.drvvbuscfg, 939 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 940 setbits_be32(&usb_phy->port2.pwrfltcfg, 941 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 942 943 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 944 if (has_erratum_a006261()) 945 fsl_erratum_a006261_workaround(usb_phy); 946 #endif 947 948 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 949 950 #ifdef CONFIG_FMAN_ENET 951 fman_enet_init(); 952 #endif 953 954 #ifdef CONFIG_FSL_CAAM 955 sec_init(); 956 #endif 957 958 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 959 /* 960 * For P1022/1013 Rev1.0 silicon, after power on SATA host 961 * controller is configured in legacy mode instead of the 962 * expected enterprise mode. Software needs to clear bit[28] 963 * of HControl register to change to enterprise mode from 964 * legacy mode. We assume that the controller is offline. 965 */ 966 if (IS_SVR_REV(svr, 1, 0) && 967 ((SVR_SOC_VER(svr) == SVR_P1022) || 968 (SVR_SOC_VER(svr) == SVR_P1013))) { 969 fsl_sata_reg_t *reg; 970 971 /* first SATA controller */ 972 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 973 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 974 975 /* second SATA controller */ 976 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 977 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 978 } 979 #endif 980 981 init_used_tlb_cams(); 982 983 return 0; 984 } 985 986 void arch_preboot_os(void) 987 { 988 u32 msr; 989 990 /* 991 * We are changing interrupt offsets and are about to boot the OS so 992 * we need to make sure we disable all async interrupts. EE is already 993 * disabled by the time we get called. 994 */ 995 msr = mfmsr(); 996 msr &= ~(MSR_ME|MSR_CE); 997 mtmsr(msr); 998 } 999 1000 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 1001 int sata_initialize(void) 1002 { 1003 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 1004 return __sata_initialize(); 1005 1006 return 1; 1007 } 1008 #endif 1009 1010 void cpu_secondary_init_r(void) 1011 { 1012 #ifdef CONFIG_U_QE 1013 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 1014 #elif defined CONFIG_QE 1015 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 1016 #endif 1017 1018 #ifdef CONFIG_QE 1019 qe_init(qe_base); 1020 qe_reset(); 1021 #endif 1022 } 1023