1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <fm_eth.h> 35 #include <asm/io.h> 36 #include <asm/cache.h> 37 #include <asm/mmu.h> 38 #include <asm/fsl_law.h> 39 #include <asm/fsl_serdes.h> 40 #include <asm/fsl_srio.h> 41 #include <hwconfig.h> 42 #include <linux/compiler.h> 43 #include "mp.h" 44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 45 #include <nand.h> 46 #include <errno.h> 47 #endif 48 49 #include "../../../../drivers/block/fsl_sata.h" 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 #ifdef CONFIG_QE 54 extern qe_iop_conf_t qe_iop_conf_tab[]; 55 extern void qe_config_iopin(u8 port, u8 pin, int dir, 56 int open_drain, int assign); 57 extern void qe_init(uint qe_base); 58 extern void qe_reset(void); 59 60 static void config_qe_ioports(void) 61 { 62 u8 port, pin; 63 int dir, open_drain, assign; 64 int i; 65 66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 67 port = qe_iop_conf_tab[i].port; 68 pin = qe_iop_conf_tab[i].pin; 69 dir = qe_iop_conf_tab[i].dir; 70 open_drain = qe_iop_conf_tab[i].open_drain; 71 assign = qe_iop_conf_tab[i].assign; 72 qe_config_iopin(port, pin, dir, open_drain, assign); 73 } 74 } 75 #endif 76 77 #ifdef CONFIG_CPM2 78 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 79 { 80 int portnum; 81 82 for (portnum = 0; portnum < 4; portnum++) { 83 uint pmsk = 0, 84 ppar = 0, 85 psor = 0, 86 pdir = 0, 87 podr = 0, 88 pdat = 0; 89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 90 iop_conf_t *eiopc = iopc + 32; 91 uint msk = 1; 92 93 /* 94 * NOTE: 95 * index 0 refers to pin 31, 96 * index 31 refers to pin 0 97 */ 98 while (iopc < eiopc) { 99 if (iopc->conf) { 100 pmsk |= msk; 101 if (iopc->ppar) 102 ppar |= msk; 103 if (iopc->psor) 104 psor |= msk; 105 if (iopc->pdir) 106 pdir |= msk; 107 if (iopc->podr) 108 podr |= msk; 109 if (iopc->pdat) 110 pdat |= msk; 111 } 112 113 msk <<= 1; 114 iopc++; 115 } 116 117 if (pmsk != 0) { 118 volatile ioport_t *iop = ioport_addr (cpm, portnum); 119 uint tpmsk = ~pmsk; 120 121 /* 122 * the (somewhat confused) paragraph at the 123 * bottom of page 35-5 warns that there might 124 * be "unknown behaviour" when programming 125 * PSORx and PDIRx, if PPARx = 1, so I 126 * decided this meant I had to disable the 127 * dedicated function first, and enable it 128 * last. 129 */ 130 iop->ppar &= tpmsk; 131 iop->psor = (iop->psor & tpmsk) | psor; 132 iop->podr = (iop->podr & tpmsk) | podr; 133 iop->pdat = (iop->pdat & tpmsk) | pdat; 134 iop->pdir = (iop->pdir & tpmsk) | pdir; 135 iop->ppar |= ppar; 136 } 137 } 138 } 139 #endif 140 141 #ifdef CONFIG_SYS_FSL_CPC 142 static void enable_cpc(void) 143 { 144 int i; 145 u32 size = 0; 146 147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 148 149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 150 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 151 size += CPC_CFG0_SZ_K(cpccfg0); 152 #ifdef CONFIG_RAMBOOT_PBL 153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 154 /* find and disable LAW of SRAM */ 155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 156 157 if (law.index == -1) { 158 printf("\nFatal error happened\n"); 159 return; 160 } 161 disable_law(law.index); 162 163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 164 out_be32(&cpc->cpccsr0, 0); 165 out_be32(&cpc->cpcsrcr0, 0); 166 } 167 #endif 168 169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 171 #endif 172 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 174 #endif 175 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 176 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 177 #endif 178 179 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 180 /* Read back to sync write */ 181 in_be32(&cpc->cpccsr0); 182 183 } 184 185 printf("Corenet Platform Cache: %d KB enabled\n", size); 186 } 187 188 static void invalidate_cpc(void) 189 { 190 int i; 191 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 192 193 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 194 /* skip CPC when it used as all SRAM */ 195 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 196 continue; 197 /* Flash invalidate the CPC and clear all the locks */ 198 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 199 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 200 ; 201 } 202 } 203 #else 204 #define enable_cpc() 205 #define invalidate_cpc() 206 #endif /* CONFIG_SYS_FSL_CPC */ 207 208 /* 209 * Breathe some life into the CPU... 210 * 211 * Set up the memory map 212 * initialize a bunch of registers 213 */ 214 215 #ifdef CONFIG_FSL_CORENET 216 static void corenet_tb_init(void) 217 { 218 volatile ccsr_rcpm_t *rcpm = 219 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 220 volatile ccsr_pic_t *pic = 221 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 222 u32 whoami = in_be32(&pic->whoami); 223 224 /* Enable the timebase register for this core */ 225 out_be32(&rcpm->ctbenrl, (1 << whoami)); 226 } 227 #endif 228 229 void cpu_init_f (void) 230 { 231 extern void m8560_cpm_reset (void); 232 #ifdef CONFIG_SYS_DCSRBAR_PHYS 233 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 234 #endif 235 #if defined(CONFIG_SECURE_BOOT) 236 struct law_entry law; 237 #endif 238 #ifdef CONFIG_MPC8548 239 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 240 uint svr = get_svr(); 241 242 /* 243 * CPU2 errata workaround: A core hang possible while executing 244 * a msync instruction and a snoopable transaction from an I/O 245 * master tagged to make quick forward progress is present. 246 * Fixed in silicon rev 2.1. 247 */ 248 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 249 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 250 #endif 251 252 disable_tlb(14); 253 disable_tlb(15); 254 255 #if defined(CONFIG_SECURE_BOOT) 256 /* Disable the LAW created for NOR flash by the PBI commands */ 257 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 258 if (law.index != -1) 259 disable_law(law.index); 260 #endif 261 262 #ifdef CONFIG_CPM2 263 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 264 #endif 265 266 init_early_memctl_regs(); 267 268 #if defined(CONFIG_CPM2) 269 m8560_cpm_reset(); 270 #endif 271 #ifdef CONFIG_QE 272 /* Config QE ioports */ 273 config_qe_ioports(); 274 #endif 275 #if defined(CONFIG_FSL_DMA) 276 dma_init(); 277 #endif 278 #ifdef CONFIG_FSL_CORENET 279 corenet_tb_init(); 280 #endif 281 init_used_tlb_cams(); 282 283 /* Invalidate the CPC before DDR gets enabled */ 284 invalidate_cpc(); 285 286 #ifdef CONFIG_SYS_DCSRBAR_PHYS 287 /* set DCSRCR so that DCSR space is 1G */ 288 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 289 in_be32(&gur->dcsrcr); 290 #endif 291 292 } 293 294 /* Implement a dummy function for those platforms w/o SERDES */ 295 static void __fsl_serdes__init(void) 296 { 297 return ; 298 } 299 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 300 301 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 302 int enable_cluster_l2(void) 303 { 304 int i = 0; 305 u32 cluster; 306 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 307 struct ccsr_cluster_l2 __iomem *l2cache; 308 309 cluster = in_be32(&gur->tp_cluster[i].lower); 310 if (cluster & TP_CLUSTER_EOC) 311 return 0; 312 313 /* The first cache has already been set up, so skip it */ 314 i++; 315 316 /* Look through the remaining clusters, and set up their caches */ 317 do { 318 int j, cluster_valid = 0; 319 320 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 321 322 cluster = in_be32(&gur->tp_cluster[i].lower); 323 324 /* check that at least one core/accel is enabled in cluster */ 325 for (j = 0; j < 4; j++) { 326 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 327 u32 type = in_be32(&gur->tp_ityp[idx]); 328 329 if (type & TP_ITYP_AV) 330 cluster_valid = 1; 331 } 332 333 if (cluster_valid) { 334 /* set stash ID to (cluster) * 2 + 32 + 1 */ 335 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 336 337 printf("enable l2 for cluster %d %p\n", i, l2cache); 338 339 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 340 while ((in_be32(&l2cache->l2csr0) 341 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 342 ; 343 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 344 } 345 i++; 346 } while (!(cluster & TP_CLUSTER_EOC)); 347 348 return 0; 349 } 350 #endif 351 352 /* 353 * Initialize L2 as cache. 354 * 355 * The newer 8548, etc, parts have twice as much cache, but 356 * use the same bit-encoding as the older 8555, etc, parts. 357 * 358 */ 359 int cpu_init_r(void) 360 { 361 __maybe_unused u32 svr = get_svr(); 362 #ifdef CONFIG_SYS_LBC_LCRR 363 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 364 #endif 365 #ifdef CONFIG_L2_CACHE 366 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 367 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 368 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 369 #endif 370 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 371 extern int spin_table_compat; 372 const char *spin; 373 #endif 374 375 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 376 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 377 /* 378 * CPU22 and NMG_CPU_A011 share the same workaround. 379 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 380 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 381 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 382 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 383 * be disabled by hwconfig with syntax: 384 * 385 * fsl_cpu_a011:disable 386 */ 387 extern int enable_cpu_a011_workaround; 388 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 389 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 390 #else 391 char buffer[HWCONFIG_BUFFER_SIZE]; 392 char *buf = NULL; 393 int n, res; 394 395 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 396 if (n > 0) 397 buf = buffer; 398 399 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 400 if (res > 0) 401 enable_cpu_a011_workaround = 0; 402 else { 403 if (n >= HWCONFIG_BUFFER_SIZE) { 404 printf("fsl_cpu_a011 was not found. hwconfig variable " 405 "may be too long\n"); 406 } 407 enable_cpu_a011_workaround = 408 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 409 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 410 } 411 #endif 412 if (enable_cpu_a011_workaround) { 413 flush_dcache(); 414 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 415 sync(); 416 } 417 #endif 418 419 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 420 spin = getenv("spin_table_compat"); 421 if (spin && (*spin == 'n')) 422 spin_table_compat = 0; 423 else 424 spin_table_compat = 1; 425 #endif 426 427 puts ("L2: "); 428 429 #if defined(CONFIG_L2_CACHE) 430 volatile uint cache_ctl; 431 uint ver; 432 u32 l2siz_field; 433 434 ver = SVR_SOC_VER(svr); 435 436 asm("msync;isync"); 437 cache_ctl = l2cache->l2ctl; 438 439 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 440 if (cache_ctl & MPC85xx_L2CTL_L2E) { 441 /* Clear L2 SRAM memory-mapped base address */ 442 out_be32(&l2cache->l2srbar0, 0x0); 443 out_be32(&l2cache->l2srbar1, 0x0); 444 445 /* set MBECCDIS=0, SBECCDIS=0 */ 446 clrbits_be32(&l2cache->l2errdis, 447 (MPC85xx_L2ERRDIS_MBECC | 448 MPC85xx_L2ERRDIS_SBECC)); 449 450 /* set L2E=0, L2SRAM=0 */ 451 clrbits_be32(&l2cache->l2ctl, 452 (MPC85xx_L2CTL_L2E | 453 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 454 } 455 #endif 456 457 l2siz_field = (cache_ctl >> 28) & 0x3; 458 459 switch (l2siz_field) { 460 case 0x0: 461 printf(" unknown size (0x%08x)\n", cache_ctl); 462 return -1; 463 break; 464 case 0x1: 465 if (ver == SVR_8540 || ver == SVR_8560 || 466 ver == SVR_8541 || ver == SVR_8555) { 467 puts("128 KB "); 468 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 469 cache_ctl = 0xc4000000; 470 } else { 471 puts("256 KB "); 472 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 473 } 474 break; 475 case 0x2: 476 if (ver == SVR_8540 || ver == SVR_8560 || 477 ver == SVR_8541 || ver == SVR_8555) { 478 puts("256 KB "); 479 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 480 cache_ctl = 0xc8000000; 481 } else { 482 puts ("512 KB "); 483 /* set L2E=1, L2I=1, & L2SRAM=0 */ 484 cache_ctl = 0xc0000000; 485 } 486 break; 487 case 0x3: 488 puts("1024 KB "); 489 /* set L2E=1, L2I=1, & L2SRAM=0 */ 490 cache_ctl = 0xc0000000; 491 break; 492 } 493 494 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 495 puts("already enabled"); 496 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 497 u32 l2srbar = l2cache->l2srbar0; 498 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 499 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 500 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 501 l2cache->l2srbar0 = l2srbar; 502 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 503 } 504 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 505 puts("\n"); 506 } else { 507 asm("msync;isync"); 508 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 509 asm("msync;isync"); 510 puts("enabled\n"); 511 } 512 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 513 if (SVR_SOC_VER(svr) == SVR_P2040) { 514 puts("N/A\n"); 515 goto skip_l2; 516 } 517 518 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 519 520 /* invalidate the L2 cache */ 521 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 522 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 523 ; 524 525 #ifdef CONFIG_SYS_CACHE_STASHING 526 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 527 mtspr(SPRN_L2CSR1, (32 + 1)); 528 #endif 529 530 /* enable the cache */ 531 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 532 533 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 534 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 535 ; 536 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 537 } 538 539 skip_l2: 540 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 541 if (l2cache->l2csr0 & L2CSR0_L2E) 542 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); 543 544 enable_cluster_l2(); 545 #else 546 puts("disabled\n"); 547 #endif 548 549 enable_cpc(); 550 551 /* needs to be in ram since code uses global static vars */ 552 fsl_serdes_init(); 553 554 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 555 if (IS_SVR_REV(svr, 1, 0)) { 556 int i; 557 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 558 559 for (i = 0; i < 12; i++) { 560 p += i + (i > 5 ? 11 : 0); 561 out_be32(p, 0x2); 562 } 563 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 564 out_be32(p, 0x34); 565 } 566 #endif 567 568 #ifdef CONFIG_SYS_SRIO 569 srio_init(); 570 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 571 char *s = getenv("bootmaster"); 572 if (s) { 573 if (!strcmp(s, "SRIO1")) { 574 srio_boot_master(1); 575 srio_boot_master_release_slave(1); 576 } 577 if (!strcmp(s, "SRIO2")) { 578 srio_boot_master(2); 579 srio_boot_master_release_slave(2); 580 } 581 } 582 #endif 583 #endif 584 585 #if defined(CONFIG_MP) 586 setup_mp(); 587 #endif 588 589 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 590 { 591 if (SVR_MAJ(svr) < 3) { 592 void *p; 593 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 594 setbits_be32(p, 1 << (31 - 14)); 595 } 596 } 597 #endif 598 599 #ifdef CONFIG_SYS_LBC_LCRR 600 /* 601 * Modify the CLKDIV field of LCRR register to improve the writing 602 * speed for NOR flash. 603 */ 604 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 605 __raw_readl(&lbc->lcrr); 606 isync(); 607 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 608 udelay(100); 609 #endif 610 #endif 611 612 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 613 { 614 ccsr_usb_phy_t *usb_phy1 = 615 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 616 out_be32(&usb_phy1->usb_enable_override, 617 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 618 } 619 #endif 620 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 621 { 622 ccsr_usb_phy_t *usb_phy2 = 623 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 624 out_be32(&usb_phy2->usb_enable_override, 625 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 626 } 627 #endif 628 629 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 630 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 631 * multi-bit ECC errors which has impact on performance, so software 632 * should disable all ECC reporting from USB1 and USB2. 633 */ 634 if (IS_SVR_REV(get_svr(), 1, 0)) { 635 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 636 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 637 setbits_be32(&dcfg->ecccr1, 638 (DCSR_DCFG_ECC_DISABLE_USB1 | 639 DCSR_DCFG_ECC_DISABLE_USB2)); 640 } 641 #endif 642 643 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 644 ccsr_usb_phy_t *usb_phy = 645 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 646 setbits_be32(&usb_phy->pllprg[1], 647 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 648 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 649 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 650 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 651 setbits_be32(&usb_phy->port1.ctrl, 652 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 653 setbits_be32(&usb_phy->port1.drvvbuscfg, 654 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 655 setbits_be32(&usb_phy->port1.pwrfltcfg, 656 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 657 setbits_be32(&usb_phy->port2.ctrl, 658 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 659 setbits_be32(&usb_phy->port2.drvvbuscfg, 660 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 661 setbits_be32(&usb_phy->port2.pwrfltcfg, 662 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 663 #endif 664 665 #ifdef CONFIG_FMAN_ENET 666 fman_enet_init(); 667 #endif 668 669 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 670 /* 671 * For P1022/1013 Rev1.0 silicon, after power on SATA host 672 * controller is configured in legacy mode instead of the 673 * expected enterprise mode. Software needs to clear bit[28] 674 * of HControl register to change to enterprise mode from 675 * legacy mode. We assume that the controller is offline. 676 */ 677 if (IS_SVR_REV(svr, 1, 0) && 678 ((SVR_SOC_VER(svr) == SVR_P1022) || 679 (SVR_SOC_VER(svr) == SVR_P1013))) { 680 fsl_sata_reg_t *reg; 681 682 /* first SATA controller */ 683 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 684 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 685 686 /* second SATA controller */ 687 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 688 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 689 } 690 #endif 691 692 693 return 0; 694 } 695 696 extern void setup_ivors(void); 697 698 void arch_preboot_os(void) 699 { 700 u32 msr; 701 702 /* 703 * We are changing interrupt offsets and are about to boot the OS so 704 * we need to make sure we disable all async interrupts. EE is already 705 * disabled by the time we get called. 706 */ 707 msr = mfmsr(); 708 msr &= ~(MSR_ME|MSR_CE); 709 mtmsr(msr); 710 711 setup_ivors(); 712 } 713 714 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 715 int sata_initialize(void) 716 { 717 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 718 return __sata_initialize(); 719 720 return 1; 721 } 722 #endif 723 724 void cpu_secondary_init_r(void) 725 { 726 #ifdef CONFIG_QE 727 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 728 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 729 int ret; 730 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 731 732 /* load QE firmware from NAND flash to DDR first */ 733 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 734 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 735 736 if (ret && ret == -EUCLEAN) { 737 printf ("NAND read for QE firmware at offset %x failed %d\n", 738 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 739 } 740 #endif 741 qe_init(qe_base); 742 qe_reset(); 743 #endif 744 } 745