1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 #include <asm/fsl_serdes.h> 38 #include "mp.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_MPC8536 43 extern void fsl_serdes_init(void); 44 #endif 45 46 #ifdef CONFIG_QE 47 extern qe_iop_conf_t qe_iop_conf_tab[]; 48 extern void qe_config_iopin(u8 port, u8 pin, int dir, 49 int open_drain, int assign); 50 extern void qe_init(uint qe_base); 51 extern void qe_reset(void); 52 53 static void config_qe_ioports(void) 54 { 55 u8 port, pin; 56 int dir, open_drain, assign; 57 int i; 58 59 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 60 port = qe_iop_conf_tab[i].port; 61 pin = qe_iop_conf_tab[i].pin; 62 dir = qe_iop_conf_tab[i].dir; 63 open_drain = qe_iop_conf_tab[i].open_drain; 64 assign = qe_iop_conf_tab[i].assign; 65 qe_config_iopin(port, pin, dir, open_drain, assign); 66 } 67 } 68 #endif 69 70 #ifdef CONFIG_CPM2 71 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 72 { 73 int portnum; 74 75 for (portnum = 0; portnum < 4; portnum++) { 76 uint pmsk = 0, 77 ppar = 0, 78 psor = 0, 79 pdir = 0, 80 podr = 0, 81 pdat = 0; 82 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 83 iop_conf_t *eiopc = iopc + 32; 84 uint msk = 1; 85 86 /* 87 * NOTE: 88 * index 0 refers to pin 31, 89 * index 31 refers to pin 0 90 */ 91 while (iopc < eiopc) { 92 if (iopc->conf) { 93 pmsk |= msk; 94 if (iopc->ppar) 95 ppar |= msk; 96 if (iopc->psor) 97 psor |= msk; 98 if (iopc->pdir) 99 pdir |= msk; 100 if (iopc->podr) 101 podr |= msk; 102 if (iopc->pdat) 103 pdat |= msk; 104 } 105 106 msk <<= 1; 107 iopc++; 108 } 109 110 if (pmsk != 0) { 111 volatile ioport_t *iop = ioport_addr (cpm, portnum); 112 uint tpmsk = ~pmsk; 113 114 /* 115 * the (somewhat confused) paragraph at the 116 * bottom of page 35-5 warns that there might 117 * be "unknown behaviour" when programming 118 * PSORx and PDIRx, if PPARx = 1, so I 119 * decided this meant I had to disable the 120 * dedicated function first, and enable it 121 * last. 122 */ 123 iop->ppar &= tpmsk; 124 iop->psor = (iop->psor & tpmsk) | psor; 125 iop->podr = (iop->podr & tpmsk) | podr; 126 iop->pdat = (iop->pdat & tpmsk) | pdat; 127 iop->pdir = (iop->pdir & tpmsk) | pdir; 128 iop->ppar |= ppar; 129 } 130 } 131 } 132 #endif 133 134 /* 135 * Breathe some life into the CPU... 136 * 137 * Set up the memory map 138 * initialize a bunch of registers 139 */ 140 141 #ifdef CONFIG_FSL_CORENET 142 static void corenet_tb_init(void) 143 { 144 volatile ccsr_rcpm_t *rcpm = 145 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 146 volatile ccsr_pic_t *pic = 147 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 148 u32 whoami = in_be32(&pic->whoami); 149 150 /* Enable the timebase register for this core */ 151 out_be32(&rcpm->ctbenrl, (1 << whoami)); 152 } 153 #endif 154 155 void cpu_init_f (void) 156 { 157 volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 158 extern void m8560_cpm_reset (void); 159 #ifdef CONFIG_MPC8548 160 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 161 uint svr = get_svr(); 162 163 /* 164 * CPU2 errata workaround: A core hang possible while executing 165 * a msync instruction and a snoopable transaction from an I/O 166 * master tagged to make quick forward progress is present. 167 * Fixed in silicon rev 2.1. 168 */ 169 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 170 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 171 #endif 172 173 disable_tlb(14); 174 disable_tlb(15); 175 176 #ifdef CONFIG_CPM2 177 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 178 #endif 179 180 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary 181 * addresses - these have to be modified later when FLASH size 182 * has been determined 183 */ 184 #if defined(CONFIG_SYS_OR0_REMAP) 185 out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP); 186 #endif 187 #if defined(CONFIG_SYS_OR1_REMAP) 188 out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP); 189 #endif 190 191 /* now restrict to preliminary range */ 192 /* if cs1 is already set via debugger, leave cs0/cs1 alone */ 193 if (! memctl->br1 & 1) { 194 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) 195 out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM); 196 out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM); 197 #endif 198 199 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) 200 out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM); 201 out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM); 202 #endif 203 } 204 205 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) 206 out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM); 207 out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM); 208 #endif 209 210 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) 211 out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM); 212 out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM); 213 #endif 214 215 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) 216 out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM); 217 out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM); 218 #endif 219 220 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) 221 out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM); 222 out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM); 223 #endif 224 225 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) 226 out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM); 227 out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM); 228 #endif 229 230 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) 231 out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM); 232 out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM); 233 #endif 234 235 #if defined(CONFIG_CPM2) 236 m8560_cpm_reset(); 237 #endif 238 #ifdef CONFIG_QE 239 /* Config QE ioports */ 240 config_qe_ioports(); 241 #endif 242 #if defined(CONFIG_MPC8536) 243 fsl_serdes_init(); 244 #endif 245 #if defined(CONFIG_FSL_DMA) 246 dma_init(); 247 #endif 248 #ifdef CONFIG_FSL_CORENET 249 corenet_tb_init(); 250 #endif 251 init_used_tlb_cams(); 252 } 253 254 255 /* 256 * Initialize L2 as cache. 257 * 258 * The newer 8548, etc, parts have twice as much cache, but 259 * use the same bit-encoding as the older 8555, etc, parts. 260 * 261 */ 262 263 int cpu_init_r(void) 264 { 265 #ifdef CONFIG_SYS_LBC_LCRR 266 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 267 #endif 268 269 puts ("L2: "); 270 271 #if defined(CONFIG_L2_CACHE) 272 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 273 volatile uint cache_ctl; 274 uint svr, ver; 275 uint l2srbar; 276 u32 l2siz_field; 277 278 svr = get_svr(); 279 ver = SVR_SOC_VER(svr); 280 281 asm("msync;isync"); 282 cache_ctl = l2cache->l2ctl; 283 284 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 285 if (cache_ctl & MPC85xx_L2CTL_L2E) { 286 /* Clear L2 SRAM memory-mapped base address */ 287 out_be32(&l2cache->l2srbar0, 0x0); 288 out_be32(&l2cache->l2srbar1, 0x0); 289 290 /* set MBECCDIS=0, SBECCDIS=0 */ 291 clrbits_be32(&l2cache->l2errdis, 292 (MPC85xx_L2ERRDIS_MBECC | 293 MPC85xx_L2ERRDIS_SBECC)); 294 295 /* set L2E=0, L2SRAM=0 */ 296 clrbits_be32(&l2cache->l2ctl, 297 (MPC85xx_L2CTL_L2E | 298 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 299 } 300 #endif 301 302 l2siz_field = (cache_ctl >> 28) & 0x3; 303 304 switch (l2siz_field) { 305 case 0x0: 306 printf(" unknown size (0x%08x)\n", cache_ctl); 307 return -1; 308 break; 309 case 0x1: 310 if (ver == SVR_8540 || ver == SVR_8560 || 311 ver == SVR_8541 || ver == SVR_8541_E || 312 ver == SVR_8555 || ver == SVR_8555_E) { 313 puts("128 KB "); 314 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 315 cache_ctl = 0xc4000000; 316 } else { 317 puts("256 KB "); 318 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 319 } 320 break; 321 case 0x2: 322 if (ver == SVR_8540 || ver == SVR_8560 || 323 ver == SVR_8541 || ver == SVR_8541_E || 324 ver == SVR_8555 || ver == SVR_8555_E) { 325 puts("256 KB "); 326 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 327 cache_ctl = 0xc8000000; 328 } else { 329 puts ("512 KB "); 330 /* set L2E=1, L2I=1, & L2SRAM=0 */ 331 cache_ctl = 0xc0000000; 332 } 333 break; 334 case 0x3: 335 puts("1024 KB "); 336 /* set L2E=1, L2I=1, & L2SRAM=0 */ 337 cache_ctl = 0xc0000000; 338 break; 339 } 340 341 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 342 puts("already enabled"); 343 l2srbar = l2cache->l2srbar0; 344 #ifdef CONFIG_SYS_INIT_L2_ADDR 345 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 346 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 347 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 348 l2cache->l2srbar0 = l2srbar; 349 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 350 } 351 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 352 puts("\n"); 353 } else { 354 asm("msync;isync"); 355 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 356 asm("msync;isync"); 357 puts("enabled\n"); 358 } 359 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 360 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 361 362 /* invalidate the L2 cache */ 363 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 364 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 365 ; 366 367 #ifdef CONFIG_SYS_CACHE_STASHING 368 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 369 mtspr(SPRN_L2CSR1, (32 + 1)); 370 #endif 371 372 /* enable the cache */ 373 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 374 375 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 376 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 377 ; 378 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 379 } 380 #else 381 puts("disabled\n"); 382 #endif 383 #ifdef CONFIG_QE 384 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 385 qe_init(qe_base); 386 qe_reset(); 387 #endif 388 389 #if defined(CONFIG_MP) 390 setup_mp(); 391 #endif 392 393 #ifdef CONFIG_SYS_LBC_LCRR 394 /* 395 * Modify the CLKDIV field of LCRR register to improve the writing 396 * speed for NOR flash. 397 */ 398 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 399 __raw_readl(&lbc->lcrr); 400 isync(); 401 #endif 402 403 return 0; 404 } 405 406 extern void setup_ivors(void); 407 408 void arch_preboot_os(void) 409 { 410 u32 msr; 411 412 /* 413 * We are changing interrupt offsets and are about to boot the OS so 414 * we need to make sure we disable all async interrupts. EE is already 415 * disabled by the time we get called. 416 */ 417 msr = mfmsr(); 418 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 419 mtmsr(msr); 420 421 setup_ivors(); 422 } 423 424 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 425 int sata_initialize(void) 426 { 427 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 428 return __sata_initialize(); 429 430 return 1; 431 } 432 #endif 433