1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <watchdog.h> 31 #include <asm/processor.h> 32 #include <ioports.h> 33 #include <sata.h> 34 #include <fm_eth.h> 35 #include <asm/io.h> 36 #include <asm/cache.h> 37 #include <asm/mmu.h> 38 #include <asm/fsl_law.h> 39 #include <asm/fsl_serdes.h> 40 #include <linux/compiler.h> 41 #include "mp.h" 42 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 43 #include <nand.h> 44 #include <errno.h> 45 #endif 46 47 #include "../../../../drivers/block/fsl_sata.h" 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 extern void srio_init(void); 52 53 #ifdef CONFIG_QE 54 extern qe_iop_conf_t qe_iop_conf_tab[]; 55 extern void qe_config_iopin(u8 port, u8 pin, int dir, 56 int open_drain, int assign); 57 extern void qe_init(uint qe_base); 58 extern void qe_reset(void); 59 60 static void config_qe_ioports(void) 61 { 62 u8 port, pin; 63 int dir, open_drain, assign; 64 int i; 65 66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 67 port = qe_iop_conf_tab[i].port; 68 pin = qe_iop_conf_tab[i].pin; 69 dir = qe_iop_conf_tab[i].dir; 70 open_drain = qe_iop_conf_tab[i].open_drain; 71 assign = qe_iop_conf_tab[i].assign; 72 qe_config_iopin(port, pin, dir, open_drain, assign); 73 } 74 } 75 #endif 76 77 #ifdef CONFIG_CPM2 78 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 79 { 80 int portnum; 81 82 for (portnum = 0; portnum < 4; portnum++) { 83 uint pmsk = 0, 84 ppar = 0, 85 psor = 0, 86 pdir = 0, 87 podr = 0, 88 pdat = 0; 89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 90 iop_conf_t *eiopc = iopc + 32; 91 uint msk = 1; 92 93 /* 94 * NOTE: 95 * index 0 refers to pin 31, 96 * index 31 refers to pin 0 97 */ 98 while (iopc < eiopc) { 99 if (iopc->conf) { 100 pmsk |= msk; 101 if (iopc->ppar) 102 ppar |= msk; 103 if (iopc->psor) 104 psor |= msk; 105 if (iopc->pdir) 106 pdir |= msk; 107 if (iopc->podr) 108 podr |= msk; 109 if (iopc->pdat) 110 pdat |= msk; 111 } 112 113 msk <<= 1; 114 iopc++; 115 } 116 117 if (pmsk != 0) { 118 volatile ioport_t *iop = ioport_addr (cpm, portnum); 119 uint tpmsk = ~pmsk; 120 121 /* 122 * the (somewhat confused) paragraph at the 123 * bottom of page 35-5 warns that there might 124 * be "unknown behaviour" when programming 125 * PSORx and PDIRx, if PPARx = 1, so I 126 * decided this meant I had to disable the 127 * dedicated function first, and enable it 128 * last. 129 */ 130 iop->ppar &= tpmsk; 131 iop->psor = (iop->psor & tpmsk) | psor; 132 iop->podr = (iop->podr & tpmsk) | podr; 133 iop->pdat = (iop->pdat & tpmsk) | pdat; 134 iop->pdir = (iop->pdir & tpmsk) | pdir; 135 iop->ppar |= ppar; 136 } 137 } 138 } 139 #endif 140 141 #ifdef CONFIG_SYS_FSL_CPC 142 static void enable_cpc(void) 143 { 144 int i; 145 u32 size = 0; 146 147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 148 149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 150 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 151 size += CPC_CFG0_SZ_K(cpccfg0); 152 #ifdef CONFIG_RAMBOOT_PBL 153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 154 /* find and disable LAW of SRAM */ 155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 156 157 if (law.index == -1) { 158 printf("\nFatal error happened\n"); 159 return; 160 } 161 disable_law(law.index); 162 163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 164 out_be32(&cpc->cpccsr0, 0); 165 out_be32(&cpc->cpcsrcr0, 0); 166 } 167 #endif 168 169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 171 #endif 172 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 174 #endif 175 176 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 177 /* Read back to sync write */ 178 in_be32(&cpc->cpccsr0); 179 180 } 181 182 printf("Corenet Platform Cache: %d KB enabled\n", size); 183 } 184 185 void invalidate_cpc(void) 186 { 187 int i; 188 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 189 190 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 191 /* skip CPC when it used as all SRAM */ 192 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 193 continue; 194 /* Flash invalidate the CPC and clear all the locks */ 195 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 196 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 197 ; 198 } 199 } 200 #else 201 #define enable_cpc() 202 #define invalidate_cpc() 203 #endif /* CONFIG_SYS_FSL_CPC */ 204 205 /* 206 * Breathe some life into the CPU... 207 * 208 * Set up the memory map 209 * initialize a bunch of registers 210 */ 211 212 #ifdef CONFIG_FSL_CORENET 213 static void corenet_tb_init(void) 214 { 215 volatile ccsr_rcpm_t *rcpm = 216 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 217 volatile ccsr_pic_t *pic = 218 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 219 u32 whoami = in_be32(&pic->whoami); 220 221 /* Enable the timebase register for this core */ 222 out_be32(&rcpm->ctbenrl, (1 << whoami)); 223 } 224 #endif 225 226 void cpu_init_f (void) 227 { 228 extern void m8560_cpm_reset (void); 229 #ifdef CONFIG_SYS_DCSRBAR_PHYS 230 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 231 #endif 232 #if defined(CONFIG_SECURE_BOOT) 233 struct law_entry law; 234 #endif 235 #ifdef CONFIG_MPC8548 236 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 237 uint svr = get_svr(); 238 239 /* 240 * CPU2 errata workaround: A core hang possible while executing 241 * a msync instruction and a snoopable transaction from an I/O 242 * master tagged to make quick forward progress is present. 243 * Fixed in silicon rev 2.1. 244 */ 245 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 246 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 247 #endif 248 249 disable_tlb(14); 250 disable_tlb(15); 251 252 #if defined(CONFIG_SECURE_BOOT) 253 /* Disable the LAW created for NOR flash by the PBI commands */ 254 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 255 if (law.index != -1) 256 disable_law(law.index); 257 #endif 258 259 #ifdef CONFIG_CPM2 260 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 261 #endif 262 263 init_early_memctl_regs(); 264 265 #if defined(CONFIG_CPM2) 266 m8560_cpm_reset(); 267 #endif 268 #ifdef CONFIG_QE 269 /* Config QE ioports */ 270 config_qe_ioports(); 271 #endif 272 #if defined(CONFIG_FSL_DMA) 273 dma_init(); 274 #endif 275 #ifdef CONFIG_FSL_CORENET 276 corenet_tb_init(); 277 #endif 278 init_used_tlb_cams(); 279 280 /* Invalidate the CPC before DDR gets enabled */ 281 invalidate_cpc(); 282 283 #ifdef CONFIG_SYS_DCSRBAR_PHYS 284 /* set DCSRCR so that DCSR space is 1G */ 285 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 286 in_be32(&gur->dcsrcr); 287 #endif 288 289 } 290 291 /* Implement a dummy function for those platforms w/o SERDES */ 292 static void __fsl_serdes__init(void) 293 { 294 return ; 295 } 296 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 297 298 /* 299 * Initialize L2 as cache. 300 * 301 * The newer 8548, etc, parts have twice as much cache, but 302 * use the same bit-encoding as the older 8555, etc, parts. 303 * 304 */ 305 int cpu_init_r(void) 306 { 307 __maybe_unused u32 svr = get_svr(); 308 #ifdef CONFIG_SYS_LBC_LCRR 309 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 310 #endif 311 312 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 313 flush_dcache(); 314 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 315 sync(); 316 #endif 317 318 puts ("L2: "); 319 320 #if defined(CONFIG_L2_CACHE) 321 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 322 volatile uint cache_ctl; 323 uint ver; 324 u32 l2siz_field; 325 326 ver = SVR_SOC_VER(svr); 327 328 asm("msync;isync"); 329 cache_ctl = l2cache->l2ctl; 330 331 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 332 if (cache_ctl & MPC85xx_L2CTL_L2E) { 333 /* Clear L2 SRAM memory-mapped base address */ 334 out_be32(&l2cache->l2srbar0, 0x0); 335 out_be32(&l2cache->l2srbar1, 0x0); 336 337 /* set MBECCDIS=0, SBECCDIS=0 */ 338 clrbits_be32(&l2cache->l2errdis, 339 (MPC85xx_L2ERRDIS_MBECC | 340 MPC85xx_L2ERRDIS_SBECC)); 341 342 /* set L2E=0, L2SRAM=0 */ 343 clrbits_be32(&l2cache->l2ctl, 344 (MPC85xx_L2CTL_L2E | 345 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 346 } 347 #endif 348 349 l2siz_field = (cache_ctl >> 28) & 0x3; 350 351 switch (l2siz_field) { 352 case 0x0: 353 printf(" unknown size (0x%08x)\n", cache_ctl); 354 return -1; 355 break; 356 case 0x1: 357 if (ver == SVR_8540 || ver == SVR_8560 || 358 ver == SVR_8541 || ver == SVR_8541_E || 359 ver == SVR_8555 || ver == SVR_8555_E) { 360 puts("128 KB "); 361 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 362 cache_ctl = 0xc4000000; 363 } else { 364 puts("256 KB "); 365 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 366 } 367 break; 368 case 0x2: 369 if (ver == SVR_8540 || ver == SVR_8560 || 370 ver == SVR_8541 || ver == SVR_8541_E || 371 ver == SVR_8555 || ver == SVR_8555_E) { 372 puts("256 KB "); 373 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 374 cache_ctl = 0xc8000000; 375 } else { 376 puts ("512 KB "); 377 /* set L2E=1, L2I=1, & L2SRAM=0 */ 378 cache_ctl = 0xc0000000; 379 } 380 break; 381 case 0x3: 382 puts("1024 KB "); 383 /* set L2E=1, L2I=1, & L2SRAM=0 */ 384 cache_ctl = 0xc0000000; 385 break; 386 } 387 388 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 389 puts("already enabled"); 390 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 391 u32 l2srbar = l2cache->l2srbar0; 392 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 393 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 394 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 395 l2cache->l2srbar0 = l2srbar; 396 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 397 } 398 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 399 puts("\n"); 400 } else { 401 asm("msync;isync"); 402 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 403 asm("msync;isync"); 404 puts("enabled\n"); 405 } 406 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 407 if ((SVR_SOC_VER(svr) == SVR_P2040) || 408 (SVR_SOC_VER(svr) == SVR_P2040_E)) { 409 puts("N/A\n"); 410 goto skip_l2; 411 } 412 413 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 414 415 /* invalidate the L2 cache */ 416 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 417 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 418 ; 419 420 #ifdef CONFIG_SYS_CACHE_STASHING 421 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 422 mtspr(SPRN_L2CSR1, (32 + 1)); 423 #endif 424 425 /* enable the cache */ 426 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 427 428 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 429 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 430 ; 431 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 432 } 433 434 skip_l2: 435 #else 436 puts("disabled\n"); 437 #endif 438 439 enable_cpc(); 440 441 /* needs to be in ram since code uses global static vars */ 442 fsl_serdes_init(); 443 444 #ifdef CONFIG_SYS_SRIO 445 srio_init(); 446 #endif 447 448 #if defined(CONFIG_MP) 449 setup_mp(); 450 #endif 451 452 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136 453 { 454 void *p; 455 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 456 setbits_be32(p, 1 << (31 - 14)); 457 } 458 #endif 459 460 #ifdef CONFIG_SYS_LBC_LCRR 461 /* 462 * Modify the CLKDIV field of LCRR register to improve the writing 463 * speed for NOR flash. 464 */ 465 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 466 __raw_readl(&lbc->lcrr); 467 isync(); 468 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 469 udelay(100); 470 #endif 471 #endif 472 473 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 474 { 475 ccsr_usb_phy_t *usb_phy1 = 476 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 477 out_be32(&usb_phy1->usb_enable_override, 478 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 479 } 480 #endif 481 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 482 { 483 ccsr_usb_phy_t *usb_phy2 = 484 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 485 out_be32(&usb_phy2->usb_enable_override, 486 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 487 } 488 #endif 489 490 #ifdef CONFIG_FMAN_ENET 491 fman_enet_init(); 492 #endif 493 494 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 495 /* 496 * For P1022/1013 Rev1.0 silicon, after power on SATA host 497 * controller is configured in legacy mode instead of the 498 * expected enterprise mode. Software needs to clear bit[28] 499 * of HControl register to change to enterprise mode from 500 * legacy mode. We assume that the controller is offline. 501 */ 502 if (IS_SVR_REV(svr, 1, 0) && 503 ((SVR_SOC_VER(svr) == SVR_P1022) || 504 (SVR_SOC_VER(svr) == SVR_P1022_E) || 505 (SVR_SOC_VER(svr) == SVR_P1013) || 506 (SVR_SOC_VER(svr) == SVR_P1013_E))) { 507 fsl_sata_reg_t *reg; 508 509 /* first SATA controller */ 510 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 511 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 512 513 /* second SATA controller */ 514 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 515 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 516 } 517 #endif 518 519 520 return 0; 521 } 522 523 extern void setup_ivors(void); 524 525 void arch_preboot_os(void) 526 { 527 u32 msr; 528 529 /* 530 * We are changing interrupt offsets and are about to boot the OS so 531 * we need to make sure we disable all async interrupts. EE is already 532 * disabled by the time we get called. 533 */ 534 msr = mfmsr(); 535 msr &= ~(MSR_ME|MSR_CE|MSR_DE); 536 mtmsr(msr); 537 538 setup_ivors(); 539 } 540 541 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 542 int sata_initialize(void) 543 { 544 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 545 return __sata_initialize(); 546 547 return 1; 548 } 549 #endif 550 551 void cpu_secondary_init_r(void) 552 { 553 #ifdef CONFIG_QE 554 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 555 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 556 int ret; 557 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 558 559 /* load QE firmware from NAND flash to DDR first */ 560 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 561 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 562 563 if (ret && ret == -EUCLEAN) { 564 printf ("NAND read for QE firmware at offset %x failed %d\n", 565 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 566 } 567 #endif 568 qe_init(qe_base); 569 qe_reset(); 570 #endif 571 } 572