1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_errata.h> 23 #include <asm/fsl_law.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_srio.h> 26 #include <fsl_usb.h> 27 #include <hwconfig.h> 28 #include <linux/compiler.h> 29 #include "mp.h" 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 31 #include <nand.h> 32 #include <errno.h> 33 #endif 34 35 #include "../../../../drivers/block/fsl_sata.h" 36 #ifdef CONFIG_U_QE 37 #include "../../../../drivers/qe/qe.h" 38 #endif 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 43 /* 44 * For deriving usb clock from 100MHz sysclk, reference divisor is set 45 * to a value of 5, which gives an intermediate value 20(100/5). The 46 * multiplication factor integer is set to 24, which when multiplied to 47 * above intermediate value provides clock for usb ip. 48 */ 49 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 50 { 51 sys_info_t sysinfo; 52 53 get_sys_info(&sysinfo); 54 if (sysinfo.diff_sysclk == 1) { 55 clrbits_be32(&usb_phy->pllprg[1], 56 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 57 setbits_be32(&usb_phy->pllprg[1], 58 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 60 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 61 } 62 } 63 #endif 64 65 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 66 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 67 { 68 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 69 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 70 71 /* Increase Disconnect Threshold by 50mV */ 72 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 73 INC_DCNT_THRESHOLD_50MV; 74 /* Enable programming of USB High speed Disconnect threshold */ 75 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 76 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 77 78 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 79 /* Increase Disconnect Threshold by 50mV */ 80 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 81 INC_DCNT_THRESHOLD_50MV; 82 /* Enable programming of USB High speed Disconnect threshold */ 83 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 84 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 85 #else 86 87 u32 temp = 0; 88 u32 status = in_be32(&usb_phy->status1); 89 90 u32 squelch_prog_rd_0_2 = 91 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 92 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 93 94 u32 squelch_prog_rd_3_5 = 95 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 96 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 97 98 setbits_be32(&usb_phy->config1, 99 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 100 setbits_be32(&usb_phy->config2, 101 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 102 103 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 104 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 105 106 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 108 #endif 109 } 110 #endif 111 112 113 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 114 extern qe_iop_conf_t qe_iop_conf_tab[]; 115 extern void qe_config_iopin(u8 port, u8 pin, int dir, 116 int open_drain, int assign); 117 extern void qe_init(uint qe_base); 118 extern void qe_reset(void); 119 120 static void config_qe_ioports(void) 121 { 122 u8 port, pin; 123 int dir, open_drain, assign; 124 int i; 125 126 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 127 port = qe_iop_conf_tab[i].port; 128 pin = qe_iop_conf_tab[i].pin; 129 dir = qe_iop_conf_tab[i].dir; 130 open_drain = qe_iop_conf_tab[i].open_drain; 131 assign = qe_iop_conf_tab[i].assign; 132 qe_config_iopin(port, pin, dir, open_drain, assign); 133 } 134 } 135 #endif 136 137 #ifdef CONFIG_CPM2 138 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 139 { 140 int portnum; 141 142 for (portnum = 0; portnum < 4; portnum++) { 143 uint pmsk = 0, 144 ppar = 0, 145 psor = 0, 146 pdir = 0, 147 podr = 0, 148 pdat = 0; 149 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 150 iop_conf_t *eiopc = iopc + 32; 151 uint msk = 1; 152 153 /* 154 * NOTE: 155 * index 0 refers to pin 31, 156 * index 31 refers to pin 0 157 */ 158 while (iopc < eiopc) { 159 if (iopc->conf) { 160 pmsk |= msk; 161 if (iopc->ppar) 162 ppar |= msk; 163 if (iopc->psor) 164 psor |= msk; 165 if (iopc->pdir) 166 pdir |= msk; 167 if (iopc->podr) 168 podr |= msk; 169 if (iopc->pdat) 170 pdat |= msk; 171 } 172 173 msk <<= 1; 174 iopc++; 175 } 176 177 if (pmsk != 0) { 178 volatile ioport_t *iop = ioport_addr (cpm, portnum); 179 uint tpmsk = ~pmsk; 180 181 /* 182 * the (somewhat confused) paragraph at the 183 * bottom of page 35-5 warns that there might 184 * be "unknown behaviour" when programming 185 * PSORx and PDIRx, if PPARx = 1, so I 186 * decided this meant I had to disable the 187 * dedicated function first, and enable it 188 * last. 189 */ 190 iop->ppar &= tpmsk; 191 iop->psor = (iop->psor & tpmsk) | psor; 192 iop->podr = (iop->podr & tpmsk) | podr; 193 iop->pdat = (iop->pdat & tpmsk) | pdat; 194 iop->pdir = (iop->pdir & tpmsk) | pdir; 195 iop->ppar |= ppar; 196 } 197 } 198 } 199 #endif 200 201 #ifdef CONFIG_SYS_FSL_CPC 202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 203 void disable_cpc_sram(void) 204 { 205 int i; 206 207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 208 209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 210 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 211 /* find and disable LAW of SRAM */ 212 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 213 214 if (law.index == -1) { 215 printf("\nFatal error happened\n"); 216 return; 217 } 218 disable_law(law.index); 219 220 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 221 out_be32(&cpc->cpccsr0, 0); 222 out_be32(&cpc->cpcsrcr0, 0); 223 } 224 } 225 } 226 #endif 227 228 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 229 #ifdef CONFIG_POST 230 #error POST memory test cannot be enabled with TDM 231 #endif 232 static void enable_tdm_law(void) 233 { 234 int ret; 235 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 236 int tdm_hwconfig_enabled = 0; 237 238 /* 239 * Extract hwconfig from environment since environment 240 * is not setup properly yet. Search for tdm entry in 241 * hwconfig. 242 */ 243 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 244 if (ret > 0) { 245 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 246 /* If tdm is defined in hwconfig, set law for tdm workaround */ 247 if (tdm_hwconfig_enabled) 248 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 249 LAW_TRGT_IF_CCSR); 250 } 251 } 252 #endif 253 254 void enable_cpc(void) 255 { 256 int i; 257 int ret; 258 u32 size = 0; 259 u32 cpccfg0; 260 char buffer[HWCONFIG_BUFFER_SIZE]; 261 char cpc_subarg[16]; 262 bool have_hwconfig = false; 263 int cpc_args = 0; 264 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 265 266 /* Extract hwconfig from environment */ 267 ret = getenv_f("hwconfig", buffer, sizeof(buffer)); 268 if (ret > 0) { 269 /* 270 * If "en_cpc" is not defined in hwconfig then by default all 271 * cpcs are enable. If this config is defined then individual 272 * cpcs which have to be enabled should also be defined. 273 * e.g en_cpc:cpc1,cpc2; 274 */ 275 if (hwconfig_f("en_cpc", buffer)) 276 have_hwconfig = true; 277 } 278 279 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 280 if (have_hwconfig) { 281 sprintf(cpc_subarg, "cpc%u", i + 1); 282 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); 283 if (cpc_args == 0) 284 continue; 285 } 286 cpccfg0 = in_be32(&cpc->cpccfg0); 287 size += CPC_CFG0_SZ_K(cpccfg0); 288 289 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 290 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 291 #endif 292 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 293 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 294 #endif 295 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 296 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 297 #endif 298 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 299 if (has_erratum_a006379()) { 300 setbits_be32(&cpc->cpchdbcr0, 301 CPC_HDBCR0_SPLRU_LEVEL_EN); 302 } 303 #endif 304 305 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 306 /* Read back to sync write */ 307 in_be32(&cpc->cpccsr0); 308 309 } 310 311 puts("Corenet Platform Cache: "); 312 print_size(size * 1024, " enabled\n"); 313 } 314 315 static void invalidate_cpc(void) 316 { 317 int i; 318 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 319 320 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 321 /* skip CPC when it used as all SRAM */ 322 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 323 continue; 324 /* Flash invalidate the CPC and clear all the locks */ 325 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 326 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 327 ; 328 } 329 } 330 #else 331 #define enable_cpc() 332 #define invalidate_cpc() 333 #define disable_cpc_sram() 334 #endif /* CONFIG_SYS_FSL_CPC */ 335 336 /* 337 * Breathe some life into the CPU... 338 * 339 * Set up the memory map 340 * initialize a bunch of registers 341 */ 342 343 #ifdef CONFIG_FSL_CORENET 344 static void corenet_tb_init(void) 345 { 346 volatile ccsr_rcpm_t *rcpm = 347 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 348 volatile ccsr_pic_t *pic = 349 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 350 u32 whoami = in_be32(&pic->whoami); 351 352 /* Enable the timebase register for this core */ 353 out_be32(&rcpm->ctbenrl, (1 << whoami)); 354 } 355 #endif 356 357 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 358 void fsl_erratum_a007212_workaround(void) 359 { 360 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 361 u32 ddr_pll_ratio; 362 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 363 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 364 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 365 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 366 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 367 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 368 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 369 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 370 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 371 #endif 372 #endif 373 /* 374 * Even this workaround applies to selected version of SoCs, it is 375 * safe to apply to all versions, with the limitation of odd ratios. 376 * If RCW has disabled DDR PLL, we have to apply this workaround, 377 * otherwise DDR will not work. 378 */ 379 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 380 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 381 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 382 /* check if RCW sets ratio to 0, required by this workaround */ 383 if (ddr_pll_ratio != 0) 384 return; 385 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 386 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 387 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 388 /* check if reserved bits have the desired ratio */ 389 if (ddr_pll_ratio == 0) { 390 printf("Error: Unknown DDR PLL ratio!\n"); 391 return; 392 } 393 ddr_pll_ratio >>= 1; 394 395 setbits_be32(plldadcr1, 0x02000001); 396 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 397 setbits_be32(plldadcr2, 0x02000001); 398 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 399 setbits_be32(plldadcr3, 0x02000001); 400 #endif 401 #endif 402 setbits_be32(dpdovrcr4, 0xe0000000); 403 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 404 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 405 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 406 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 407 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 408 #endif 409 #endif 410 udelay(100); 411 clrbits_be32(plldadcr1, 0x02000001); 412 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 413 clrbits_be32(plldadcr2, 0x02000001); 414 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) 415 clrbits_be32(plldadcr3, 0x02000001); 416 #endif 417 #endif 418 clrbits_be32(dpdovrcr4, 0xe0000000); 419 } 420 #endif 421 422 ulong cpu_init_f(void) 423 { 424 ulong flag = 0; 425 extern void m8560_cpm_reset (void); 426 #ifdef CONFIG_SYS_DCSRBAR_PHYS 427 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 428 #endif 429 #if defined(CONFIG_SECURE_BOOT) 430 struct law_entry law; 431 #endif 432 #ifdef CONFIG_MPC8548 433 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 434 uint svr = get_svr(); 435 436 /* 437 * CPU2 errata workaround: A core hang possible while executing 438 * a msync instruction and a snoopable transaction from an I/O 439 * master tagged to make quick forward progress is present. 440 * Fixed in silicon rev 2.1. 441 */ 442 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 443 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 444 #endif 445 446 disable_tlb(14); 447 disable_tlb(15); 448 449 #if defined(CONFIG_SECURE_BOOT) 450 /* Disable the LAW created for NOR flash by the PBI commands */ 451 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 452 if (law.index != -1) 453 disable_law(law.index); 454 455 #if defined(CONFIG_SYS_CPC_REINIT_F) 456 disable_cpc_sram(); 457 #endif 458 #endif 459 460 #ifdef CONFIG_CPM2 461 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 462 #endif 463 464 init_early_memctl_regs(); 465 466 #if defined(CONFIG_CPM2) 467 m8560_cpm_reset(); 468 #endif 469 470 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 471 /* Config QE ioports */ 472 config_qe_ioports(); 473 #endif 474 475 #if defined(CONFIG_FSL_DMA) 476 dma_init(); 477 #endif 478 #ifdef CONFIG_FSL_CORENET 479 corenet_tb_init(); 480 #endif 481 init_used_tlb_cams(); 482 483 /* Invalidate the CPC before DDR gets enabled */ 484 invalidate_cpc(); 485 486 #ifdef CONFIG_SYS_DCSRBAR_PHYS 487 /* set DCSRCR so that DCSR space is 1G */ 488 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 489 in_be32(&gur->dcsrcr); 490 #endif 491 492 #ifdef CONFIG_SYS_DCSRBAR_PHYS 493 #ifdef CONFIG_DEEP_SLEEP 494 /* disable the console if boot from deep sleep */ 495 if (in_be32(&gur->scrtsr[0]) & (1 << 3)) 496 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 497 #endif 498 #endif 499 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 500 fsl_erratum_a007212_workaround(); 501 #endif 502 503 return flag; 504 } 505 506 /* Implement a dummy function for those platforms w/o SERDES */ 507 static void __fsl_serdes__init(void) 508 { 509 return ; 510 } 511 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 512 513 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 514 int enable_cluster_l2(void) 515 { 516 int i = 0; 517 u32 cluster, svr = get_svr(); 518 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 519 struct ccsr_cluster_l2 __iomem *l2cache; 520 521 /* only the L2 of first cluster should be enabled as expected on T4080, 522 * but there is no EOC in the first cluster as HW sake, so return here 523 * to skip enabling L2 cache of the 2nd cluster. 524 */ 525 if (SVR_SOC_VER(svr) == SVR_T4080) 526 return 0; 527 528 cluster = in_be32(&gur->tp_cluster[i].lower); 529 if (cluster & TP_CLUSTER_EOC) 530 return 0; 531 532 /* The first cache has already been set up, so skip it */ 533 i++; 534 535 /* Look through the remaining clusters, and set up their caches */ 536 do { 537 int j, cluster_valid = 0; 538 539 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 540 541 cluster = in_be32(&gur->tp_cluster[i].lower); 542 543 /* check that at least one core/accel is enabled in cluster */ 544 for (j = 0; j < 4; j++) { 545 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 546 u32 type = in_be32(&gur->tp_ityp[idx]); 547 548 if ((type & TP_ITYP_AV) && 549 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 550 cluster_valid = 1; 551 } 552 553 if (cluster_valid) { 554 /* set stash ID to (cluster) * 2 + 32 + 1 */ 555 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 556 557 printf("enable l2 for cluster %d %p\n", i, l2cache); 558 559 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 560 while ((in_be32(&l2cache->l2csr0) 561 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 562 ; 563 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 564 } 565 i++; 566 } while (!(cluster & TP_CLUSTER_EOC)); 567 568 return 0; 569 } 570 #endif 571 572 /* 573 * Initialize L2 as cache. 574 */ 575 int l2cache_init(void) 576 { 577 __maybe_unused u32 svr = get_svr(); 578 #ifdef CONFIG_L2_CACHE 579 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 580 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 581 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 582 #endif 583 584 puts ("L2: "); 585 586 #if defined(CONFIG_L2_CACHE) 587 volatile uint cache_ctl; 588 uint ver; 589 u32 l2siz_field; 590 591 ver = SVR_SOC_VER(svr); 592 593 asm("msync;isync"); 594 cache_ctl = l2cache->l2ctl; 595 596 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 597 if (cache_ctl & MPC85xx_L2CTL_L2E) { 598 /* Clear L2 SRAM memory-mapped base address */ 599 out_be32(&l2cache->l2srbar0, 0x0); 600 out_be32(&l2cache->l2srbar1, 0x0); 601 602 /* set MBECCDIS=0, SBECCDIS=0 */ 603 clrbits_be32(&l2cache->l2errdis, 604 (MPC85xx_L2ERRDIS_MBECC | 605 MPC85xx_L2ERRDIS_SBECC)); 606 607 /* set L2E=0, L2SRAM=0 */ 608 clrbits_be32(&l2cache->l2ctl, 609 (MPC85xx_L2CTL_L2E | 610 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 611 } 612 #endif 613 614 l2siz_field = (cache_ctl >> 28) & 0x3; 615 616 switch (l2siz_field) { 617 case 0x0: 618 printf(" unknown size (0x%08x)\n", cache_ctl); 619 return -1; 620 break; 621 case 0x1: 622 if (ver == SVR_8540 || ver == SVR_8560 || 623 ver == SVR_8541 || ver == SVR_8555) { 624 puts("128 KiB "); 625 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 626 cache_ctl = 0xc4000000; 627 } else { 628 puts("256 KiB "); 629 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 630 } 631 break; 632 case 0x2: 633 if (ver == SVR_8540 || ver == SVR_8560 || 634 ver == SVR_8541 || ver == SVR_8555) { 635 puts("256 KiB "); 636 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 637 cache_ctl = 0xc8000000; 638 } else { 639 puts("512 KiB "); 640 /* set L2E=1, L2I=1, & L2SRAM=0 */ 641 cache_ctl = 0xc0000000; 642 } 643 break; 644 case 0x3: 645 puts("1024 KiB "); 646 /* set L2E=1, L2I=1, & L2SRAM=0 */ 647 cache_ctl = 0xc0000000; 648 break; 649 } 650 651 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 652 puts("already enabled"); 653 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 654 u32 l2srbar = l2cache->l2srbar0; 655 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 656 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 657 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 658 l2cache->l2srbar0 = l2srbar; 659 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 660 } 661 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 662 puts("\n"); 663 } else { 664 asm("msync;isync"); 665 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 666 asm("msync;isync"); 667 puts("enabled\n"); 668 } 669 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 670 if (SVR_SOC_VER(svr) == SVR_P2040) { 671 puts("N/A\n"); 672 goto skip_l2; 673 } 674 675 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 676 677 /* invalidate the L2 cache */ 678 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 679 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 680 ; 681 682 #ifdef CONFIG_SYS_CACHE_STASHING 683 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 684 mtspr(SPRN_L2CSR1, (32 + 1)); 685 #endif 686 687 /* enable the cache */ 688 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 689 690 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 691 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 692 ; 693 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 694 } 695 696 skip_l2: 697 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 698 if (l2cache->l2csr0 & L2CSR0_L2E) 699 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 700 " enabled\n"); 701 702 enable_cluster_l2(); 703 #else 704 puts("disabled\n"); 705 #endif 706 707 return 0; 708 } 709 710 /* 711 * 712 * The newer 8548, etc, parts have twice as much cache, but 713 * use the same bit-encoding as the older 8555, etc, parts. 714 * 715 */ 716 int cpu_init_r(void) 717 { 718 __maybe_unused u32 svr = get_svr(); 719 #ifdef CONFIG_SYS_LBC_LCRR 720 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 721 #endif 722 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 723 extern int spin_table_compat; 724 const char *spin; 725 #endif 726 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 727 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 728 #endif 729 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 730 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 731 /* 732 * CPU22 and NMG_CPU_A011 share the same workaround. 733 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 734 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 735 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 736 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 737 * be disabled by hwconfig with syntax: 738 * 739 * fsl_cpu_a011:disable 740 */ 741 extern int enable_cpu_a011_workaround; 742 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 743 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 744 #else 745 char buffer[HWCONFIG_BUFFER_SIZE]; 746 char *buf = NULL; 747 int n, res; 748 749 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 750 if (n > 0) 751 buf = buffer; 752 753 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 754 if (res > 0) { 755 enable_cpu_a011_workaround = 0; 756 } else { 757 if (n >= HWCONFIG_BUFFER_SIZE) { 758 printf("fsl_cpu_a011 was not found. hwconfig variable " 759 "may be too long\n"); 760 } 761 enable_cpu_a011_workaround = 762 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 763 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 764 } 765 #endif 766 if (enable_cpu_a011_workaround) { 767 flush_dcache(); 768 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 769 sync(); 770 } 771 #endif 772 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 773 /* 774 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 775 * in write shadow mode. Checking DCWS before setting SPR 976. 776 */ 777 if (mfspr(L1CSR2) & L1CSR2_DCWS) 778 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 779 #endif 780 781 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 782 spin = getenv("spin_table_compat"); 783 if (spin && (*spin == 'n')) 784 spin_table_compat = 0; 785 else 786 spin_table_compat = 1; 787 #endif 788 789 l2cache_init(); 790 #if defined(CONFIG_RAMBOOT_PBL) 791 disable_cpc_sram(); 792 #endif 793 enable_cpc(); 794 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 795 enable_tdm_law(); 796 #endif 797 798 #ifndef CONFIG_SYS_FSL_NO_SERDES 799 /* needs to be in ram since code uses global static vars */ 800 fsl_serdes_init(); 801 #endif 802 803 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 804 #define MCFGR_AXIPIPE 0x000000f0 805 if (IS_SVR_REV(svr, 1, 0)) 806 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 807 #endif 808 809 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 810 if (IS_SVR_REV(svr, 1, 0)) { 811 int i; 812 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 813 814 for (i = 0; i < 12; i++) { 815 p += i + (i > 5 ? 11 : 0); 816 out_be32(p, 0x2); 817 } 818 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 819 out_be32(p, 0x34); 820 } 821 #endif 822 823 #ifdef CONFIG_SYS_SRIO 824 srio_init(); 825 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 826 char *s = getenv("bootmaster"); 827 if (s) { 828 if (!strcmp(s, "SRIO1")) { 829 srio_boot_master(1); 830 srio_boot_master_release_slave(1); 831 } 832 if (!strcmp(s, "SRIO2")) { 833 srio_boot_master(2); 834 srio_boot_master_release_slave(2); 835 } 836 } 837 #endif 838 #endif 839 840 #if defined(CONFIG_MP) 841 setup_mp(); 842 #endif 843 844 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 845 { 846 if (SVR_MAJ(svr) < 3) { 847 void *p; 848 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 849 setbits_be32(p, 1 << (31 - 14)); 850 } 851 } 852 #endif 853 854 #ifdef CONFIG_SYS_LBC_LCRR 855 /* 856 * Modify the CLKDIV field of LCRR register to improve the writing 857 * speed for NOR flash. 858 */ 859 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 860 __raw_readl(&lbc->lcrr); 861 isync(); 862 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 863 udelay(100); 864 #endif 865 #endif 866 867 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 868 { 869 struct ccsr_usb_phy __iomem *usb_phy1 = 870 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 871 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 872 if (has_erratum_a006261()) 873 fsl_erratum_a006261_workaround(usb_phy1); 874 #endif 875 out_be32(&usb_phy1->usb_enable_override, 876 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 877 } 878 #endif 879 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 880 { 881 struct ccsr_usb_phy __iomem *usb_phy2 = 882 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 883 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 884 if (has_erratum_a006261()) 885 fsl_erratum_a006261_workaround(usb_phy2); 886 #endif 887 out_be32(&usb_phy2->usb_enable_override, 888 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 889 } 890 #endif 891 892 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 893 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 894 * multi-bit ECC errors which has impact on performance, so software 895 * should disable all ECC reporting from USB1 and USB2. 896 */ 897 if (IS_SVR_REV(get_svr(), 1, 0)) { 898 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 899 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 900 setbits_be32(&dcfg->ecccr1, 901 (DCSR_DCFG_ECC_DISABLE_USB1 | 902 DCSR_DCFG_ECC_DISABLE_USB2)); 903 } 904 #endif 905 906 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 907 struct ccsr_usb_phy __iomem *usb_phy = 908 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 909 setbits_be32(&usb_phy->pllprg[1], 910 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 911 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 912 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 913 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 914 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 915 usb_single_source_clk_configure(usb_phy); 916 #endif 917 setbits_be32(&usb_phy->port1.ctrl, 918 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 919 setbits_be32(&usb_phy->port1.drvvbuscfg, 920 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 921 setbits_be32(&usb_phy->port1.pwrfltcfg, 922 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 923 setbits_be32(&usb_phy->port2.ctrl, 924 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 925 setbits_be32(&usb_phy->port2.drvvbuscfg, 926 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 927 setbits_be32(&usb_phy->port2.pwrfltcfg, 928 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 929 930 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 931 if (has_erratum_a006261()) 932 fsl_erratum_a006261_workaround(usb_phy); 933 #endif 934 935 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 936 937 #ifdef CONFIG_FMAN_ENET 938 fman_enet_init(); 939 #endif 940 941 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 942 /* 943 * For P1022/1013 Rev1.0 silicon, after power on SATA host 944 * controller is configured in legacy mode instead of the 945 * expected enterprise mode. Software needs to clear bit[28] 946 * of HControl register to change to enterprise mode from 947 * legacy mode. We assume that the controller is offline. 948 */ 949 if (IS_SVR_REV(svr, 1, 0) && 950 ((SVR_SOC_VER(svr) == SVR_P1022) || 951 (SVR_SOC_VER(svr) == SVR_P1013))) { 952 fsl_sata_reg_t *reg; 953 954 /* first SATA controller */ 955 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 956 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 957 958 /* second SATA controller */ 959 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 960 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 961 } 962 #endif 963 964 init_used_tlb_cams(); 965 966 return 0; 967 } 968 969 void arch_preboot_os(void) 970 { 971 u32 msr; 972 973 /* 974 * We are changing interrupt offsets and are about to boot the OS so 975 * we need to make sure we disable all async interrupts. EE is already 976 * disabled by the time we get called. 977 */ 978 msr = mfmsr(); 979 msr &= ~(MSR_ME|MSR_CE); 980 mtmsr(msr); 981 } 982 983 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 984 int sata_initialize(void) 985 { 986 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 987 return __sata_initialize(); 988 989 return 1; 990 } 991 #endif 992 993 void cpu_secondary_init_r(void) 994 { 995 #ifdef CONFIG_U_QE 996 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 997 #elif defined CONFIG_QE 998 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 999 #endif 1000 1001 #ifdef CONFIG_QE 1002 qe_init(qe_base); 1003 qe_reset(); 1004 #endif 1005 } 1006