1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2003 Motorola Inc. 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 6 * 7 * (C) Copyright 2000 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <watchdog.h> 15 #include <asm/processor.h> 16 #include <ioports.h> 17 #include <sata.h> 18 #include <fm_eth.h> 19 #include <asm/io.h> 20 #include <asm/cache.h> 21 #include <asm/mmu.h> 22 #include <asm/fsl_law.h> 23 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_srio.h> 25 #include <hwconfig.h> 26 #include <linux/compiler.h> 27 #include "mp.h" 28 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 29 #include <nand.h> 30 #include <errno.h> 31 #endif 32 33 #include "../../../../drivers/block/fsl_sata.h" 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifdef CONFIG_QE 38 extern qe_iop_conf_t qe_iop_conf_tab[]; 39 extern void qe_config_iopin(u8 port, u8 pin, int dir, 40 int open_drain, int assign); 41 extern void qe_init(uint qe_base); 42 extern void qe_reset(void); 43 44 static void config_qe_ioports(void) 45 { 46 u8 port, pin; 47 int dir, open_drain, assign; 48 int i; 49 50 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 51 port = qe_iop_conf_tab[i].port; 52 pin = qe_iop_conf_tab[i].pin; 53 dir = qe_iop_conf_tab[i].dir; 54 open_drain = qe_iop_conf_tab[i].open_drain; 55 assign = qe_iop_conf_tab[i].assign; 56 qe_config_iopin(port, pin, dir, open_drain, assign); 57 } 58 } 59 #endif 60 61 #ifdef CONFIG_CPM2 62 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 63 { 64 int portnum; 65 66 for (portnum = 0; portnum < 4; portnum++) { 67 uint pmsk = 0, 68 ppar = 0, 69 psor = 0, 70 pdir = 0, 71 podr = 0, 72 pdat = 0; 73 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 74 iop_conf_t *eiopc = iopc + 32; 75 uint msk = 1; 76 77 /* 78 * NOTE: 79 * index 0 refers to pin 31, 80 * index 31 refers to pin 0 81 */ 82 while (iopc < eiopc) { 83 if (iopc->conf) { 84 pmsk |= msk; 85 if (iopc->ppar) 86 ppar |= msk; 87 if (iopc->psor) 88 psor |= msk; 89 if (iopc->pdir) 90 pdir |= msk; 91 if (iopc->podr) 92 podr |= msk; 93 if (iopc->pdat) 94 pdat |= msk; 95 } 96 97 msk <<= 1; 98 iopc++; 99 } 100 101 if (pmsk != 0) { 102 volatile ioport_t *iop = ioport_addr (cpm, portnum); 103 uint tpmsk = ~pmsk; 104 105 /* 106 * the (somewhat confused) paragraph at the 107 * bottom of page 35-5 warns that there might 108 * be "unknown behaviour" when programming 109 * PSORx and PDIRx, if PPARx = 1, so I 110 * decided this meant I had to disable the 111 * dedicated function first, and enable it 112 * last. 113 */ 114 iop->ppar &= tpmsk; 115 iop->psor = (iop->psor & tpmsk) | psor; 116 iop->podr = (iop->podr & tpmsk) | podr; 117 iop->pdat = (iop->pdat & tpmsk) | pdat; 118 iop->pdir = (iop->pdir & tpmsk) | pdir; 119 iop->ppar |= ppar; 120 } 121 } 122 } 123 #endif 124 125 #ifdef CONFIG_SYS_FSL_CPC 126 static void enable_cpc(void) 127 { 128 int i; 129 u32 size = 0; 130 131 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 132 133 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 134 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 135 size += CPC_CFG0_SZ_K(cpccfg0); 136 #ifdef CONFIG_RAMBOOT_PBL 137 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 138 /* find and disable LAW of SRAM */ 139 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 140 141 if (law.index == -1) { 142 printf("\nFatal error happened\n"); 143 return; 144 } 145 disable_law(law.index); 146 147 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 148 out_be32(&cpc->cpccsr0, 0); 149 out_be32(&cpc->cpcsrcr0, 0); 150 } 151 #endif 152 153 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 154 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 155 #endif 156 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 157 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 158 #endif 159 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 160 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 161 #endif 162 163 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 164 /* Read back to sync write */ 165 in_be32(&cpc->cpccsr0); 166 167 } 168 169 printf("Corenet Platform Cache: %d KB enabled\n", size); 170 } 171 172 static void invalidate_cpc(void) 173 { 174 int i; 175 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 176 177 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 178 /* skip CPC when it used as all SRAM */ 179 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 180 continue; 181 /* Flash invalidate the CPC and clear all the locks */ 182 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 183 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 184 ; 185 } 186 } 187 #else 188 #define enable_cpc() 189 #define invalidate_cpc() 190 #endif /* CONFIG_SYS_FSL_CPC */ 191 192 /* 193 * Breathe some life into the CPU... 194 * 195 * Set up the memory map 196 * initialize a bunch of registers 197 */ 198 199 #ifdef CONFIG_FSL_CORENET 200 static void corenet_tb_init(void) 201 { 202 volatile ccsr_rcpm_t *rcpm = 203 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 204 volatile ccsr_pic_t *pic = 205 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 206 u32 whoami = in_be32(&pic->whoami); 207 208 /* Enable the timebase register for this core */ 209 out_be32(&rcpm->ctbenrl, (1 << whoami)); 210 } 211 #endif 212 213 void cpu_init_f (void) 214 { 215 extern void m8560_cpm_reset (void); 216 #ifdef CONFIG_SYS_DCSRBAR_PHYS 217 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 218 #endif 219 #if defined(CONFIG_SECURE_BOOT) 220 struct law_entry law; 221 #endif 222 #ifdef CONFIG_MPC8548 223 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 224 uint svr = get_svr(); 225 226 /* 227 * CPU2 errata workaround: A core hang possible while executing 228 * a msync instruction and a snoopable transaction from an I/O 229 * master tagged to make quick forward progress is present. 230 * Fixed in silicon rev 2.1. 231 */ 232 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 233 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 234 #endif 235 236 disable_tlb(14); 237 disable_tlb(15); 238 239 #if defined(CONFIG_SECURE_BOOT) 240 /* Disable the LAW created for NOR flash by the PBI commands */ 241 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 242 if (law.index != -1) 243 disable_law(law.index); 244 #endif 245 246 #ifdef CONFIG_CPM2 247 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 248 #endif 249 250 init_early_memctl_regs(); 251 252 #if defined(CONFIG_CPM2) 253 m8560_cpm_reset(); 254 #endif 255 #ifdef CONFIG_QE 256 /* Config QE ioports */ 257 config_qe_ioports(); 258 #endif 259 #if defined(CONFIG_FSL_DMA) 260 dma_init(); 261 #endif 262 #ifdef CONFIG_FSL_CORENET 263 corenet_tb_init(); 264 #endif 265 init_used_tlb_cams(); 266 267 /* Invalidate the CPC before DDR gets enabled */ 268 invalidate_cpc(); 269 270 #ifdef CONFIG_SYS_DCSRBAR_PHYS 271 /* set DCSRCR so that DCSR space is 1G */ 272 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 273 in_be32(&gur->dcsrcr); 274 #endif 275 276 } 277 278 /* Implement a dummy function for those platforms w/o SERDES */ 279 static void __fsl_serdes__init(void) 280 { 281 return ; 282 } 283 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 284 285 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 286 int enable_cluster_l2(void) 287 { 288 int i = 0; 289 u32 cluster; 290 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 291 struct ccsr_cluster_l2 __iomem *l2cache; 292 293 cluster = in_be32(&gur->tp_cluster[i].lower); 294 if (cluster & TP_CLUSTER_EOC) 295 return 0; 296 297 /* The first cache has already been set up, so skip it */ 298 i++; 299 300 /* Look through the remaining clusters, and set up their caches */ 301 do { 302 int j, cluster_valid = 0; 303 304 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 305 306 cluster = in_be32(&gur->tp_cluster[i].lower); 307 308 /* check that at least one core/accel is enabled in cluster */ 309 for (j = 0; j < 4; j++) { 310 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 311 u32 type = in_be32(&gur->tp_ityp[idx]); 312 313 if (type & TP_ITYP_AV) 314 cluster_valid = 1; 315 } 316 317 if (cluster_valid) { 318 /* set stash ID to (cluster) * 2 + 32 + 1 */ 319 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 320 321 printf("enable l2 for cluster %d %p\n", i, l2cache); 322 323 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 324 while ((in_be32(&l2cache->l2csr0) 325 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 326 ; 327 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 328 } 329 i++; 330 } while (!(cluster & TP_CLUSTER_EOC)); 331 332 return 0; 333 } 334 #endif 335 336 /* 337 * Initialize L2 as cache. 338 * 339 * The newer 8548, etc, parts have twice as much cache, but 340 * use the same bit-encoding as the older 8555, etc, parts. 341 * 342 */ 343 int cpu_init_r(void) 344 { 345 __maybe_unused u32 svr = get_svr(); 346 #ifdef CONFIG_SYS_LBC_LCRR 347 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 348 #endif 349 #ifdef CONFIG_L2_CACHE 350 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 351 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 352 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 353 #endif 354 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 355 extern int spin_table_compat; 356 const char *spin; 357 #endif 358 359 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 360 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 361 /* 362 * CPU22 and NMG_CPU_A011 share the same workaround. 363 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 364 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 365 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 366 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 367 * be disabled by hwconfig with syntax: 368 * 369 * fsl_cpu_a011:disable 370 */ 371 extern int enable_cpu_a011_workaround; 372 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 373 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 374 #else 375 char buffer[HWCONFIG_BUFFER_SIZE]; 376 char *buf = NULL; 377 int n, res; 378 379 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 380 if (n > 0) 381 buf = buffer; 382 383 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 384 if (res > 0) 385 enable_cpu_a011_workaround = 0; 386 else { 387 if (n >= HWCONFIG_BUFFER_SIZE) { 388 printf("fsl_cpu_a011 was not found. hwconfig variable " 389 "may be too long\n"); 390 } 391 enable_cpu_a011_workaround = 392 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 393 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 394 } 395 #endif 396 if (enable_cpu_a011_workaround) { 397 flush_dcache(); 398 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 399 sync(); 400 } 401 #endif 402 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 403 /* 404 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 405 * in write shadow mode. Checking DCWS before setting SPR 976. 406 */ 407 if (mfspr(L1CSR2) & L1CSR2_DCWS) 408 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 409 #endif 410 411 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 412 spin = getenv("spin_table_compat"); 413 if (spin && (*spin == 'n')) 414 spin_table_compat = 0; 415 else 416 spin_table_compat = 1; 417 #endif 418 419 puts ("L2: "); 420 421 #if defined(CONFIG_L2_CACHE) 422 volatile uint cache_ctl; 423 uint ver; 424 u32 l2siz_field; 425 426 ver = SVR_SOC_VER(svr); 427 428 asm("msync;isync"); 429 cache_ctl = l2cache->l2ctl; 430 431 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 432 if (cache_ctl & MPC85xx_L2CTL_L2E) { 433 /* Clear L2 SRAM memory-mapped base address */ 434 out_be32(&l2cache->l2srbar0, 0x0); 435 out_be32(&l2cache->l2srbar1, 0x0); 436 437 /* set MBECCDIS=0, SBECCDIS=0 */ 438 clrbits_be32(&l2cache->l2errdis, 439 (MPC85xx_L2ERRDIS_MBECC | 440 MPC85xx_L2ERRDIS_SBECC)); 441 442 /* set L2E=0, L2SRAM=0 */ 443 clrbits_be32(&l2cache->l2ctl, 444 (MPC85xx_L2CTL_L2E | 445 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 446 } 447 #endif 448 449 l2siz_field = (cache_ctl >> 28) & 0x3; 450 451 switch (l2siz_field) { 452 case 0x0: 453 printf(" unknown size (0x%08x)\n", cache_ctl); 454 return -1; 455 break; 456 case 0x1: 457 if (ver == SVR_8540 || ver == SVR_8560 || 458 ver == SVR_8541 || ver == SVR_8555) { 459 puts("128 KB "); 460 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ 461 cache_ctl = 0xc4000000; 462 } else { 463 puts("256 KB "); 464 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 465 } 466 break; 467 case 0x2: 468 if (ver == SVR_8540 || ver == SVR_8560 || 469 ver == SVR_8541 || ver == SVR_8555) { 470 puts("256 KB "); 471 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ 472 cache_ctl = 0xc8000000; 473 } else { 474 puts ("512 KB "); 475 /* set L2E=1, L2I=1, & L2SRAM=0 */ 476 cache_ctl = 0xc0000000; 477 } 478 break; 479 case 0x3: 480 puts("1024 KB "); 481 /* set L2E=1, L2I=1, & L2SRAM=0 */ 482 cache_ctl = 0xc0000000; 483 break; 484 } 485 486 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 487 puts("already enabled"); 488 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 489 u32 l2srbar = l2cache->l2srbar0; 490 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 491 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 492 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 493 l2cache->l2srbar0 = l2srbar; 494 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 495 } 496 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 497 puts("\n"); 498 } else { 499 asm("msync;isync"); 500 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 501 asm("msync;isync"); 502 puts("enabled\n"); 503 } 504 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 505 if (SVR_SOC_VER(svr) == SVR_P2040) { 506 puts("N/A\n"); 507 goto skip_l2; 508 } 509 510 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 511 512 /* invalidate the L2 cache */ 513 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 514 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 515 ; 516 517 #ifdef CONFIG_SYS_CACHE_STASHING 518 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 519 mtspr(SPRN_L2CSR1, (32 + 1)); 520 #endif 521 522 /* enable the cache */ 523 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 524 525 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 526 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 527 ; 528 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); 529 } 530 531 skip_l2: 532 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 533 if (l2cache->l2csr0 & L2CSR0_L2E) 534 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); 535 536 enable_cluster_l2(); 537 #else 538 puts("disabled\n"); 539 #endif 540 541 enable_cpc(); 542 543 #ifndef CONFIG_SYS_FSL_NO_SERDES 544 /* needs to be in ram since code uses global static vars */ 545 fsl_serdes_init(); 546 #endif 547 548 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 549 if (IS_SVR_REV(svr, 1, 0)) { 550 int i; 551 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 552 553 for (i = 0; i < 12; i++) { 554 p += i + (i > 5 ? 11 : 0); 555 out_be32(p, 0x2); 556 } 557 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 558 out_be32(p, 0x34); 559 } 560 #endif 561 562 #ifdef CONFIG_SYS_SRIO 563 srio_init(); 564 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 565 char *s = getenv("bootmaster"); 566 if (s) { 567 if (!strcmp(s, "SRIO1")) { 568 srio_boot_master(1); 569 srio_boot_master_release_slave(1); 570 } 571 if (!strcmp(s, "SRIO2")) { 572 srio_boot_master(2); 573 srio_boot_master_release_slave(2); 574 } 575 } 576 #endif 577 #endif 578 579 #if defined(CONFIG_MP) 580 setup_mp(); 581 #endif 582 583 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 584 { 585 if (SVR_MAJ(svr) < 3) { 586 void *p; 587 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 588 setbits_be32(p, 1 << (31 - 14)); 589 } 590 } 591 #endif 592 593 #ifdef CONFIG_SYS_LBC_LCRR 594 /* 595 * Modify the CLKDIV field of LCRR register to improve the writing 596 * speed for NOR flash. 597 */ 598 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 599 __raw_readl(&lbc->lcrr); 600 isync(); 601 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 602 udelay(100); 603 #endif 604 #endif 605 606 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 607 { 608 ccsr_usb_phy_t *usb_phy1 = 609 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 610 out_be32(&usb_phy1->usb_enable_override, 611 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 612 } 613 #endif 614 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 615 { 616 ccsr_usb_phy_t *usb_phy2 = 617 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 618 out_be32(&usb_phy2->usb_enable_override, 619 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 620 } 621 #endif 622 623 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 624 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 625 * multi-bit ECC errors which has impact on performance, so software 626 * should disable all ECC reporting from USB1 and USB2. 627 */ 628 if (IS_SVR_REV(get_svr(), 1, 0)) { 629 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 630 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 631 setbits_be32(&dcfg->ecccr1, 632 (DCSR_DCFG_ECC_DISABLE_USB1 | 633 DCSR_DCFG_ECC_DISABLE_USB2)); 634 } 635 #endif 636 637 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 638 ccsr_usb_phy_t *usb_phy = 639 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 640 setbits_be32(&usb_phy->pllprg[1], 641 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 642 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 643 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 644 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 645 setbits_be32(&usb_phy->port1.ctrl, 646 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 647 setbits_be32(&usb_phy->port1.drvvbuscfg, 648 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 649 setbits_be32(&usb_phy->port1.pwrfltcfg, 650 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 651 setbits_be32(&usb_phy->port2.ctrl, 652 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 653 setbits_be32(&usb_phy->port2.drvvbuscfg, 654 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 655 setbits_be32(&usb_phy->port2.pwrfltcfg, 656 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 657 #endif 658 659 #ifdef CONFIG_FMAN_ENET 660 fman_enet_init(); 661 #endif 662 663 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 664 /* 665 * For P1022/1013 Rev1.0 silicon, after power on SATA host 666 * controller is configured in legacy mode instead of the 667 * expected enterprise mode. Software needs to clear bit[28] 668 * of HControl register to change to enterprise mode from 669 * legacy mode. We assume that the controller is offline. 670 */ 671 if (IS_SVR_REV(svr, 1, 0) && 672 ((SVR_SOC_VER(svr) == SVR_P1022) || 673 (SVR_SOC_VER(svr) == SVR_P1013))) { 674 fsl_sata_reg_t *reg; 675 676 /* first SATA controller */ 677 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 678 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 679 680 /* second SATA controller */ 681 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 682 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 683 } 684 #endif 685 686 687 return 0; 688 } 689 690 extern void setup_ivors(void); 691 692 void arch_preboot_os(void) 693 { 694 u32 msr; 695 696 /* 697 * We are changing interrupt offsets and are about to boot the OS so 698 * we need to make sure we disable all async interrupts. EE is already 699 * disabled by the time we get called. 700 */ 701 msr = mfmsr(); 702 msr &= ~(MSR_ME|MSR_CE); 703 mtmsr(msr); 704 705 setup_ivors(); 706 } 707 708 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 709 int sata_initialize(void) 710 { 711 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 712 return __sata_initialize(); 713 714 return 1; 715 } 716 #endif 717 718 void cpu_secondary_init_r(void) 719 { 720 #ifdef CONFIG_QE 721 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 722 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 723 int ret; 724 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 725 726 /* load QE firmware from NAND flash to DDR first */ 727 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 728 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 729 730 if (ret && ret == -EUCLEAN) { 731 printf ("NAND read for QE firmware at offset %x failed %d\n", 732 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 733 } 734 #endif 735 qe_init(qe_base); 736 qe_reset(); 737 #endif 738 } 739