xref: /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/cpu.c (revision ffe16911)
1 /*
2  * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3  * (C) Copyright 2002, 2003 Motorola Inc.
4  * Xianghua Xiao (X.Xiao@motorola.com)
5  *
6  * (C) Copyright 2000
7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <config.h>
13 #include <common.h>
14 #include <watchdog.h>
15 #include <command.h>
16 #include <fsl_esdhc.h>
17 #include <asm/cache.h>
18 #include <asm/io.h>
19 #include <asm/mmu.h>
20 #include <fsl_ifc.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_lbc.h>
23 #include <post.h>
24 #include <asm/processor.h>
25 #include <fsl_ddr_sdram.h>
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 /*
30  * Default board reset function
31  */
32 static void
33 __board_reset(void)
34 {
35 	/* Do nothing */
36 }
37 void board_reset(void) __attribute__((weak, alias("__board_reset")));
38 
39 int checkcpu (void)
40 {
41 	sys_info_t sysinfo;
42 	uint pvr, svr;
43 	uint ver;
44 	uint major, minor;
45 	struct cpu_type *cpu;
46 	char buf1[32], buf2[32];
47 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
48 	ccsr_gur_t __iomem *gur =
49 		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 #endif
51 
52 	/*
53 	 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
54 	 * mode. Previous platform use ddr ratio to do the same. This
55 	 * information is only for display here.
56 	 */
57 #ifdef CONFIG_FSL_CORENET
58 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
59 	u32 ddr_sync = 0;	/* only async mode is supported */
60 #else
61 	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
62 		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
63 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
64 #else	/* CONFIG_FSL_CORENET */
65 #ifdef CONFIG_DDR_CLK_FREQ
66 	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
67 		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
68 #else
69 	u32 ddr_ratio = 0;
70 #endif /* CONFIG_DDR_CLK_FREQ */
71 #endif /* CONFIG_FSL_CORENET */
72 
73 	unsigned int i, core, nr_cores = cpu_numcores();
74 	u32 mask = cpu_mask();
75 
76 	svr = get_svr();
77 	major = SVR_MAJ(svr);
78 	minor = SVR_MIN(svr);
79 
80 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
81 	if (SVR_SOC_VER(svr) == SVR_T4080) {
82 		ccsr_rcpm_t *rcpm =
83 			(void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
84 
85 		setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
86 			     FSL_CORENET_DEVDISR2_DTSEC1_9);
87 		setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
88 		setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
89 
90 		/* It needs SW to disable core4~7 as HW design sake on T4080 */
91 		for (i = 4; i < 8; i++)
92 			cpu_disable(i);
93 
94 		/* request core4~7 into PH20 state, prior to entering PCL10
95 		 * state, all cores in cluster should be placed in PH20 state.
96 		 */
97 		setbits_be32(&rcpm->pcph20setr, 0xf0);
98 
99 		/* put the 2nd cluster into PCL10 state */
100 		setbits_be32(&rcpm->clpcl10setr, 1 << 1);
101 	}
102 #endif
103 
104 	if (cpu_numcores() > 1) {
105 #ifndef CONFIG_MP
106 		puts("Unicore software on multiprocessor system!!\n"
107 		     "To enable mutlticore build define CONFIG_MP\n");
108 #endif
109 		volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
110 		printf("CPU%d:  ", pic->whoami);
111 	} else {
112 		puts("CPU:   ");
113 	}
114 
115 	cpu = gd->arch.cpu;
116 
117 	puts(cpu->name);
118 	if (IS_E_PROCESSOR(svr))
119 		puts("E");
120 
121 	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
122 
123 	pvr = get_pvr();
124 	ver = PVR_VER(pvr);
125 	major = PVR_MAJ(pvr);
126 	minor = PVR_MIN(pvr);
127 
128 	printf("Core:  ");
129 	switch(ver) {
130 	case PVR_VER_E500_V1:
131 	case PVR_VER_E500_V2:
132 		puts("e500");
133 		break;
134 	case PVR_VER_E500MC:
135 		puts("e500mc");
136 		break;
137 	case PVR_VER_E5500:
138 		puts("e5500");
139 		break;
140 	case PVR_VER_E6500:
141 		puts("e6500");
142 		break;
143 	default:
144 		puts("Unknown");
145 		break;
146 	}
147 
148 	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
149 
150 	if (nr_cores > CONFIG_MAX_CPUS) {
151 		panic("\nUnexpected number of cores: %d, max is %d\n",
152 			nr_cores, CONFIG_MAX_CPUS);
153 	}
154 
155 	get_sys_info(&sysinfo);
156 
157 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
158 	if (sysinfo.diff_sysclk == 1)
159 		puts("Single Source Clock Configuration\n");
160 #endif
161 
162 	puts("Clock Configuration:");
163 	for_each_cpu(i, core, nr_cores, mask) {
164 		if (!(i & 3))
165 			printf ("\n       ");
166 		printf("CPU%d:%-4s MHz, ", core,
167 			strmhz(buf1, sysinfo.freq_processor[core]));
168 	}
169 	printf("\n       CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
170 	printf("\n");
171 
172 #ifdef CONFIG_FSL_CORENET
173 	if (ddr_sync == 1) {
174 		printf("       DDR:%-4s MHz (%s MT/s data rate) "
175 			"(Synchronous), ",
176 			strmhz(buf1, sysinfo.freq_ddrbus/2),
177 			strmhz(buf2, sysinfo.freq_ddrbus));
178 	} else {
179 		printf("       DDR:%-4s MHz (%s MT/s data rate) "
180 			"(Asynchronous), ",
181 			strmhz(buf1, sysinfo.freq_ddrbus/2),
182 			strmhz(buf2, sysinfo.freq_ddrbus));
183 	}
184 #else
185 	switch (ddr_ratio) {
186 	case 0x0:
187 		printf("       DDR:%-4s MHz (%s MT/s data rate), ",
188 			strmhz(buf1, sysinfo.freq_ddrbus/2),
189 			strmhz(buf2, sysinfo.freq_ddrbus));
190 		break;
191 	case 0x7:
192 		printf("       DDR:%-4s MHz (%s MT/s data rate) "
193 			"(Synchronous), ",
194 			strmhz(buf1, sysinfo.freq_ddrbus/2),
195 			strmhz(buf2, sysinfo.freq_ddrbus));
196 		break;
197 	default:
198 		printf("       DDR:%-4s MHz (%s MT/s data rate) "
199 			"(Asynchronous), ",
200 			strmhz(buf1, sysinfo.freq_ddrbus/2),
201 			strmhz(buf2, sysinfo.freq_ddrbus));
202 		break;
203 	}
204 #endif
205 
206 #if defined(CONFIG_FSL_LBC)
207 	if (sysinfo.freq_localbus > LCRR_CLKDIV) {
208 		printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
209 	} else {
210 		printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
211 		       sysinfo.freq_localbus);
212 	}
213 #endif
214 
215 #if defined(CONFIG_FSL_IFC)
216 	printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
217 #endif
218 
219 #ifdef CONFIG_CPM2
220 	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
221 #endif
222 
223 #ifdef CONFIG_QE
224 	printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
225 #endif
226 
227 #ifdef CONFIG_SYS_DPAA_FMAN
228 	for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
229 		printf("       FMAN%d: %s MHz\n", i + 1,
230 			strmhz(buf1, sysinfo.freq_fman[i]));
231 	}
232 #endif
233 
234 #ifdef CONFIG_SYS_DPAA_QBMAN
235 	printf("       QMAN:  %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
236 #endif
237 
238 #ifdef CONFIG_SYS_DPAA_PME
239 	printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
240 #endif
241 
242 	puts("L1:    D-cache 32 KiB enabled\n       I-cache 32 KiB enabled\n");
243 
244 #ifdef CONFIG_FSL_CORENET
245 	/* Display the RCW, so that no one gets confused as to what RCW
246 	 * we're actually using for this boot.
247 	 */
248 	puts("Reset Configuration Word (RCW):");
249 	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
250 		u32 rcw = in_be32(&gur->rcwsr[i]);
251 
252 		if ((i % 4) == 0)
253 			printf("\n       %08x:", i * 4);
254 		printf(" %08x", rcw);
255 	}
256 	puts("\n");
257 #endif
258 
259 	return 0;
260 }
261 
262 
263 /* ------------------------------------------------------------------------- */
264 
265 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
266 {
267 /* Everything after the first generation of PQ3 parts has RSTCR */
268 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
269     defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
270 	unsigned long val, msr;
271 
272 	/*
273 	 * Initiate hard reset in debug control register DBCR0
274 	 * Make sure MSR[DE] = 1.  This only resets the core.
275 	 */
276 	msr = mfmsr ();
277 	msr |= MSR_DE;
278 	mtmsr (msr);
279 
280 	val = mfspr(DBCR0);
281 	val |= 0x70000000;
282 	mtspr(DBCR0,val);
283 #else
284 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
285 
286 	/* Attempt board-specific reset */
287 	board_reset();
288 
289 	/* Next try asserting HRESET_REQ */
290 	out_be32(&gur->rstcr, 0x2);
291 	udelay(100);
292 #endif
293 
294 	return 1;
295 }
296 
297 
298 /*
299  * Get timebase clock frequency
300  */
301 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
302 #define CONFIG_SYS_FSL_TBCLK_DIV 8
303 #endif
304 __weak unsigned long get_tbclk (void)
305 {
306 	unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
307 
308 	return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
309 }
310 
311 
312 #if defined(CONFIG_WATCHDOG)
313 void
314 reset_85xx_watchdog(void)
315 {
316 	/*
317 	 * Clear TSR(WIS) bit by writing 1
318 	 */
319 	mtspr(SPRN_TSR, TSR_WIS);
320 }
321 
322 void
323 watchdog_reset(void)
324 {
325 	int re_enable = disable_interrupts();
326 
327 	reset_85xx_watchdog();
328 	if (re_enable)
329 		enable_interrupts();
330 }
331 #endif	/* CONFIG_WATCHDOG */
332 
333 /*
334  * Initializes on-chip MMC controllers.
335  * to override, implement board_mmc_init()
336  */
337 int cpu_mmc_init(bd_t *bis)
338 {
339 #ifdef CONFIG_FSL_ESDHC
340 	return fsl_esdhc_mmc_init(bis);
341 #else
342 	return 0;
343 #endif
344 }
345 
346 /*
347  * Print out the state of various machine registers.
348  * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
349  * parameters for IFC and TLBs
350  */
351 void mpc85xx_reginfo(void)
352 {
353 	print_tlbcam();
354 	print_laws();
355 #if defined(CONFIG_FSL_LBC)
356 	print_lbc_regs();
357 #endif
358 #ifdef CONFIG_FSL_IFC
359 	print_ifc_regs();
360 #endif
361 
362 }
363 
364 /* Common ddr init for non-corenet fsl 85xx platforms */
365 #ifndef CONFIG_FSL_CORENET
366 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
367 	!defined(CONFIG_SYS_INIT_L2_ADDR)
368 phys_size_t initdram(int board_type)
369 {
370 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
371 	defined(CONFIG_QEMU_E500)
372 	return fsl_ddr_sdram_size();
373 #else
374 	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
375 #endif
376 }
377 #else /* CONFIG_SYS_RAMBOOT */
378 phys_size_t initdram(int board_type)
379 {
380 	phys_size_t dram_size = 0;
381 
382 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
383 	{
384 		ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
385 		unsigned int x = 10;
386 		unsigned int i;
387 
388 		/*
389 		 * Work around to stabilize DDR DLL
390 		 */
391 		out_be32(&gur->ddrdllcr, 0x81000000);
392 		asm("sync;isync;msync");
393 		udelay(200);
394 		while (in_be32(&gur->ddrdllcr) != 0x81000100) {
395 			setbits_be32(&gur->devdisr, 0x00010000);
396 			for (i = 0; i < x; i++)
397 				;
398 			clrbits_be32(&gur->devdisr, 0x00010000);
399 			x++;
400 		}
401 	}
402 #endif
403 
404 #if	defined(CONFIG_SPD_EEPROM)	|| \
405 	defined(CONFIG_DDR_SPD)		|| \
406 	defined(CONFIG_SYS_DDR_RAW_TIMING)
407 	dram_size = fsl_ddr_sdram();
408 #else
409 	dram_size = fixed_sdram();
410 #endif
411 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
412 	dram_size *= 0x100000;
413 
414 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
415 	/*
416 	 * Initialize and enable DDR ECC.
417 	 */
418 	ddr_enable_ecc(dram_size);
419 #endif
420 
421 #if defined(CONFIG_FSL_LBC)
422 	/* Some boards also have sdram on the lbc */
423 	lbc_sdram_init();
424 #endif
425 
426 	debug("DDR: ");
427 	return dram_size;
428 }
429 #endif /* CONFIG_SYS_RAMBOOT */
430 #endif
431 
432 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
433 
434 /* Board-specific functions defined in each board's ddr.c */
435 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
436 	unsigned int ctrl_num);
437 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
438 		       phys_addr_t *rpn);
439 unsigned int
440 	setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
441 
442 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
443 
444 static void dump_spd_ddr_reg(void)
445 {
446 	int i, j, k, m;
447 	u8 *p_8;
448 	u32 *p_32;
449 	struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
450 	generic_spd_eeprom_t
451 		spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
452 
453 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
454 		fsl_ddr_get_spd(spd[i], i);
455 
456 	puts("SPD data of all dimms (zero vaule is omitted)...\n");
457 	puts("Byte (hex)  ");
458 	k = 1;
459 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
460 		for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
461 			printf("Dimm%d ", k++);
462 	}
463 	puts("\n");
464 	for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
465 		m = 0;
466 		printf("%3d (0x%02x)  ", k, k);
467 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
468 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
469 				p_8 = (u8 *) &spd[i][j];
470 				if (p_8[k]) {
471 					printf("0x%02x  ", p_8[k]);
472 					m++;
473 				} else
474 					puts("      ");
475 			}
476 		}
477 		if (m)
478 			puts("\n");
479 		else
480 			puts("\r");
481 	}
482 
483 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
484 		switch (i) {
485 		case 0:
486 			ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
487 			break;
488 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
489 		case 1:
490 			ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
491 			break;
492 #endif
493 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
494 		case 2:
495 			ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
496 			break;
497 #endif
498 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
499 		case 3:
500 			ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
501 			break;
502 #endif
503 		default:
504 			printf("%s unexpected controller number = %u\n",
505 				__func__, i);
506 			return;
507 		}
508 	}
509 	printf("DDR registers dump for all controllers "
510 		"(zero vaule is omitted)...\n");
511 	puts("Offset (hex)   ");
512 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
513 		printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
514 	puts("\n");
515 	for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
516 		m = 0;
517 		printf("%6d (0x%04x)", k * 4, k * 4);
518 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
519 			p_32 = (u32 *) ddr[i];
520 			if (p_32[k]) {
521 				printf("        0x%08x", p_32[k]);
522 				m++;
523 			} else
524 				puts("                  ");
525 		}
526 		if (m)
527 			puts("\n");
528 		else
529 			puts("\r");
530 	}
531 	puts("\n");
532 }
533 
534 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
535 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
536 {
537 	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
538 	unsigned long epn;
539 	u32 tsize, valid, ptr;
540 	int ddr_esel;
541 
542 	clear_ddr_tlbs_phys(p_addr, size>>20);
543 
544 	/* Setup new tlb to cover the physical address */
545 	setup_ddr_tlbs_phys(p_addr, size>>20);
546 
547 	ptr = vstart;
548 	ddr_esel = find_tlb_idx((void *)ptr, 1);
549 	if (ddr_esel != -1) {
550 		read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
551 	} else {
552 		printf("TLB error in function %s\n", __func__);
553 		return -1;
554 	}
555 
556 	return 0;
557 }
558 
559 /*
560  * slide the testing window up to test another area
561  * for 32_bit system, the maximum testable memory is limited to
562  * CONFIG_MAX_MEM_MAPPED
563  */
564 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
565 {
566 	phys_addr_t test_cap, p_addr;
567 	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
568 
569 #if !defined(CONFIG_PHYS_64BIT) || \
570     !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
571 	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
572 		test_cap = p_size;
573 #else
574 		test_cap = gd->ram_size;
575 #endif
576 	p_addr = (*vstart) + (*size) + (*phys_offset);
577 	if (p_addr < test_cap - 1) {
578 		p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
579 		if (reset_tlb(p_addr, p_size, phys_offset) == -1)
580 			return -1;
581 		*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
582 		*size = (u32) p_size;
583 		printf("Testing 0x%08llx - 0x%08llx\n",
584 			(u64)(*vstart) + (*phys_offset),
585 			(u64)(*vstart) + (*phys_offset) + (*size) - 1);
586 	} else
587 		return 1;
588 
589 	return 0;
590 }
591 
592 /* initialization for testing area */
593 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
594 {
595 	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
596 
597 	*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
598 	*size = (u32) p_size;	/* CONFIG_MAX_MEM_MAPPED < 4G */
599 	*phys_offset = 0;
600 
601 #if !defined(CONFIG_PHYS_64BIT) || \
602     !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
603 	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
604 		if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
605 			puts("Cannot test more than ");
606 			print_size(CONFIG_MAX_MEM_MAPPED,
607 				" without proper 36BIT support.\n");
608 		}
609 #endif
610 	printf("Testing 0x%08llx - 0x%08llx\n",
611 		(u64)(*vstart) + (*phys_offset),
612 		(u64)(*vstart) + (*phys_offset) + (*size) - 1);
613 
614 	return 0;
615 }
616 
617 /* invalid TLBs for DDR and remap as normal after testing */
618 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
619 {
620 	unsigned long epn;
621 	u32 tsize, valid, ptr;
622 	phys_addr_t rpn = 0;
623 	int ddr_esel;
624 
625 	/* disable the TLBs for this testing */
626 	ptr = *vstart;
627 
628 	while (ptr < (*vstart) + (*size)) {
629 		ddr_esel = find_tlb_idx((void *)ptr, 1);
630 		if (ddr_esel != -1) {
631 			read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
632 			disable_tlb(ddr_esel);
633 		}
634 		ptr += TSIZE_TO_BYTES(tsize);
635 	}
636 
637 	puts("Remap DDR ");
638 	setup_ddr_tlbs(gd->ram_size>>20);
639 	puts("\n");
640 
641 	return 0;
642 }
643 
644 void arch_memory_failure_handle(void)
645 {
646 	dump_spd_ddr_reg();
647 }
648 #endif
649