1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <watchdog.h> 15 #include <command.h> 16 #include <fsl_esdhc.h> 17 #include <asm/cache.h> 18 #include <asm/io.h> 19 #include <asm/mmu.h> 20 #include <asm/fsl_ifc.h> 21 #include <asm/fsl_law.h> 22 #include <asm/fsl_lbc.h> 23 #include <post.h> 24 #include <asm/processor.h> 25 #include <asm/fsl_ddr_sdram.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* 30 * Default board reset function 31 */ 32 static void 33 __board_reset(void) 34 { 35 /* Do nothing */ 36 } 37 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 38 39 int checkcpu (void) 40 { 41 sys_info_t sysinfo; 42 uint pvr, svr; 43 uint ver; 44 uint major, minor; 45 struct cpu_type *cpu; 46 char buf1[32], buf2[32]; 47 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 48 ccsr_gur_t __iomem *gur = 49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 #endif 51 52 /* 53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async 54 * mode. Previous platform use ddr ratio to do the same. This 55 * information is only for display here. 56 */ 57 #ifdef CONFIG_FSL_CORENET 58 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 59 u32 ddr_sync = 0; /* only async mode is supported */ 60 #else 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 64 #else /* CONFIG_FSL_CORENET */ 65 #ifdef CONFIG_DDR_CLK_FREQ 66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 68 #else 69 u32 ddr_ratio = 0; 70 #endif /* CONFIG_DDR_CLK_FREQ */ 71 #endif /* CONFIG_FSL_CORENET */ 72 73 unsigned int i, core, nr_cores = cpu_numcores(); 74 u32 mask = cpu_mask(); 75 76 svr = get_svr(); 77 major = SVR_MAJ(svr); 78 minor = SVR_MIN(svr); 79 80 if (cpu_numcores() > 1) { 81 #ifndef CONFIG_MP 82 puts("Unicore software on multiprocessor system!!\n" 83 "To enable mutlticore build define CONFIG_MP\n"); 84 #endif 85 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 86 printf("CPU%d: ", pic->whoami); 87 } else { 88 puts("CPU: "); 89 } 90 91 cpu = gd->arch.cpu; 92 93 puts(cpu->name); 94 if (IS_E_PROCESSOR(svr)) 95 puts("E"); 96 97 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 98 99 pvr = get_pvr(); 100 ver = PVR_VER(pvr); 101 major = PVR_MAJ(pvr); 102 minor = PVR_MIN(pvr); 103 104 printf("Core: "); 105 switch(ver) { 106 case PVR_VER_E500_V1: 107 case PVR_VER_E500_V2: 108 puts("e500"); 109 break; 110 case PVR_VER_E500MC: 111 puts("e500mc"); 112 break; 113 case PVR_VER_E5500: 114 puts("e5500"); 115 break; 116 case PVR_VER_E6500: 117 puts("e6500"); 118 break; 119 default: 120 puts("Unknown"); 121 break; 122 } 123 124 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 125 126 if (nr_cores > CONFIG_MAX_CPUS) { 127 panic("\nUnexpected number of cores: %d, max is %d\n", 128 nr_cores, CONFIG_MAX_CPUS); 129 } 130 131 get_sys_info(&sysinfo); 132 133 puts("Clock Configuration:"); 134 for_each_cpu(i, core, nr_cores, mask) { 135 if (!(i & 3)) 136 printf ("\n "); 137 printf("CPU%d:%-4s MHz, ", core, 138 strmhz(buf1, sysinfo.freqProcessor[core])); 139 } 140 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 141 142 #ifdef CONFIG_FSL_CORENET 143 if (ddr_sync == 1) { 144 printf(" DDR:%-4s MHz (%s MT/s data rate) " 145 "(Synchronous), ", 146 strmhz(buf1, sysinfo.freqDDRBus/2), 147 strmhz(buf2, sysinfo.freqDDRBus)); 148 } else { 149 printf(" DDR:%-4s MHz (%s MT/s data rate) " 150 "(Asynchronous), ", 151 strmhz(buf1, sysinfo.freqDDRBus/2), 152 strmhz(buf2, sysinfo.freqDDRBus)); 153 } 154 #else 155 switch (ddr_ratio) { 156 case 0x0: 157 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 158 strmhz(buf1, sysinfo.freqDDRBus/2), 159 strmhz(buf2, sysinfo.freqDDRBus)); 160 break; 161 case 0x7: 162 printf(" DDR:%-4s MHz (%s MT/s data rate) " 163 "(Synchronous), ", 164 strmhz(buf1, sysinfo.freqDDRBus/2), 165 strmhz(buf2, sysinfo.freqDDRBus)); 166 break; 167 default: 168 printf(" DDR:%-4s MHz (%s MT/s data rate) " 169 "(Asynchronous), ", 170 strmhz(buf1, sysinfo.freqDDRBus/2), 171 strmhz(buf2, sysinfo.freqDDRBus)); 172 break; 173 } 174 #endif 175 176 #if defined(CONFIG_FSL_LBC) 177 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 178 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 179 } else { 180 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 181 sysinfo.freqLocalBus); 182 } 183 #endif 184 185 #if defined(CONFIG_FSL_IFC) 186 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 187 #endif 188 189 #ifdef CONFIG_CPM2 190 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 191 #endif 192 193 #ifdef CONFIG_QE 194 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 195 #endif 196 197 #ifdef CONFIG_SYS_DPAA_FMAN 198 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 199 printf(" FMAN%d: %s MHz\n", i + 1, 200 strmhz(buf1, sysinfo.freqFMan[i])); 201 } 202 #endif 203 204 #ifdef CONFIG_SYS_DPAA_QBMAN 205 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); 206 #endif 207 208 #ifdef CONFIG_SYS_DPAA_PME 209 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 210 #endif 211 212 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 213 214 #ifdef CONFIG_FSL_CORENET 215 /* Display the RCW, so that no one gets confused as to what RCW 216 * we're actually using for this boot. 217 */ 218 puts("Reset Configuration Word (RCW):"); 219 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 220 u32 rcw = in_be32(&gur->rcwsr[i]); 221 222 if ((i % 4) == 0) 223 printf("\n %08x:", i * 4); 224 printf(" %08x", rcw); 225 } 226 puts("\n"); 227 #endif 228 229 return 0; 230 } 231 232 233 /* ------------------------------------------------------------------------- */ 234 235 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 236 { 237 /* Everything after the first generation of PQ3 parts has RSTCR */ 238 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 239 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 240 unsigned long val, msr; 241 242 /* 243 * Initiate hard reset in debug control register DBCR0 244 * Make sure MSR[DE] = 1. This only resets the core. 245 */ 246 msr = mfmsr (); 247 msr |= MSR_DE; 248 mtmsr (msr); 249 250 val = mfspr(DBCR0); 251 val |= 0x70000000; 252 mtspr(DBCR0,val); 253 #else 254 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 255 256 /* Attempt board-specific reset */ 257 board_reset(); 258 259 /* Next try asserting HRESET_REQ */ 260 out_be32(&gur->rstcr, 0x2); 261 udelay(100); 262 #endif 263 264 return 1; 265 } 266 267 268 /* 269 * Get timebase clock frequency 270 */ 271 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 272 #define CONFIG_SYS_FSL_TBCLK_DIV 8 273 #endif 274 unsigned long get_tbclk (void) 275 { 276 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 277 278 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 279 } 280 281 282 #if defined(CONFIG_WATCHDOG) 283 void 284 reset_85xx_watchdog(void) 285 { 286 /* 287 * Clear TSR(WIS) bit by writing 1 288 */ 289 mtspr(SPRN_TSR, TSR_WIS); 290 } 291 292 void 293 watchdog_reset(void) 294 { 295 int re_enable = disable_interrupts(); 296 297 reset_85xx_watchdog(); 298 if (re_enable) 299 enable_interrupts(); 300 } 301 #endif /* CONFIG_WATCHDOG */ 302 303 /* 304 * Initializes on-chip MMC controllers. 305 * to override, implement board_mmc_init() 306 */ 307 int cpu_mmc_init(bd_t *bis) 308 { 309 #ifdef CONFIG_FSL_ESDHC 310 return fsl_esdhc_mmc_init(bis); 311 #else 312 return 0; 313 #endif 314 } 315 316 /* 317 * Print out the state of various machine registers. 318 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 319 * parameters for IFC and TLBs 320 */ 321 void mpc85xx_reginfo(void) 322 { 323 print_tlbcam(); 324 print_laws(); 325 #if defined(CONFIG_FSL_LBC) 326 print_lbc_regs(); 327 #endif 328 #ifdef CONFIG_FSL_IFC 329 print_ifc_regs(); 330 #endif 331 332 } 333 334 /* Common ddr init for non-corenet fsl 85xx platforms */ 335 #ifndef CONFIG_FSL_CORENET 336 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ 337 !defined(CONFIG_SYS_INIT_L2_ADDR) 338 phys_size_t initdram(int board_type) 339 { 340 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 341 return fsl_ddr_sdram_size(); 342 #else 343 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 344 #endif 345 } 346 #else /* CONFIG_SYS_RAMBOOT */ 347 phys_size_t initdram(int board_type) 348 { 349 phys_size_t dram_size = 0; 350 351 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 352 { 353 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 354 unsigned int x = 10; 355 unsigned int i; 356 357 /* 358 * Work around to stabilize DDR DLL 359 */ 360 out_be32(&gur->ddrdllcr, 0x81000000); 361 asm("sync;isync;msync"); 362 udelay(200); 363 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 364 setbits_be32(&gur->devdisr, 0x00010000); 365 for (i = 0; i < x; i++) 366 ; 367 clrbits_be32(&gur->devdisr, 0x00010000); 368 x++; 369 } 370 } 371 #endif 372 373 #if defined(CONFIG_SPD_EEPROM) || \ 374 defined(CONFIG_DDR_SPD) || \ 375 defined(CONFIG_SYS_DDR_RAW_TIMING) 376 dram_size = fsl_ddr_sdram(); 377 #else 378 dram_size = fixed_sdram(); 379 #endif 380 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 381 dram_size *= 0x100000; 382 383 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 384 /* 385 * Initialize and enable DDR ECC. 386 */ 387 ddr_enable_ecc(dram_size); 388 #endif 389 390 #if defined(CONFIG_FSL_LBC) 391 /* Some boards also have sdram on the lbc */ 392 lbc_sdram_init(); 393 #endif 394 395 debug("DDR: "); 396 return dram_size; 397 } 398 #endif /* CONFIG_SYS_RAMBOOT */ 399 #endif 400 401 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 402 403 /* Board-specific functions defined in each board's ddr.c */ 404 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 405 unsigned int ctrl_num); 406 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 407 phys_addr_t *rpn); 408 unsigned int 409 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 410 411 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 412 413 static void dump_spd_ddr_reg(void) 414 { 415 int i, j, k, m; 416 u8 *p_8; 417 u32 *p_32; 418 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 419 generic_spd_eeprom_t 420 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 421 422 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 423 fsl_ddr_get_spd(spd[i], i); 424 425 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 426 puts("Byte (hex) "); 427 k = 1; 428 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 429 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 430 printf("Dimm%d ", k++); 431 } 432 puts("\n"); 433 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 434 m = 0; 435 printf("%3d (0x%02x) ", k, k); 436 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 437 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 438 p_8 = (u8 *) &spd[i][j]; 439 if (p_8[k]) { 440 printf("0x%02x ", p_8[k]); 441 m++; 442 } else 443 puts(" "); 444 } 445 } 446 if (m) 447 puts("\n"); 448 else 449 puts("\r"); 450 } 451 452 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 453 switch (i) { 454 case 0: 455 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; 456 break; 457 #if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 458 case 1: 459 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; 460 break; 461 #endif 462 #if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 463 case 2: 464 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; 465 break; 466 #endif 467 #if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 468 case 3: 469 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; 470 break; 471 #endif 472 default: 473 printf("%s unexpected controller number = %u\n", 474 __func__, i); 475 return; 476 } 477 } 478 printf("DDR registers dump for all controllers " 479 "(zero vaule is omitted)...\n"); 480 puts("Offset (hex) "); 481 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 482 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 483 puts("\n"); 484 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 485 m = 0; 486 printf("%6d (0x%04x)", k * 4, k * 4); 487 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 488 p_32 = (u32 *) ddr[i]; 489 if (p_32[k]) { 490 printf(" 0x%08x", p_32[k]); 491 m++; 492 } else 493 puts(" "); 494 } 495 if (m) 496 puts("\n"); 497 else 498 puts("\r"); 499 } 500 puts("\n"); 501 } 502 503 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 504 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 505 { 506 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 507 unsigned long epn; 508 u32 tsize, valid, ptr; 509 int ddr_esel; 510 511 clear_ddr_tlbs_phys(p_addr, size>>20); 512 513 /* Setup new tlb to cover the physical address */ 514 setup_ddr_tlbs_phys(p_addr, size>>20); 515 516 ptr = vstart; 517 ddr_esel = find_tlb_idx((void *)ptr, 1); 518 if (ddr_esel != -1) { 519 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 520 } else { 521 printf("TLB error in function %s\n", __func__); 522 return -1; 523 } 524 525 return 0; 526 } 527 528 /* 529 * slide the testing window up to test another area 530 * for 32_bit system, the maximum testable memory is limited to 531 * CONFIG_MAX_MEM_MAPPED 532 */ 533 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 534 { 535 phys_addr_t test_cap, p_addr; 536 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 537 538 #if !defined(CONFIG_PHYS_64BIT) || \ 539 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 540 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 541 test_cap = p_size; 542 #else 543 test_cap = gd->ram_size; 544 #endif 545 p_addr = (*vstart) + (*size) + (*phys_offset); 546 if (p_addr < test_cap - 1) { 547 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 548 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 549 return -1; 550 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 551 *size = (u32) p_size; 552 printf("Testing 0x%08llx - 0x%08llx\n", 553 (u64)(*vstart) + (*phys_offset), 554 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 555 } else 556 return 1; 557 558 return 0; 559 } 560 561 /* initialization for testing area */ 562 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 563 { 564 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 565 566 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 567 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 568 *phys_offset = 0; 569 570 #if !defined(CONFIG_PHYS_64BIT) || \ 571 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 572 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 573 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 574 puts("Cannot test more than "); 575 print_size(CONFIG_MAX_MEM_MAPPED, 576 " without proper 36BIT support.\n"); 577 } 578 #endif 579 printf("Testing 0x%08llx - 0x%08llx\n", 580 (u64)(*vstart) + (*phys_offset), 581 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 582 583 return 0; 584 } 585 586 /* invalid TLBs for DDR and remap as normal after testing */ 587 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 588 { 589 unsigned long epn; 590 u32 tsize, valid, ptr; 591 phys_addr_t rpn = 0; 592 int ddr_esel; 593 594 /* disable the TLBs for this testing */ 595 ptr = *vstart; 596 597 while (ptr < (*vstart) + (*size)) { 598 ddr_esel = find_tlb_idx((void *)ptr, 1); 599 if (ddr_esel != -1) { 600 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 601 disable_tlb(ddr_esel); 602 } 603 ptr += TSIZE_TO_BYTES(tsize); 604 } 605 606 puts("Remap DDR "); 607 setup_ddr_tlbs(gd->ram_size>>20); 608 puts("\n"); 609 610 return 0; 611 } 612 613 void arch_memory_failure_handle(void) 614 { 615 dump_spd_ddr_reg(); 616 } 617 #endif 618