1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 #include <asm/fsl_lbc.h> 38 #include <post.h> 39 #include <asm/processor.h> 40 #include <asm/fsl_ddr_sdram.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 int checkcpu (void) 45 { 46 sys_info_t sysinfo; 47 uint pvr, svr; 48 uint fam; 49 uint ver; 50 uint major, minor; 51 struct cpu_type *cpu; 52 char buf1[32], buf2[32]; 53 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 54 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 #endif /* CONFIG_FSL_CORENET */ 56 #ifdef CONFIG_DDR_CLK_FREQ 57 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 58 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 59 #else 60 #ifdef CONFIG_FSL_CORENET 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #else 64 u32 ddr_ratio = 0; 65 #endif /* CONFIG_FSL_CORENET */ 66 #endif /* CONFIG_DDR_CLK_FREQ */ 67 int i; 68 69 svr = get_svr(); 70 major = SVR_MAJ(svr); 71 #ifdef CONFIG_MPC8536 72 major &= 0x7; /* the msb of this nibble is a mfg code */ 73 #endif 74 minor = SVR_MIN(svr); 75 76 if (cpu_numcores() > 1) { 77 #ifndef CONFIG_MP 78 puts("Unicore software on multiprocessor system!!\n" 79 "To enable mutlticore build define CONFIG_MP\n"); 80 #endif 81 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 82 printf("CPU%d: ", pic->whoami); 83 } else { 84 puts("CPU: "); 85 } 86 87 cpu = gd->cpu; 88 89 puts(cpu->name); 90 if (IS_E_PROCESSOR(svr)) 91 puts("E"); 92 93 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 94 95 pvr = get_pvr(); 96 fam = PVR_FAM(pvr); 97 ver = PVR_VER(pvr); 98 major = PVR_MAJ(pvr); 99 minor = PVR_MIN(pvr); 100 101 printf("Core: "); 102 if (PVR_FAM(PVR_85xx)) { 103 switch(PVR_MEM(pvr)) { 104 case 0x1: 105 case 0x2: 106 puts("E500"); 107 break; 108 case 0x3: 109 puts("E500MC"); 110 break; 111 case 0x4: 112 puts("E5500"); 113 break; 114 default: 115 puts("Unknown"); 116 break; 117 } 118 } else { 119 puts("Unknown"); 120 } 121 122 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 123 124 get_sys_info(&sysinfo); 125 126 puts("Clock Configuration:"); 127 for (i = 0; i < cpu_numcores(); i++) { 128 if (!(i & 3)) 129 printf ("\n "); 130 printf("CPU%d:%-4s MHz, ", 131 i,strmhz(buf1, sysinfo.freqProcessor[i])); 132 } 133 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 134 135 #ifdef CONFIG_FSL_CORENET 136 if (ddr_sync == 1) { 137 printf(" DDR:%-4s MHz (%s MT/s data rate) " 138 "(Synchronous), ", 139 strmhz(buf1, sysinfo.freqDDRBus/2), 140 strmhz(buf2, sysinfo.freqDDRBus)); 141 } else { 142 printf(" DDR:%-4s MHz (%s MT/s data rate) " 143 "(Asynchronous), ", 144 strmhz(buf1, sysinfo.freqDDRBus/2), 145 strmhz(buf2, sysinfo.freqDDRBus)); 146 } 147 #else 148 switch (ddr_ratio) { 149 case 0x0: 150 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 151 strmhz(buf1, sysinfo.freqDDRBus/2), 152 strmhz(buf2, sysinfo.freqDDRBus)); 153 break; 154 case 0x7: 155 printf(" DDR:%-4s MHz (%s MT/s data rate) " 156 "(Synchronous), ", 157 strmhz(buf1, sysinfo.freqDDRBus/2), 158 strmhz(buf2, sysinfo.freqDDRBus)); 159 break; 160 default: 161 printf(" DDR:%-4s MHz (%s MT/s data rate) " 162 "(Asynchronous), ", 163 strmhz(buf1, sysinfo.freqDDRBus/2), 164 strmhz(buf2, sysinfo.freqDDRBus)); 165 break; 166 } 167 #endif 168 169 #if defined(CONFIG_FSL_LBC) 170 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 171 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 172 } else { 173 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 174 sysinfo.freqLocalBus); 175 } 176 #endif 177 178 #ifdef CONFIG_CPM2 179 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 180 #endif 181 182 #ifdef CONFIG_QE 183 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 184 #endif 185 186 #ifdef CONFIG_SYS_DPAA_FMAN 187 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 188 printf(" FMAN%d: %s MHz\n", i + 1, 189 strmhz(buf1, sysinfo.freqFMan[i])); 190 } 191 #endif 192 193 #ifdef CONFIG_SYS_DPAA_PME 194 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 195 #endif 196 197 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 198 199 return 0; 200 } 201 202 203 /* ------------------------------------------------------------------------- */ 204 205 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 206 { 207 /* Everything after the first generation of PQ3 parts has RSTCR */ 208 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 209 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 210 unsigned long val, msr; 211 212 /* 213 * Initiate hard reset in debug control register DBCR0 214 * Make sure MSR[DE] = 1. This only resets the core. 215 */ 216 msr = mfmsr (); 217 msr |= MSR_DE; 218 mtmsr (msr); 219 220 val = mfspr(DBCR0); 221 val |= 0x70000000; 222 mtspr(DBCR0,val); 223 #else 224 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 225 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 226 udelay(100); 227 #endif 228 229 return 1; 230 } 231 232 233 /* 234 * Get timebase clock frequency 235 */ 236 unsigned long get_tbclk (void) 237 { 238 #ifdef CONFIG_FSL_CORENET 239 return (gd->bus_clk + 8) / 16; 240 #else 241 return (gd->bus_clk + 4UL)/8UL; 242 #endif 243 } 244 245 246 #if defined(CONFIG_WATCHDOG) 247 void 248 watchdog_reset(void) 249 { 250 int re_enable = disable_interrupts(); 251 reset_85xx_watchdog(); 252 if (re_enable) enable_interrupts(); 253 } 254 255 void 256 reset_85xx_watchdog(void) 257 { 258 /* 259 * Clear TSR(WIS) bit by writing 1 260 */ 261 unsigned long val; 262 val = mfspr(SPRN_TSR); 263 val |= TSR_WIS; 264 mtspr(SPRN_TSR, val); 265 } 266 #endif /* CONFIG_WATCHDOG */ 267 268 /* 269 * Initializes on-chip MMC controllers. 270 * to override, implement board_mmc_init() 271 */ 272 int cpu_mmc_init(bd_t *bis) 273 { 274 #ifdef CONFIG_FSL_ESDHC 275 return fsl_esdhc_mmc_init(bis); 276 #else 277 return 0; 278 #endif 279 } 280 281 /* 282 * Print out the state of various machine registers. 283 * Currently prints out LAWs, BR0/OR0, and TLBs 284 */ 285 void mpc85xx_reginfo(void) 286 { 287 print_tlbcam(); 288 print_laws(); 289 #if defined(CONFIG_FSL_LBC) 290 print_lbc_regs(); 291 #endif 292 293 } 294 295 /* Common ddr init for non-corenet fsl 85xx platforms */ 296 #ifndef CONFIG_FSL_CORENET 297 phys_size_t initdram(int board_type) 298 { 299 phys_size_t dram_size = 0; 300 301 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 302 { 303 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 304 unsigned int x = 10; 305 unsigned int i; 306 307 /* 308 * Work around to stabilize DDR DLL 309 */ 310 out_be32(&gur->ddrdllcr, 0x81000000); 311 asm("sync;isync;msync"); 312 udelay(200); 313 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 314 setbits_be32(&gur->devdisr, 0x00010000); 315 for (i = 0; i < x; i++) 316 ; 317 clrbits_be32(&gur->devdisr, 0x00010000); 318 x++; 319 } 320 } 321 #endif 322 323 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 324 dram_size = fsl_ddr_sdram(); 325 #else 326 dram_size = fixed_sdram(); 327 #endif 328 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 329 dram_size *= 0x100000; 330 331 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 332 /* 333 * Initialize and enable DDR ECC. 334 */ 335 ddr_enable_ecc(dram_size); 336 #endif 337 338 #if defined(CONFIG_FSL_LBC) 339 /* Some boards also have sdram on the lbc */ 340 lbc_sdram_init(); 341 #endif 342 343 puts("DDR: "); 344 return dram_size; 345 } 346 #endif 347 348 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 349 350 /* Board-specific functions defined in each board's ddr.c */ 351 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 352 unsigned int ctrl_num); 353 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 354 phys_addr_t *rpn); 355 unsigned int 356 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 357 358 static void dump_spd_ddr_reg(void) 359 { 360 int i, j, k, m; 361 u8 *p_8; 362 u32 *p_32; 363 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 364 generic_spd_eeprom_t 365 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 366 367 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 368 fsl_ddr_get_spd(spd[i], i); 369 370 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 371 puts("Byte (hex) "); 372 k = 1; 373 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 374 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 375 printf("Dimm%d ", k++); 376 } 377 puts("\n"); 378 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 379 m = 0; 380 printf("%3d (0x%02x) ", k, k); 381 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 382 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 383 p_8 = (u8 *) &spd[i][j]; 384 if (p_8[k]) { 385 printf("0x%02x ", p_8[k]); 386 m++; 387 } else 388 puts(" "); 389 } 390 } 391 if (m) 392 puts("\n"); 393 else 394 puts("\r"); 395 } 396 397 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 398 switch (i) { 399 case 0: 400 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 401 break; 402 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 403 case 1: 404 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 405 break; 406 #endif 407 default: 408 printf("%s unexpected controller number = %u\n", 409 __func__, i); 410 return; 411 } 412 } 413 printf("DDR registers dump for all controllers " 414 "(zero vaule is omitted)...\n"); 415 puts("Offset (hex) "); 416 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 417 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 418 puts("\n"); 419 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 420 m = 0; 421 printf("%6d (0x%04x)", k * 4, k * 4); 422 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 423 p_32 = (u32 *) ddr[i]; 424 if (p_32[k]) { 425 printf(" 0x%08x", p_32[k]); 426 m++; 427 } else 428 puts(" "); 429 } 430 if (m) 431 puts("\n"); 432 else 433 puts("\r"); 434 } 435 puts("\n"); 436 } 437 438 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 439 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 440 { 441 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 442 unsigned long epn; 443 u32 tsize, valid, ptr; 444 phys_addr_t rpn = 0; 445 int ddr_esel; 446 447 ptr = vstart; 448 449 while (ptr < (vstart + size)) { 450 ddr_esel = find_tlb_idx((void *)ptr, 1); 451 if (ddr_esel != -1) { 452 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 453 disable_tlb(ddr_esel); 454 } 455 ptr += TSIZE_TO_BYTES(tsize); 456 } 457 458 /* Setup new tlb to cover the physical address */ 459 setup_ddr_tlbs_phys(p_addr, size>>20); 460 461 ptr = vstart; 462 ddr_esel = find_tlb_idx((void *)ptr, 1); 463 if (ddr_esel != -1) { 464 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 465 } else { 466 printf("TLB error in function %s\n", __func__); 467 return -1; 468 } 469 470 return 0; 471 } 472 473 /* 474 * slide the testing window up to test another area 475 * for 32_bit system, the maximum testable memory is limited to 476 * CONFIG_MAX_MEM_MAPPED 477 */ 478 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 479 { 480 phys_addr_t test_cap, p_addr; 481 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 482 483 #if !defined(CONFIG_PHYS_64BIT) || \ 484 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 485 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 486 test_cap = p_size; 487 #else 488 test_cap = gd->ram_size; 489 #endif 490 p_addr = (*vstart) + (*size) + (*phys_offset); 491 if (p_addr < test_cap - 1) { 492 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 493 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 494 return -1; 495 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 496 *size = (u32) p_size; 497 printf("Testing 0x%08llx - 0x%08llx\n", 498 (u64)(*vstart) + (*phys_offset), 499 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 500 } else 501 return 1; 502 503 return 0; 504 } 505 506 /* initialization for testing area */ 507 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 508 { 509 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 510 511 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 512 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 513 *phys_offset = 0; 514 515 #if !defined(CONFIG_PHYS_64BIT) || \ 516 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 517 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 518 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 519 puts("Cannot test more than "); 520 print_size(CONFIG_MAX_MEM_MAPPED, 521 " without proper 36BIT support.\n"); 522 } 523 #endif 524 printf("Testing 0x%08llx - 0x%08llx\n", 525 (u64)(*vstart) + (*phys_offset), 526 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 527 528 return 0; 529 } 530 531 /* invalid TLBs for DDR and remap as normal after testing */ 532 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 533 { 534 unsigned long epn; 535 u32 tsize, valid, ptr; 536 phys_addr_t rpn = 0; 537 int ddr_esel; 538 539 /* disable the TLBs for this testing */ 540 ptr = *vstart; 541 542 while (ptr < (*vstart) + (*size)) { 543 ddr_esel = find_tlb_idx((void *)ptr, 1); 544 if (ddr_esel != -1) { 545 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 546 disable_tlb(ddr_esel); 547 } 548 ptr += TSIZE_TO_BYTES(tsize); 549 } 550 551 puts("Remap DDR "); 552 setup_ddr_tlbs(gd->ram_size>>20); 553 puts("\n"); 554 555 return 0; 556 } 557 558 void arch_memory_failure_handle(void) 559 { 560 dump_spd_ddr_reg(); 561 } 562 #endif 563