1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* 46 * Default board reset function 47 */ 48 static void 49 __board_reset(void) 50 { 51 /* Do nothing */ 52 } 53 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 54 55 int checkcpu (void) 56 { 57 sys_info_t sysinfo; 58 uint pvr, svr; 59 uint ver; 60 uint major, minor; 61 struct cpu_type *cpu; 62 char buf1[32], buf2[32]; 63 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 64 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 65 #endif /* CONFIG_FSL_CORENET */ 66 #ifdef CONFIG_DDR_CLK_FREQ 67 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 68 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 69 #else 70 #ifdef CONFIG_FSL_CORENET 71 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 72 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 73 #else 74 u32 ddr_ratio = 0; 75 #endif /* CONFIG_FSL_CORENET */ 76 #endif /* CONFIG_DDR_CLK_FREQ */ 77 unsigned int i, core, nr_cores = cpu_numcores(); 78 u32 mask = cpu_mask(); 79 80 svr = get_svr(); 81 major = SVR_MAJ(svr); 82 minor = SVR_MIN(svr); 83 84 if (cpu_numcores() > 1) { 85 #ifndef CONFIG_MP 86 puts("Unicore software on multiprocessor system!!\n" 87 "To enable mutlticore build define CONFIG_MP\n"); 88 #endif 89 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 90 printf("CPU%d: ", pic->whoami); 91 } else { 92 puts("CPU: "); 93 } 94 95 cpu = gd->cpu; 96 97 puts(cpu->name); 98 if (IS_E_PROCESSOR(svr)) 99 puts("E"); 100 101 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 102 103 pvr = get_pvr(); 104 ver = PVR_VER(pvr); 105 major = PVR_MAJ(pvr); 106 minor = PVR_MIN(pvr); 107 108 printf("Core: "); 109 switch(ver) { 110 case PVR_VER_E500_V1: 111 case PVR_VER_E500_V2: 112 puts("E500"); 113 break; 114 case PVR_VER_E500MC: 115 puts("E500MC"); 116 break; 117 case PVR_VER_E5500: 118 puts("E5500"); 119 break; 120 default: 121 puts("Unknown"); 122 break; 123 } 124 125 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 126 127 get_sys_info(&sysinfo); 128 129 puts("Clock Configuration:"); 130 for_each_cpu(i, core, nr_cores, mask) { 131 if (!(i & 3)) 132 printf ("\n "); 133 printf("CPU%d:%-4s MHz, ", core, 134 strmhz(buf1, sysinfo.freqProcessor[core])); 135 } 136 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 137 138 #ifdef CONFIG_FSL_CORENET 139 if (ddr_sync == 1) { 140 printf(" DDR:%-4s MHz (%s MT/s data rate) " 141 "(Synchronous), ", 142 strmhz(buf1, sysinfo.freqDDRBus/2), 143 strmhz(buf2, sysinfo.freqDDRBus)); 144 } else { 145 printf(" DDR:%-4s MHz (%s MT/s data rate) " 146 "(Asynchronous), ", 147 strmhz(buf1, sysinfo.freqDDRBus/2), 148 strmhz(buf2, sysinfo.freqDDRBus)); 149 } 150 #else 151 switch (ddr_ratio) { 152 case 0x0: 153 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 154 strmhz(buf1, sysinfo.freqDDRBus/2), 155 strmhz(buf2, sysinfo.freqDDRBus)); 156 break; 157 case 0x7: 158 printf(" DDR:%-4s MHz (%s MT/s data rate) " 159 "(Synchronous), ", 160 strmhz(buf1, sysinfo.freqDDRBus/2), 161 strmhz(buf2, sysinfo.freqDDRBus)); 162 break; 163 default: 164 printf(" DDR:%-4s MHz (%s MT/s data rate) " 165 "(Asynchronous), ", 166 strmhz(buf1, sysinfo.freqDDRBus/2), 167 strmhz(buf2, sysinfo.freqDDRBus)); 168 break; 169 } 170 #endif 171 172 #if defined(CONFIG_FSL_LBC) 173 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 174 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 175 } else { 176 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 177 sysinfo.freqLocalBus); 178 } 179 #endif 180 181 #ifdef CONFIG_CPM2 182 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 183 #endif 184 185 #ifdef CONFIG_QE 186 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 187 #endif 188 189 #ifdef CONFIG_SYS_DPAA_FMAN 190 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 191 printf(" FMAN%d: %s MHz\n", i + 1, 192 strmhz(buf1, sysinfo.freqFMan[i])); 193 } 194 #endif 195 196 #ifdef CONFIG_SYS_DPAA_PME 197 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 198 #endif 199 200 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 201 202 return 0; 203 } 204 205 206 /* ------------------------------------------------------------------------- */ 207 208 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 209 { 210 /* Everything after the first generation of PQ3 parts has RSTCR */ 211 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 212 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 213 unsigned long val, msr; 214 215 /* 216 * Initiate hard reset in debug control register DBCR0 217 * Make sure MSR[DE] = 1. This only resets the core. 218 */ 219 msr = mfmsr (); 220 msr |= MSR_DE; 221 mtmsr (msr); 222 223 val = mfspr(DBCR0); 224 val |= 0x70000000; 225 mtspr(DBCR0,val); 226 #else 227 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 228 229 /* Attempt board-specific reset */ 230 board_reset(); 231 232 /* Next try asserting HRESET_REQ */ 233 out_be32(&gur->rstcr, 0x2); 234 udelay(100); 235 #endif 236 237 return 1; 238 } 239 240 241 /* 242 * Get timebase clock frequency 243 */ 244 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 245 #define CONFIG_SYS_FSL_TBCLK_DIV 8 246 #endif 247 unsigned long get_tbclk (void) 248 { 249 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 250 251 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 252 } 253 254 255 #if defined(CONFIG_WATCHDOG) 256 void 257 watchdog_reset(void) 258 { 259 int re_enable = disable_interrupts(); 260 reset_85xx_watchdog(); 261 if (re_enable) enable_interrupts(); 262 } 263 264 void 265 reset_85xx_watchdog(void) 266 { 267 /* 268 * Clear TSR(WIS) bit by writing 1 269 */ 270 unsigned long val; 271 val = mfspr(SPRN_TSR); 272 val |= TSR_WIS; 273 mtspr(SPRN_TSR, val); 274 } 275 #endif /* CONFIG_WATCHDOG */ 276 277 /* 278 * Initializes on-chip MMC controllers. 279 * to override, implement board_mmc_init() 280 */ 281 int cpu_mmc_init(bd_t *bis) 282 { 283 #ifdef CONFIG_FSL_ESDHC 284 return fsl_esdhc_mmc_init(bis); 285 #else 286 return 0; 287 #endif 288 } 289 290 /* 291 * Print out the state of various machine registers. 292 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 293 * parameters for IFC and TLBs 294 */ 295 void mpc85xx_reginfo(void) 296 { 297 print_tlbcam(); 298 print_laws(); 299 #if defined(CONFIG_FSL_LBC) 300 print_lbc_regs(); 301 #endif 302 #ifdef CONFIG_FSL_IFC 303 print_ifc_regs(); 304 #endif 305 306 } 307 308 /* Common ddr init for non-corenet fsl 85xx platforms */ 309 #ifndef CONFIG_FSL_CORENET 310 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 311 phys_size_t initdram(int board_type) 312 { 313 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 314 return fsl_ddr_sdram_size(); 315 #else 316 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 317 #endif 318 } 319 #else /* CONFIG_SYS_RAMBOOT */ 320 phys_size_t initdram(int board_type) 321 { 322 phys_size_t dram_size = 0; 323 324 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 325 { 326 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 327 unsigned int x = 10; 328 unsigned int i; 329 330 /* 331 * Work around to stabilize DDR DLL 332 */ 333 out_be32(&gur->ddrdllcr, 0x81000000); 334 asm("sync;isync;msync"); 335 udelay(200); 336 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 337 setbits_be32(&gur->devdisr, 0x00010000); 338 for (i = 0; i < x; i++) 339 ; 340 clrbits_be32(&gur->devdisr, 0x00010000); 341 x++; 342 } 343 } 344 #endif 345 346 #if defined(CONFIG_SPD_EEPROM) || \ 347 defined(CONFIG_DDR_SPD) || \ 348 defined(CONFIG_SYS_DDR_RAW_TIMING) 349 dram_size = fsl_ddr_sdram(); 350 #else 351 dram_size = fixed_sdram(); 352 #endif 353 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 354 dram_size *= 0x100000; 355 356 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 357 /* 358 * Initialize and enable DDR ECC. 359 */ 360 ddr_enable_ecc(dram_size); 361 #endif 362 363 #if defined(CONFIG_FSL_LBC) 364 /* Some boards also have sdram on the lbc */ 365 lbc_sdram_init(); 366 #endif 367 368 debug("DDR: "); 369 return dram_size; 370 } 371 #endif /* CONFIG_SYS_RAMBOOT */ 372 #endif 373 374 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 375 376 /* Board-specific functions defined in each board's ddr.c */ 377 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 378 unsigned int ctrl_num); 379 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 380 phys_addr_t *rpn); 381 unsigned int 382 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 383 384 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 385 386 static void dump_spd_ddr_reg(void) 387 { 388 int i, j, k, m; 389 u8 *p_8; 390 u32 *p_32; 391 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 392 generic_spd_eeprom_t 393 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 394 395 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 396 fsl_ddr_get_spd(spd[i], i); 397 398 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 399 puts("Byte (hex) "); 400 k = 1; 401 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 402 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 403 printf("Dimm%d ", k++); 404 } 405 puts("\n"); 406 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 407 m = 0; 408 printf("%3d (0x%02x) ", k, k); 409 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 410 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 411 p_8 = (u8 *) &spd[i][j]; 412 if (p_8[k]) { 413 printf("0x%02x ", p_8[k]); 414 m++; 415 } else 416 puts(" "); 417 } 418 } 419 if (m) 420 puts("\n"); 421 else 422 puts("\r"); 423 } 424 425 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 426 switch (i) { 427 case 0: 428 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 429 break; 430 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 431 case 1: 432 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 433 break; 434 #endif 435 default: 436 printf("%s unexpected controller number = %u\n", 437 __func__, i); 438 return; 439 } 440 } 441 printf("DDR registers dump for all controllers " 442 "(zero vaule is omitted)...\n"); 443 puts("Offset (hex) "); 444 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 445 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 446 puts("\n"); 447 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 448 m = 0; 449 printf("%6d (0x%04x)", k * 4, k * 4); 450 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 451 p_32 = (u32 *) ddr[i]; 452 if (p_32[k]) { 453 printf(" 0x%08x", p_32[k]); 454 m++; 455 } else 456 puts(" "); 457 } 458 if (m) 459 puts("\n"); 460 else 461 puts("\r"); 462 } 463 puts("\n"); 464 } 465 466 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 467 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 468 { 469 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 470 unsigned long epn; 471 u32 tsize, valid, ptr; 472 int ddr_esel; 473 474 clear_ddr_tlbs_phys(p_addr, size>>20); 475 476 /* Setup new tlb to cover the physical address */ 477 setup_ddr_tlbs_phys(p_addr, size>>20); 478 479 ptr = vstart; 480 ddr_esel = find_tlb_idx((void *)ptr, 1); 481 if (ddr_esel != -1) { 482 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 483 } else { 484 printf("TLB error in function %s\n", __func__); 485 return -1; 486 } 487 488 return 0; 489 } 490 491 /* 492 * slide the testing window up to test another area 493 * for 32_bit system, the maximum testable memory is limited to 494 * CONFIG_MAX_MEM_MAPPED 495 */ 496 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 497 { 498 phys_addr_t test_cap, p_addr; 499 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 500 501 #if !defined(CONFIG_PHYS_64BIT) || \ 502 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 503 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 504 test_cap = p_size; 505 #else 506 test_cap = gd->ram_size; 507 #endif 508 p_addr = (*vstart) + (*size) + (*phys_offset); 509 if (p_addr < test_cap - 1) { 510 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 511 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 512 return -1; 513 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 514 *size = (u32) p_size; 515 printf("Testing 0x%08llx - 0x%08llx\n", 516 (u64)(*vstart) + (*phys_offset), 517 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 518 } else 519 return 1; 520 521 return 0; 522 } 523 524 /* initialization for testing area */ 525 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 526 { 527 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 528 529 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 530 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 531 *phys_offset = 0; 532 533 #if !defined(CONFIG_PHYS_64BIT) || \ 534 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 535 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 536 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 537 puts("Cannot test more than "); 538 print_size(CONFIG_MAX_MEM_MAPPED, 539 " without proper 36BIT support.\n"); 540 } 541 #endif 542 printf("Testing 0x%08llx - 0x%08llx\n", 543 (u64)(*vstart) + (*phys_offset), 544 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 545 546 return 0; 547 } 548 549 /* invalid TLBs for DDR and remap as normal after testing */ 550 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 551 { 552 unsigned long epn; 553 u32 tsize, valid, ptr; 554 phys_addr_t rpn = 0; 555 int ddr_esel; 556 557 /* disable the TLBs for this testing */ 558 ptr = *vstart; 559 560 while (ptr < (*vstart) + (*size)) { 561 ddr_esel = find_tlb_idx((void *)ptr, 1); 562 if (ddr_esel != -1) { 563 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 564 disable_tlb(ddr_esel); 565 } 566 ptr += TSIZE_TO_BYTES(tsize); 567 } 568 569 puts("Remap DDR "); 570 setup_ddr_tlbs(gd->ram_size>>20); 571 puts("\n"); 572 573 return 0; 574 } 575 576 void arch_memory_failure_handle(void) 577 { 578 dump_spd_ddr_reg(); 579 } 580 #endif 581