1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu (void) 46 { 47 sys_info_t sysinfo; 48 uint pvr, svr; 49 uint ver; 50 uint major, minor; 51 struct cpu_type *cpu; 52 char buf1[32], buf2[32]; 53 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 54 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 #endif /* CONFIG_FSL_CORENET */ 56 #ifdef CONFIG_DDR_CLK_FREQ 57 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 58 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 59 #else 60 #ifdef CONFIG_FSL_CORENET 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #else 64 u32 ddr_ratio = 0; 65 #endif /* CONFIG_FSL_CORENET */ 66 #endif /* CONFIG_DDR_CLK_FREQ */ 67 int i; 68 69 svr = get_svr(); 70 major = SVR_MAJ(svr); 71 #ifdef CONFIG_MPC8536 72 major &= 0x7; /* the msb of this nibble is a mfg code */ 73 #endif 74 minor = SVR_MIN(svr); 75 76 if (cpu_numcores() > 1) { 77 #ifndef CONFIG_MP 78 puts("Unicore software on multiprocessor system!!\n" 79 "To enable mutlticore build define CONFIG_MP\n"); 80 #endif 81 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 82 printf("CPU%d: ", pic->whoami); 83 } else { 84 puts("CPU: "); 85 } 86 87 cpu = gd->cpu; 88 89 puts(cpu->name); 90 if (IS_E_PROCESSOR(svr)) 91 puts("E"); 92 93 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 94 95 pvr = get_pvr(); 96 ver = PVR_VER(pvr); 97 major = PVR_MAJ(pvr); 98 minor = PVR_MIN(pvr); 99 100 printf("Core: "); 101 switch(ver) { 102 case PVR_VER_E500_V1: 103 case PVR_VER_E500_V2: 104 puts("E500"); 105 break; 106 case PVR_VER_E500MC: 107 puts("E500MC"); 108 break; 109 case PVR_VER_E5500: 110 puts("E5500"); 111 break; 112 default: 113 puts("Unknown"); 114 break; 115 } 116 117 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 118 119 get_sys_info(&sysinfo); 120 121 puts("Clock Configuration:"); 122 for (i = 0; i < cpu_numcores(); i++) { 123 if (!(i & 3)) 124 printf ("\n "); 125 printf("CPU%d:%-4s MHz, ", 126 i,strmhz(buf1, sysinfo.freqProcessor[i])); 127 } 128 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 129 130 #ifdef CONFIG_FSL_CORENET 131 if (ddr_sync == 1) { 132 printf(" DDR:%-4s MHz (%s MT/s data rate) " 133 "(Synchronous), ", 134 strmhz(buf1, sysinfo.freqDDRBus/2), 135 strmhz(buf2, sysinfo.freqDDRBus)); 136 } else { 137 printf(" DDR:%-4s MHz (%s MT/s data rate) " 138 "(Asynchronous), ", 139 strmhz(buf1, sysinfo.freqDDRBus/2), 140 strmhz(buf2, sysinfo.freqDDRBus)); 141 } 142 #else 143 switch (ddr_ratio) { 144 case 0x0: 145 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 146 strmhz(buf1, sysinfo.freqDDRBus/2), 147 strmhz(buf2, sysinfo.freqDDRBus)); 148 break; 149 case 0x7: 150 printf(" DDR:%-4s MHz (%s MT/s data rate) " 151 "(Synchronous), ", 152 strmhz(buf1, sysinfo.freqDDRBus/2), 153 strmhz(buf2, sysinfo.freqDDRBus)); 154 break; 155 default: 156 printf(" DDR:%-4s MHz (%s MT/s data rate) " 157 "(Asynchronous), ", 158 strmhz(buf1, sysinfo.freqDDRBus/2), 159 strmhz(buf2, sysinfo.freqDDRBus)); 160 break; 161 } 162 #endif 163 164 #if defined(CONFIG_FSL_LBC) 165 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 166 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 167 } else { 168 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 169 sysinfo.freqLocalBus); 170 } 171 #endif 172 173 #ifdef CONFIG_CPM2 174 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 175 #endif 176 177 #ifdef CONFIG_QE 178 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 179 #endif 180 181 #ifdef CONFIG_SYS_DPAA_FMAN 182 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 183 printf(" FMAN%d: %s MHz\n", i + 1, 184 strmhz(buf1, sysinfo.freqFMan[i])); 185 } 186 #endif 187 188 #ifdef CONFIG_SYS_DPAA_PME 189 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 190 #endif 191 192 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 193 194 return 0; 195 } 196 197 198 /* ------------------------------------------------------------------------- */ 199 200 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 201 { 202 /* Everything after the first generation of PQ3 parts has RSTCR */ 203 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 204 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 205 unsigned long val, msr; 206 207 /* 208 * Initiate hard reset in debug control register DBCR0 209 * Make sure MSR[DE] = 1. This only resets the core. 210 */ 211 msr = mfmsr (); 212 msr |= MSR_DE; 213 mtmsr (msr); 214 215 val = mfspr(DBCR0); 216 val |= 0x70000000; 217 mtspr(DBCR0,val); 218 #else 219 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 220 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 221 udelay(100); 222 #endif 223 224 return 1; 225 } 226 227 228 /* 229 * Get timebase clock frequency 230 */ 231 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 232 #define CONFIG_SYS_FSL_TBCLK_DIV 8 233 #endif 234 unsigned long get_tbclk (void) 235 { 236 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 237 238 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 239 } 240 241 242 #if defined(CONFIG_WATCHDOG) 243 void 244 watchdog_reset(void) 245 { 246 int re_enable = disable_interrupts(); 247 reset_85xx_watchdog(); 248 if (re_enable) enable_interrupts(); 249 } 250 251 void 252 reset_85xx_watchdog(void) 253 { 254 /* 255 * Clear TSR(WIS) bit by writing 1 256 */ 257 unsigned long val; 258 val = mfspr(SPRN_TSR); 259 val |= TSR_WIS; 260 mtspr(SPRN_TSR, val); 261 } 262 #endif /* CONFIG_WATCHDOG */ 263 264 /* 265 * Initializes on-chip MMC controllers. 266 * to override, implement board_mmc_init() 267 */ 268 int cpu_mmc_init(bd_t *bis) 269 { 270 #ifdef CONFIG_FSL_ESDHC 271 return fsl_esdhc_mmc_init(bis); 272 #else 273 return 0; 274 #endif 275 } 276 277 /* 278 * Print out the state of various machine registers. 279 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 280 * parameters for IFC and TLBs 281 */ 282 void mpc85xx_reginfo(void) 283 { 284 print_tlbcam(); 285 print_laws(); 286 #if defined(CONFIG_FSL_LBC) 287 print_lbc_regs(); 288 #endif 289 #ifdef CONFIG_FSL_IFC 290 print_ifc_regs(); 291 #endif 292 293 } 294 295 /* Common ddr init for non-corenet fsl 85xx platforms */ 296 #ifndef CONFIG_FSL_CORENET 297 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 298 phys_size_t initdram(int board_type) 299 { 300 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 301 return fsl_ddr_sdram_size(); 302 #else 303 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 304 #endif 305 } 306 #else /* CONFIG_SYS_RAMBOOT */ 307 phys_size_t initdram(int board_type) 308 { 309 phys_size_t dram_size = 0; 310 311 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 312 { 313 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 314 unsigned int x = 10; 315 unsigned int i; 316 317 /* 318 * Work around to stabilize DDR DLL 319 */ 320 out_be32(&gur->ddrdllcr, 0x81000000); 321 asm("sync;isync;msync"); 322 udelay(200); 323 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 324 setbits_be32(&gur->devdisr, 0x00010000); 325 for (i = 0; i < x; i++) 326 ; 327 clrbits_be32(&gur->devdisr, 0x00010000); 328 x++; 329 } 330 } 331 #endif 332 333 #if defined(CONFIG_SPD_EEPROM) || \ 334 defined(CONFIG_DDR_SPD) || \ 335 defined(CONFIG_SYS_DDR_RAW_TIMING) 336 dram_size = fsl_ddr_sdram(); 337 #else 338 dram_size = fixed_sdram(); 339 #endif 340 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 341 dram_size *= 0x100000; 342 343 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 344 /* 345 * Initialize and enable DDR ECC. 346 */ 347 ddr_enable_ecc(dram_size); 348 #endif 349 350 #if defined(CONFIG_FSL_LBC) 351 /* Some boards also have sdram on the lbc */ 352 lbc_sdram_init(); 353 #endif 354 355 debug("DDR: "); 356 return dram_size; 357 } 358 #endif /* CONFIG_SYS_RAMBOOT */ 359 #endif 360 361 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 362 363 /* Board-specific functions defined in each board's ddr.c */ 364 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 365 unsigned int ctrl_num); 366 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 367 phys_addr_t *rpn); 368 unsigned int 369 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 370 371 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 372 373 static void dump_spd_ddr_reg(void) 374 { 375 int i, j, k, m; 376 u8 *p_8; 377 u32 *p_32; 378 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 379 generic_spd_eeprom_t 380 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 381 382 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 383 fsl_ddr_get_spd(spd[i], i); 384 385 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 386 puts("Byte (hex) "); 387 k = 1; 388 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 389 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 390 printf("Dimm%d ", k++); 391 } 392 puts("\n"); 393 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 394 m = 0; 395 printf("%3d (0x%02x) ", k, k); 396 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 397 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 398 p_8 = (u8 *) &spd[i][j]; 399 if (p_8[k]) { 400 printf("0x%02x ", p_8[k]); 401 m++; 402 } else 403 puts(" "); 404 } 405 } 406 if (m) 407 puts("\n"); 408 else 409 puts("\r"); 410 } 411 412 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 413 switch (i) { 414 case 0: 415 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 416 break; 417 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 418 case 1: 419 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 420 break; 421 #endif 422 default: 423 printf("%s unexpected controller number = %u\n", 424 __func__, i); 425 return; 426 } 427 } 428 printf("DDR registers dump for all controllers " 429 "(zero vaule is omitted)...\n"); 430 puts("Offset (hex) "); 431 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 432 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 433 puts("\n"); 434 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 435 m = 0; 436 printf("%6d (0x%04x)", k * 4, k * 4); 437 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 438 p_32 = (u32 *) ddr[i]; 439 if (p_32[k]) { 440 printf(" 0x%08x", p_32[k]); 441 m++; 442 } else 443 puts(" "); 444 } 445 if (m) 446 puts("\n"); 447 else 448 puts("\r"); 449 } 450 puts("\n"); 451 } 452 453 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 454 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 455 { 456 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 457 unsigned long epn; 458 u32 tsize, valid, ptr; 459 int ddr_esel; 460 461 clear_ddr_tlbs_phys(p_addr, size>>20); 462 463 /* Setup new tlb to cover the physical address */ 464 setup_ddr_tlbs_phys(p_addr, size>>20); 465 466 ptr = vstart; 467 ddr_esel = find_tlb_idx((void *)ptr, 1); 468 if (ddr_esel != -1) { 469 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 470 } else { 471 printf("TLB error in function %s\n", __func__); 472 return -1; 473 } 474 475 return 0; 476 } 477 478 /* 479 * slide the testing window up to test another area 480 * for 32_bit system, the maximum testable memory is limited to 481 * CONFIG_MAX_MEM_MAPPED 482 */ 483 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 484 { 485 phys_addr_t test_cap, p_addr; 486 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 487 488 #if !defined(CONFIG_PHYS_64BIT) || \ 489 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 490 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 491 test_cap = p_size; 492 #else 493 test_cap = gd->ram_size; 494 #endif 495 p_addr = (*vstart) + (*size) + (*phys_offset); 496 if (p_addr < test_cap - 1) { 497 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 498 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 499 return -1; 500 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 501 *size = (u32) p_size; 502 printf("Testing 0x%08llx - 0x%08llx\n", 503 (u64)(*vstart) + (*phys_offset), 504 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 505 } else 506 return 1; 507 508 return 0; 509 } 510 511 /* initialization for testing area */ 512 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 513 { 514 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 515 516 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 517 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 518 *phys_offset = 0; 519 520 #if !defined(CONFIG_PHYS_64BIT) || \ 521 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 522 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 523 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 524 puts("Cannot test more than "); 525 print_size(CONFIG_MAX_MEM_MAPPED, 526 " without proper 36BIT support.\n"); 527 } 528 #endif 529 printf("Testing 0x%08llx - 0x%08llx\n", 530 (u64)(*vstart) + (*phys_offset), 531 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 532 533 return 0; 534 } 535 536 /* invalid TLBs for DDR and remap as normal after testing */ 537 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 538 { 539 unsigned long epn; 540 u32 tsize, valid, ptr; 541 phys_addr_t rpn = 0; 542 int ddr_esel; 543 544 /* disable the TLBs for this testing */ 545 ptr = *vstart; 546 547 while (ptr < (*vstart) + (*size)) { 548 ddr_esel = find_tlb_idx((void *)ptr, 1); 549 if (ddr_esel != -1) { 550 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 551 disable_tlb(ddr_esel); 552 } 553 ptr += TSIZE_TO_BYTES(tsize); 554 } 555 556 puts("Remap DDR "); 557 setup_ddr_tlbs(gd->ram_size>>20); 558 puts("\n"); 559 560 return 0; 561 } 562 563 void arch_memory_failure_handle(void) 564 { 565 dump_spd_ddr_reg(); 566 } 567 #endif 568