1 /* 2 * Copyright 2004,2007-2009 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 int checkcpu (void) 39 { 40 sys_info_t sysinfo; 41 uint pvr, svr; 42 uint fam; 43 uint ver; 44 uint major, minor; 45 struct cpu_type *cpu; 46 char buf1[32], buf2[32]; 47 #ifdef CONFIG_DDR_CLK_FREQ 48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49 #ifdef CONFIG_FSL_CORENET 50 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 51 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 52 #else 53 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 54 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 55 #endif 56 #else 57 #ifdef CONFIG_FSL_CORENET 58 u32 ddr_sync = 0; 59 #else 60 u32 ddr_ratio = 0; 61 #endif 62 #endif /* CONFIG_DDR_CLK_FREQ */ 63 int i; 64 65 svr = get_svr(); 66 major = SVR_MAJ(svr); 67 #ifdef CONFIG_MPC8536 68 major &= 0x7; /* the msb of this nibble is a mfg code */ 69 #endif 70 minor = SVR_MIN(svr); 71 72 if (cpu_numcores() > 1) { 73 #ifndef CONFIG_MP 74 puts("Unicore software on multiprocessor system!!\n" 75 "To enable mutlticore build define CONFIG_MP\n"); 76 #endif 77 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 78 printf("CPU%d: ", pic->whoami); 79 } else { 80 puts("CPU: "); 81 } 82 83 cpu = gd->cpu; 84 85 puts(cpu->name); 86 if (IS_E_PROCESSOR(svr)) 87 puts("E"); 88 89 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 90 91 pvr = get_pvr(); 92 fam = PVR_FAM(pvr); 93 ver = PVR_VER(pvr); 94 major = PVR_MAJ(pvr); 95 minor = PVR_MIN(pvr); 96 97 printf("Core: "); 98 switch (fam) { 99 case PVR_FAM(PVR_85xx): 100 puts("E500"); 101 break; 102 default: 103 puts("Unknown"); 104 break; 105 } 106 107 if (PVR_MEM(pvr) == 0x03) 108 puts("MC"); 109 110 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 111 112 get_sys_info(&sysinfo); 113 114 puts("Clock Configuration:"); 115 for (i = 0; i < cpu_numcores(); i++) { 116 if (!(i & 3)) 117 printf ("\n "); 118 printf("CPU%d:%-4s MHz, ", 119 i,strmhz(buf1, sysinfo.freqProcessor[i])); 120 } 121 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 122 123 #ifdef CONFIG_FSL_CORENET 124 if (ddr_sync == 1) { 125 printf(" DDR:%-4s MHz (%s MT/s data rate) " 126 "(Synchronous), ", 127 strmhz(buf1, sysinfo.freqDDRBus/2), 128 strmhz(buf2, sysinfo.freqDDRBus)); 129 } else { 130 printf(" DDR:%-4s MHz (%s MT/s data rate) " 131 "(Asynchronous), ", 132 strmhz(buf1, sysinfo.freqDDRBus/2), 133 strmhz(buf2, sysinfo.freqDDRBus)); 134 } 135 #else 136 switch (ddr_ratio) { 137 case 0x0: 138 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 139 strmhz(buf1, sysinfo.freqDDRBus/2), 140 strmhz(buf2, sysinfo.freqDDRBus)); 141 break; 142 case 0x7: 143 printf(" DDR:%-4s MHz (%s MT/s data rate) " 144 "(Synchronous), ", 145 strmhz(buf1, sysinfo.freqDDRBus/2), 146 strmhz(buf2, sysinfo.freqDDRBus)); 147 break; 148 default: 149 printf(" DDR:%-4s MHz (%s MT/s data rate) " 150 "(Asynchronous), ", 151 strmhz(buf1, sysinfo.freqDDRBus/2), 152 strmhz(buf2, sysinfo.freqDDRBus)); 153 break; 154 } 155 #endif 156 157 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 158 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 159 } else { 160 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 161 sysinfo.freqLocalBus); 162 } 163 164 #ifdef CONFIG_CPM2 165 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 166 #endif 167 168 #ifdef CONFIG_QE 169 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 170 #endif 171 172 #ifdef CONFIG_SYS_DPAA_FMAN 173 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 174 printf(" FMAN%d: %s MHz\n", i, 175 strmhz(buf1, sysinfo.freqFMan[i])); 176 } 177 #endif 178 179 #ifdef CONFIG_SYS_DPAA_PME 180 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 181 #endif 182 183 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 184 185 return 0; 186 } 187 188 189 /* ------------------------------------------------------------------------- */ 190 191 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) 192 { 193 /* Everything after the first generation of PQ3 parts has RSTCR */ 194 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 195 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 196 unsigned long val, msr; 197 198 /* 199 * Initiate hard reset in debug control register DBCR0 200 * Make sure MSR[DE] = 1. This only resets the core. 201 */ 202 msr = mfmsr (); 203 msr |= MSR_DE; 204 mtmsr (msr); 205 206 val = mfspr(DBCR0); 207 val |= 0x70000000; 208 mtspr(DBCR0,val); 209 #else 210 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 211 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 212 udelay(100); 213 #endif 214 215 return 1; 216 } 217 218 219 /* 220 * Get timebase clock frequency 221 */ 222 unsigned long get_tbclk (void) 223 { 224 #ifdef CONFIG_FSL_CORENET 225 return (gd->bus_clk + 8) / 16; 226 #else 227 return (gd->bus_clk + 4UL)/8UL; 228 #endif 229 } 230 231 232 #if defined(CONFIG_WATCHDOG) 233 void 234 watchdog_reset(void) 235 { 236 int re_enable = disable_interrupts(); 237 reset_85xx_watchdog(); 238 if (re_enable) enable_interrupts(); 239 } 240 241 void 242 reset_85xx_watchdog(void) 243 { 244 /* 245 * Clear TSR(WIS) bit by writing 1 246 */ 247 unsigned long val; 248 val = mfspr(SPRN_TSR); 249 val |= TSR_WIS; 250 mtspr(SPRN_TSR, val); 251 } 252 #endif /* CONFIG_WATCHDOG */ 253 254 /* 255 * Configures a UPM. The function requires the respective MxMR to be set 256 * before calling this function. "size" is the number or entries, not a sizeof. 257 */ 258 void upmconfig (uint upm, uint * table, uint size) 259 { 260 int i, mdr, mad, old_mad = 0; 261 volatile u32 *mxmr; 262 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 263 volatile u32 *brp,*orp; 264 volatile u8* dummy = NULL; 265 int upmmask; 266 267 switch (upm) { 268 case UPMA: 269 mxmr = &lbc->mamr; 270 upmmask = BR_MS_UPMA; 271 break; 272 case UPMB: 273 mxmr = &lbc->mbmr; 274 upmmask = BR_MS_UPMB; 275 break; 276 case UPMC: 277 mxmr = &lbc->mcmr; 278 upmmask = BR_MS_UPMC; 279 break; 280 default: 281 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); 282 hang(); 283 } 284 285 /* Find the address for the dummy write transaction */ 286 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; 287 i++, brp += 2, orp += 2) { 288 289 /* Look for a valid BR with selected UPM */ 290 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { 291 dummy = (volatile u8*)(in_be32(brp) & BR_BA); 292 break; 293 } 294 } 295 296 if (i == 8) { 297 printf("Error: %s() could not find matching BR\n", __FUNCTION__); 298 hang(); 299 } 300 301 for (i = 0; i < size; i++) { 302 /* 1 */ 303 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); 304 /* 2 */ 305 out_be32(&lbc->mdr, table[i]); 306 /* 3 */ 307 mdr = in_be32(&lbc->mdr); 308 /* 4 */ 309 *(volatile u8 *)dummy = 0; 310 /* 5 */ 311 do { 312 mad = in_be32(mxmr) & MxMR_MAD_MSK; 313 } while (mad <= old_mad && !(!mad && i == (size-1))); 314 old_mad = mad; 315 } 316 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); 317 } 318 319 /* 320 * Initializes on-chip MMC controllers. 321 * to override, implement board_mmc_init() 322 */ 323 int cpu_mmc_init(bd_t *bis) 324 { 325 #ifdef CONFIG_FSL_ESDHC 326 return fsl_esdhc_mmc_init(bis); 327 #else 328 return 0; 329 #endif 330 } 331