1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <watchdog.h> 15 #include <command.h> 16 #include <fsl_esdhc.h> 17 #include <asm/cache.h> 18 #include <asm/io.h> 19 #include <asm/mmu.h> 20 #include <fsl_ifc.h> 21 #include <asm/fsl_law.h> 22 #include <asm/fsl_lbc.h> 23 #include <post.h> 24 #include <asm/processor.h> 25 #include <fsl_ddr_sdram.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* 30 * Default board reset function 31 */ 32 static void 33 __board_reset(void) 34 { 35 /* Do nothing */ 36 } 37 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 38 39 int checkcpu (void) 40 { 41 sys_info_t sysinfo; 42 uint pvr, svr; 43 uint ver; 44 uint major, minor; 45 struct cpu_type *cpu; 46 char buf1[32], buf2[32]; 47 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 48 ccsr_gur_t __iomem *gur = 49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 #endif 51 52 /* 53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async 54 * mode. Previous platform use ddr ratio to do the same. This 55 * information is only for display here. 56 */ 57 #ifdef CONFIG_FSL_CORENET 58 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 59 u32 ddr_sync = 0; /* only async mode is supported */ 60 #else 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 64 #else /* CONFIG_FSL_CORENET */ 65 #ifdef CONFIG_DDR_CLK_FREQ 66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 68 #else 69 u32 ddr_ratio = 0; 70 #endif /* CONFIG_DDR_CLK_FREQ */ 71 #endif /* CONFIG_FSL_CORENET */ 72 73 unsigned int i, core, nr_cores = cpu_numcores(); 74 u32 mask = cpu_mask(); 75 76 svr = get_svr(); 77 major = SVR_MAJ(svr); 78 minor = SVR_MIN(svr); 79 80 if (cpu_numcores() > 1) { 81 #ifndef CONFIG_MP 82 puts("Unicore software on multiprocessor system!!\n" 83 "To enable mutlticore build define CONFIG_MP\n"); 84 #endif 85 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 86 printf("CPU%d: ", pic->whoami); 87 } else { 88 puts("CPU: "); 89 } 90 91 cpu = gd->arch.cpu; 92 93 puts(cpu->name); 94 if (IS_E_PROCESSOR(svr)) 95 puts("E"); 96 97 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 98 99 pvr = get_pvr(); 100 ver = PVR_VER(pvr); 101 major = PVR_MAJ(pvr); 102 minor = PVR_MIN(pvr); 103 104 printf("Core: "); 105 switch(ver) { 106 case PVR_VER_E500_V1: 107 case PVR_VER_E500_V2: 108 puts("e500"); 109 break; 110 case PVR_VER_E500MC: 111 puts("e500mc"); 112 break; 113 case PVR_VER_E5500: 114 puts("e5500"); 115 break; 116 case PVR_VER_E6500: 117 puts("e6500"); 118 break; 119 default: 120 puts("Unknown"); 121 break; 122 } 123 124 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 125 126 if (nr_cores > CONFIG_MAX_CPUS) { 127 panic("\nUnexpected number of cores: %d, max is %d\n", 128 nr_cores, CONFIG_MAX_CPUS); 129 } 130 131 get_sys_info(&sysinfo); 132 133 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 134 if (sysinfo.diff_sysclk == 1) 135 puts("Single Source Clock Configuration\n"); 136 #endif 137 138 puts("Clock Configuration:"); 139 for_each_cpu(i, core, nr_cores, mask) { 140 if (!(i & 3)) 141 printf ("\n "); 142 printf("CPU%d:%-4s MHz, ", core, 143 strmhz(buf1, sysinfo.freq_processor[core])); 144 } 145 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); 146 printf("\n"); 147 148 #ifdef CONFIG_FSL_CORENET 149 if (ddr_sync == 1) { 150 printf(" DDR:%-4s MHz (%s MT/s data rate) " 151 "(Synchronous), ", 152 strmhz(buf1, sysinfo.freq_ddrbus/2), 153 strmhz(buf2, sysinfo.freq_ddrbus)); 154 } else { 155 printf(" DDR:%-4s MHz (%s MT/s data rate) " 156 "(Asynchronous), ", 157 strmhz(buf1, sysinfo.freq_ddrbus/2), 158 strmhz(buf2, sysinfo.freq_ddrbus)); 159 } 160 #else 161 switch (ddr_ratio) { 162 case 0x0: 163 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 164 strmhz(buf1, sysinfo.freq_ddrbus/2), 165 strmhz(buf2, sysinfo.freq_ddrbus)); 166 break; 167 case 0x7: 168 printf(" DDR:%-4s MHz (%s MT/s data rate) " 169 "(Synchronous), ", 170 strmhz(buf1, sysinfo.freq_ddrbus/2), 171 strmhz(buf2, sysinfo.freq_ddrbus)); 172 break; 173 default: 174 printf(" DDR:%-4s MHz (%s MT/s data rate) " 175 "(Asynchronous), ", 176 strmhz(buf1, sysinfo.freq_ddrbus/2), 177 strmhz(buf2, sysinfo.freq_ddrbus)); 178 break; 179 } 180 #endif 181 182 #if defined(CONFIG_FSL_LBC) 183 if (sysinfo.freq_localbus > LCRR_CLKDIV) { 184 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); 185 } else { 186 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 187 sysinfo.freq_localbus); 188 } 189 #endif 190 191 #if defined(CONFIG_FSL_IFC) 192 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); 193 #endif 194 195 #ifdef CONFIG_CPM2 196 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); 197 #endif 198 199 #ifdef CONFIG_QE 200 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); 201 #endif 202 203 #ifdef CONFIG_SYS_DPAA_FMAN 204 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 205 printf(" FMAN%d: %s MHz\n", i + 1, 206 strmhz(buf1, sysinfo.freq_fman[i])); 207 } 208 #endif 209 210 #ifdef CONFIG_SYS_DPAA_QBMAN 211 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); 212 #endif 213 214 #ifdef CONFIG_SYS_DPAA_PME 215 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); 216 #endif 217 218 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); 219 220 #ifdef CONFIG_FSL_CORENET 221 /* Display the RCW, so that no one gets confused as to what RCW 222 * we're actually using for this boot. 223 */ 224 puts("Reset Configuration Word (RCW):"); 225 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 226 u32 rcw = in_be32(&gur->rcwsr[i]); 227 228 if ((i % 4) == 0) 229 printf("\n %08x:", i * 4); 230 printf(" %08x", rcw); 231 } 232 puts("\n"); 233 #endif 234 235 return 0; 236 } 237 238 239 /* ------------------------------------------------------------------------- */ 240 241 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 242 { 243 /* Everything after the first generation of PQ3 parts has RSTCR */ 244 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 245 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 246 unsigned long val, msr; 247 248 /* 249 * Initiate hard reset in debug control register DBCR0 250 * Make sure MSR[DE] = 1. This only resets the core. 251 */ 252 msr = mfmsr (); 253 msr |= MSR_DE; 254 mtmsr (msr); 255 256 val = mfspr(DBCR0); 257 val |= 0x70000000; 258 mtspr(DBCR0,val); 259 #else 260 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 261 262 /* Attempt board-specific reset */ 263 board_reset(); 264 265 /* Next try asserting HRESET_REQ */ 266 out_be32(&gur->rstcr, 0x2); 267 udelay(100); 268 #endif 269 270 return 1; 271 } 272 273 274 /* 275 * Get timebase clock frequency 276 */ 277 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 278 #define CONFIG_SYS_FSL_TBCLK_DIV 8 279 #endif 280 __weak unsigned long get_tbclk (void) 281 { 282 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 283 284 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 285 } 286 287 288 #if defined(CONFIG_WATCHDOG) 289 void 290 reset_85xx_watchdog(void) 291 { 292 /* 293 * Clear TSR(WIS) bit by writing 1 294 */ 295 mtspr(SPRN_TSR, TSR_WIS); 296 } 297 298 void 299 watchdog_reset(void) 300 { 301 int re_enable = disable_interrupts(); 302 303 reset_85xx_watchdog(); 304 if (re_enable) 305 enable_interrupts(); 306 } 307 #endif /* CONFIG_WATCHDOG */ 308 309 /* 310 * Initializes on-chip MMC controllers. 311 * to override, implement board_mmc_init() 312 */ 313 int cpu_mmc_init(bd_t *bis) 314 { 315 #ifdef CONFIG_FSL_ESDHC 316 return fsl_esdhc_mmc_init(bis); 317 #else 318 return 0; 319 #endif 320 } 321 322 /* 323 * Print out the state of various machine registers. 324 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 325 * parameters for IFC and TLBs 326 */ 327 void mpc85xx_reginfo(void) 328 { 329 print_tlbcam(); 330 print_laws(); 331 #if defined(CONFIG_FSL_LBC) 332 print_lbc_regs(); 333 #endif 334 #ifdef CONFIG_FSL_IFC 335 print_ifc_regs(); 336 #endif 337 338 } 339 340 /* Common ddr init for non-corenet fsl 85xx platforms */ 341 #ifndef CONFIG_FSL_CORENET 342 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ 343 !defined(CONFIG_SYS_INIT_L2_ADDR) 344 phys_size_t initdram(int board_type) 345 { 346 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ 347 defined(CONFIG_QEMU_E500) 348 return fsl_ddr_sdram_size(); 349 #else 350 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 351 #endif 352 } 353 #else /* CONFIG_SYS_RAMBOOT */ 354 phys_size_t initdram(int board_type) 355 { 356 phys_size_t dram_size = 0; 357 358 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 359 { 360 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 361 unsigned int x = 10; 362 unsigned int i; 363 364 /* 365 * Work around to stabilize DDR DLL 366 */ 367 out_be32(&gur->ddrdllcr, 0x81000000); 368 asm("sync;isync;msync"); 369 udelay(200); 370 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 371 setbits_be32(&gur->devdisr, 0x00010000); 372 for (i = 0; i < x; i++) 373 ; 374 clrbits_be32(&gur->devdisr, 0x00010000); 375 x++; 376 } 377 } 378 #endif 379 380 #if defined(CONFIG_SPD_EEPROM) || \ 381 defined(CONFIG_DDR_SPD) || \ 382 defined(CONFIG_SYS_DDR_RAW_TIMING) 383 dram_size = fsl_ddr_sdram(); 384 #else 385 dram_size = fixed_sdram(); 386 #endif 387 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 388 dram_size *= 0x100000; 389 390 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 391 /* 392 * Initialize and enable DDR ECC. 393 */ 394 ddr_enable_ecc(dram_size); 395 #endif 396 397 #if defined(CONFIG_FSL_LBC) 398 /* Some boards also have sdram on the lbc */ 399 lbc_sdram_init(); 400 #endif 401 402 debug("DDR: "); 403 return dram_size; 404 } 405 #endif /* CONFIG_SYS_RAMBOOT */ 406 #endif 407 408 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 409 410 /* Board-specific functions defined in each board's ddr.c */ 411 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 412 unsigned int ctrl_num); 413 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 414 phys_addr_t *rpn); 415 unsigned int 416 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 417 418 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 419 420 static void dump_spd_ddr_reg(void) 421 { 422 int i, j, k, m; 423 u8 *p_8; 424 u32 *p_32; 425 struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 426 generic_spd_eeprom_t 427 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 428 429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 430 fsl_ddr_get_spd(spd[i], i); 431 432 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 433 puts("Byte (hex) "); 434 k = 1; 435 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 436 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 437 printf("Dimm%d ", k++); 438 } 439 puts("\n"); 440 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 441 m = 0; 442 printf("%3d (0x%02x) ", k, k); 443 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 444 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 445 p_8 = (u8 *) &spd[i][j]; 446 if (p_8[k]) { 447 printf("0x%02x ", p_8[k]); 448 m++; 449 } else 450 puts(" "); 451 } 452 } 453 if (m) 454 puts("\n"); 455 else 456 puts("\r"); 457 } 458 459 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 460 switch (i) { 461 case 0: 462 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; 463 break; 464 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 465 case 1: 466 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 467 break; 468 #endif 469 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 470 case 2: 471 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 472 break; 473 #endif 474 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 475 case 3: 476 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 477 break; 478 #endif 479 default: 480 printf("%s unexpected controller number = %u\n", 481 __func__, i); 482 return; 483 } 484 } 485 printf("DDR registers dump for all controllers " 486 "(zero vaule is omitted)...\n"); 487 puts("Offset (hex) "); 488 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 489 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 490 puts("\n"); 491 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { 492 m = 0; 493 printf("%6d (0x%04x)", k * 4, k * 4); 494 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 495 p_32 = (u32 *) ddr[i]; 496 if (p_32[k]) { 497 printf(" 0x%08x", p_32[k]); 498 m++; 499 } else 500 puts(" "); 501 } 502 if (m) 503 puts("\n"); 504 else 505 puts("\r"); 506 } 507 puts("\n"); 508 } 509 510 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 511 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 512 { 513 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 514 unsigned long epn; 515 u32 tsize, valid, ptr; 516 int ddr_esel; 517 518 clear_ddr_tlbs_phys(p_addr, size>>20); 519 520 /* Setup new tlb to cover the physical address */ 521 setup_ddr_tlbs_phys(p_addr, size>>20); 522 523 ptr = vstart; 524 ddr_esel = find_tlb_idx((void *)ptr, 1); 525 if (ddr_esel != -1) { 526 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 527 } else { 528 printf("TLB error in function %s\n", __func__); 529 return -1; 530 } 531 532 return 0; 533 } 534 535 /* 536 * slide the testing window up to test another area 537 * for 32_bit system, the maximum testable memory is limited to 538 * CONFIG_MAX_MEM_MAPPED 539 */ 540 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 541 { 542 phys_addr_t test_cap, p_addr; 543 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 544 545 #if !defined(CONFIG_PHYS_64BIT) || \ 546 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 547 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 548 test_cap = p_size; 549 #else 550 test_cap = gd->ram_size; 551 #endif 552 p_addr = (*vstart) + (*size) + (*phys_offset); 553 if (p_addr < test_cap - 1) { 554 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 555 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 556 return -1; 557 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 558 *size = (u32) p_size; 559 printf("Testing 0x%08llx - 0x%08llx\n", 560 (u64)(*vstart) + (*phys_offset), 561 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 562 } else 563 return 1; 564 565 return 0; 566 } 567 568 /* initialization for testing area */ 569 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 570 { 571 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 572 573 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 574 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 575 *phys_offset = 0; 576 577 #if !defined(CONFIG_PHYS_64BIT) || \ 578 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 579 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 580 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 581 puts("Cannot test more than "); 582 print_size(CONFIG_MAX_MEM_MAPPED, 583 " without proper 36BIT support.\n"); 584 } 585 #endif 586 printf("Testing 0x%08llx - 0x%08llx\n", 587 (u64)(*vstart) + (*phys_offset), 588 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 589 590 return 0; 591 } 592 593 /* invalid TLBs for DDR and remap as normal after testing */ 594 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 595 { 596 unsigned long epn; 597 u32 tsize, valid, ptr; 598 phys_addr_t rpn = 0; 599 int ddr_esel; 600 601 /* disable the TLBs for this testing */ 602 ptr = *vstart; 603 604 while (ptr < (*vstart) + (*size)) { 605 ddr_esel = find_tlb_idx((void *)ptr, 1); 606 if (ddr_esel != -1) { 607 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 608 disable_tlb(ddr_esel); 609 } 610 ptr += TSIZE_TO_BYTES(tsize); 611 } 612 613 puts("Remap DDR "); 614 setup_ddr_tlbs(gd->ram_size>>20); 615 puts("\n"); 616 617 return 0; 618 } 619 620 void arch_memory_failure_handle(void) 621 { 622 dump_spd_ddr_reg(); 623 } 624 #endif 625