1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu (void) 46 { 47 sys_info_t sysinfo; 48 uint pvr, svr; 49 uint fam; 50 uint ver; 51 uint major, minor; 52 struct cpu_type *cpu; 53 char buf1[32], buf2[32]; 54 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 55 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 56 #endif /* CONFIG_FSL_CORENET */ 57 #ifdef CONFIG_DDR_CLK_FREQ 58 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 59 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 60 #else 61 #ifdef CONFIG_FSL_CORENET 62 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 63 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 64 #else 65 u32 ddr_ratio = 0; 66 #endif /* CONFIG_FSL_CORENET */ 67 #endif /* CONFIG_DDR_CLK_FREQ */ 68 int i; 69 70 svr = get_svr(); 71 major = SVR_MAJ(svr); 72 #ifdef CONFIG_MPC8536 73 major &= 0x7; /* the msb of this nibble is a mfg code */ 74 #endif 75 minor = SVR_MIN(svr); 76 77 if (cpu_numcores() > 1) { 78 #ifndef CONFIG_MP 79 puts("Unicore software on multiprocessor system!!\n" 80 "To enable mutlticore build define CONFIG_MP\n"); 81 #endif 82 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 83 printf("CPU%d: ", pic->whoami); 84 } else { 85 puts("CPU: "); 86 } 87 88 cpu = gd->cpu; 89 90 puts(cpu->name); 91 if (IS_E_PROCESSOR(svr)) 92 puts("E"); 93 94 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 95 96 pvr = get_pvr(); 97 fam = PVR_FAM(pvr); 98 ver = PVR_VER(pvr); 99 major = PVR_MAJ(pvr); 100 minor = PVR_MIN(pvr); 101 102 printf("Core: "); 103 if (PVR_FAM(PVR_85xx)) { 104 switch(PVR_MEM(pvr)) { 105 case 0x1: 106 case 0x2: 107 puts("E500"); 108 break; 109 case 0x3: 110 puts("E500MC"); 111 break; 112 case 0x4: 113 puts("E5500"); 114 break; 115 default: 116 puts("Unknown"); 117 break; 118 } 119 } else { 120 puts("Unknown"); 121 } 122 123 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 124 125 get_sys_info(&sysinfo); 126 127 puts("Clock Configuration:"); 128 for (i = 0; i < cpu_numcores(); i++) { 129 if (!(i & 3)) 130 printf ("\n "); 131 printf("CPU%d:%-4s MHz, ", 132 i,strmhz(buf1, sysinfo.freqProcessor[i])); 133 } 134 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 135 136 #ifdef CONFIG_FSL_CORENET 137 if (ddr_sync == 1) { 138 printf(" DDR:%-4s MHz (%s MT/s data rate) " 139 "(Synchronous), ", 140 strmhz(buf1, sysinfo.freqDDRBus/2), 141 strmhz(buf2, sysinfo.freqDDRBus)); 142 } else { 143 printf(" DDR:%-4s MHz (%s MT/s data rate) " 144 "(Asynchronous), ", 145 strmhz(buf1, sysinfo.freqDDRBus/2), 146 strmhz(buf2, sysinfo.freqDDRBus)); 147 } 148 #else 149 switch (ddr_ratio) { 150 case 0x0: 151 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 152 strmhz(buf1, sysinfo.freqDDRBus/2), 153 strmhz(buf2, sysinfo.freqDDRBus)); 154 break; 155 case 0x7: 156 printf(" DDR:%-4s MHz (%s MT/s data rate) " 157 "(Synchronous), ", 158 strmhz(buf1, sysinfo.freqDDRBus/2), 159 strmhz(buf2, sysinfo.freqDDRBus)); 160 break; 161 default: 162 printf(" DDR:%-4s MHz (%s MT/s data rate) " 163 "(Asynchronous), ", 164 strmhz(buf1, sysinfo.freqDDRBus/2), 165 strmhz(buf2, sysinfo.freqDDRBus)); 166 break; 167 } 168 #endif 169 170 #if defined(CONFIG_FSL_LBC) 171 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 172 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 173 } else { 174 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 175 sysinfo.freqLocalBus); 176 } 177 #endif 178 179 #ifdef CONFIG_CPM2 180 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 181 #endif 182 183 #ifdef CONFIG_QE 184 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 185 #endif 186 187 #ifdef CONFIG_SYS_DPAA_FMAN 188 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 189 printf(" FMAN%d: %s MHz\n", i + 1, 190 strmhz(buf1, sysinfo.freqFMan[i])); 191 } 192 #endif 193 194 #ifdef CONFIG_SYS_DPAA_PME 195 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 196 #endif 197 198 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 199 200 return 0; 201 } 202 203 204 /* ------------------------------------------------------------------------- */ 205 206 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 207 { 208 /* Everything after the first generation of PQ3 parts has RSTCR */ 209 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 210 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 211 unsigned long val, msr; 212 213 /* 214 * Initiate hard reset in debug control register DBCR0 215 * Make sure MSR[DE] = 1. This only resets the core. 216 */ 217 msr = mfmsr (); 218 msr |= MSR_DE; 219 mtmsr (msr); 220 221 val = mfspr(DBCR0); 222 val |= 0x70000000; 223 mtspr(DBCR0,val); 224 #else 225 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 226 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 227 udelay(100); 228 #endif 229 230 return 1; 231 } 232 233 234 /* 235 * Get timebase clock frequency 236 */ 237 unsigned long get_tbclk (void) 238 { 239 #ifdef CONFIG_FSL_CORENET 240 return (gd->bus_clk + 8) / 16; 241 #else 242 return (gd->bus_clk + 4UL)/8UL; 243 #endif 244 } 245 246 247 #if defined(CONFIG_WATCHDOG) 248 void 249 watchdog_reset(void) 250 { 251 int re_enable = disable_interrupts(); 252 reset_85xx_watchdog(); 253 if (re_enable) enable_interrupts(); 254 } 255 256 void 257 reset_85xx_watchdog(void) 258 { 259 /* 260 * Clear TSR(WIS) bit by writing 1 261 */ 262 unsigned long val; 263 val = mfspr(SPRN_TSR); 264 val |= TSR_WIS; 265 mtspr(SPRN_TSR, val); 266 } 267 #endif /* CONFIG_WATCHDOG */ 268 269 /* 270 * Initializes on-chip MMC controllers. 271 * to override, implement board_mmc_init() 272 */ 273 int cpu_mmc_init(bd_t *bis) 274 { 275 #ifdef CONFIG_FSL_ESDHC 276 return fsl_esdhc_mmc_init(bis); 277 #else 278 return 0; 279 #endif 280 } 281 282 /* 283 * Print out the state of various machine registers. 284 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 285 * parameters for IFC and TLBs 286 */ 287 void mpc85xx_reginfo(void) 288 { 289 print_tlbcam(); 290 print_laws(); 291 #if defined(CONFIG_FSL_LBC) 292 print_lbc_regs(); 293 #endif 294 #ifdef CONFIG_FSL_IFC 295 print_ifc_regs(); 296 #endif 297 298 } 299 300 /* Common ddr init for non-corenet fsl 85xx platforms */ 301 #ifndef CONFIG_FSL_CORENET 302 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 303 phys_size_t initdram(int board_type) 304 { 305 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 306 return fsl_ddr_sdram_size(); 307 #else 308 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 309 #endif 310 } 311 #else /* CONFIG_SYS_RAMBOOT */ 312 phys_size_t initdram(int board_type) 313 { 314 phys_size_t dram_size = 0; 315 316 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 317 { 318 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 319 unsigned int x = 10; 320 unsigned int i; 321 322 /* 323 * Work around to stabilize DDR DLL 324 */ 325 out_be32(&gur->ddrdllcr, 0x81000000); 326 asm("sync;isync;msync"); 327 udelay(200); 328 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 329 setbits_be32(&gur->devdisr, 0x00010000); 330 for (i = 0; i < x; i++) 331 ; 332 clrbits_be32(&gur->devdisr, 0x00010000); 333 x++; 334 } 335 } 336 #endif 337 338 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 339 dram_size = fsl_ddr_sdram(); 340 #else 341 dram_size = fixed_sdram(); 342 #endif 343 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 344 dram_size *= 0x100000; 345 346 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 347 /* 348 * Initialize and enable DDR ECC. 349 */ 350 ddr_enable_ecc(dram_size); 351 #endif 352 353 #if defined(CONFIG_FSL_LBC) 354 /* Some boards also have sdram on the lbc */ 355 lbc_sdram_init(); 356 #endif 357 358 puts("DDR: "); 359 return dram_size; 360 } 361 #endif /* CONFIG_SYS_RAMBOOT */ 362 #endif 363 364 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 365 366 /* Board-specific functions defined in each board's ddr.c */ 367 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 368 unsigned int ctrl_num); 369 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 370 phys_addr_t *rpn); 371 unsigned int 372 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 373 374 static void dump_spd_ddr_reg(void) 375 { 376 int i, j, k, m; 377 u8 *p_8; 378 u32 *p_32; 379 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 380 generic_spd_eeprom_t 381 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 382 383 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 384 fsl_ddr_get_spd(spd[i], i); 385 386 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 387 puts("Byte (hex) "); 388 k = 1; 389 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 390 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 391 printf("Dimm%d ", k++); 392 } 393 puts("\n"); 394 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 395 m = 0; 396 printf("%3d (0x%02x) ", k, k); 397 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 398 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 399 p_8 = (u8 *) &spd[i][j]; 400 if (p_8[k]) { 401 printf("0x%02x ", p_8[k]); 402 m++; 403 } else 404 puts(" "); 405 } 406 } 407 if (m) 408 puts("\n"); 409 else 410 puts("\r"); 411 } 412 413 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 414 switch (i) { 415 case 0: 416 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 417 break; 418 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 419 case 1: 420 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 421 break; 422 #endif 423 default: 424 printf("%s unexpected controller number = %u\n", 425 __func__, i); 426 return; 427 } 428 } 429 printf("DDR registers dump for all controllers " 430 "(zero vaule is omitted)...\n"); 431 puts("Offset (hex) "); 432 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 433 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 434 puts("\n"); 435 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 436 m = 0; 437 printf("%6d (0x%04x)", k * 4, k * 4); 438 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 439 p_32 = (u32 *) ddr[i]; 440 if (p_32[k]) { 441 printf(" 0x%08x", p_32[k]); 442 m++; 443 } else 444 puts(" "); 445 } 446 if (m) 447 puts("\n"); 448 else 449 puts("\r"); 450 } 451 puts("\n"); 452 } 453 454 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 455 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 456 { 457 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 458 unsigned long epn; 459 u32 tsize, valid, ptr; 460 phys_addr_t rpn = 0; 461 int ddr_esel; 462 463 ptr = vstart; 464 465 while (ptr < (vstart + size)) { 466 ddr_esel = find_tlb_idx((void *)ptr, 1); 467 if (ddr_esel != -1) { 468 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 469 disable_tlb(ddr_esel); 470 } 471 ptr += TSIZE_TO_BYTES(tsize); 472 } 473 474 /* Setup new tlb to cover the physical address */ 475 setup_ddr_tlbs_phys(p_addr, size>>20); 476 477 ptr = vstart; 478 ddr_esel = find_tlb_idx((void *)ptr, 1); 479 if (ddr_esel != -1) { 480 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 481 } else { 482 printf("TLB error in function %s\n", __func__); 483 return -1; 484 } 485 486 return 0; 487 } 488 489 /* 490 * slide the testing window up to test another area 491 * for 32_bit system, the maximum testable memory is limited to 492 * CONFIG_MAX_MEM_MAPPED 493 */ 494 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 495 { 496 phys_addr_t test_cap, p_addr; 497 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 498 499 #if !defined(CONFIG_PHYS_64BIT) || \ 500 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 501 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 502 test_cap = p_size; 503 #else 504 test_cap = gd->ram_size; 505 #endif 506 p_addr = (*vstart) + (*size) + (*phys_offset); 507 if (p_addr < test_cap - 1) { 508 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 509 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 510 return -1; 511 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 512 *size = (u32) p_size; 513 printf("Testing 0x%08llx - 0x%08llx\n", 514 (u64)(*vstart) + (*phys_offset), 515 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 516 } else 517 return 1; 518 519 return 0; 520 } 521 522 /* initialization for testing area */ 523 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 524 { 525 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 526 527 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 528 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 529 *phys_offset = 0; 530 531 #if !defined(CONFIG_PHYS_64BIT) || \ 532 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 533 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 534 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 535 puts("Cannot test more than "); 536 print_size(CONFIG_MAX_MEM_MAPPED, 537 " without proper 36BIT support.\n"); 538 } 539 #endif 540 printf("Testing 0x%08llx - 0x%08llx\n", 541 (u64)(*vstart) + (*phys_offset), 542 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 543 544 return 0; 545 } 546 547 /* invalid TLBs for DDR and remap as normal after testing */ 548 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 549 { 550 unsigned long epn; 551 u32 tsize, valid, ptr; 552 phys_addr_t rpn = 0; 553 int ddr_esel; 554 555 /* disable the TLBs for this testing */ 556 ptr = *vstart; 557 558 while (ptr < (*vstart) + (*size)) { 559 ddr_esel = find_tlb_idx((void *)ptr, 1); 560 if (ddr_esel != -1) { 561 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 562 disable_tlb(ddr_esel); 563 } 564 ptr += TSIZE_TO_BYTES(tsize); 565 } 566 567 puts("Remap DDR "); 568 setup_ddr_tlbs(gd->ram_size>>20); 569 puts("\n"); 570 571 return 0; 572 } 573 574 void arch_memory_failure_handle(void) 575 { 576 dump_spd_ddr_reg(); 577 } 578 #endif 579