1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* 46 * Default board reset function 47 */ 48 static void 49 __board_reset(void) 50 { 51 /* Do nothing */ 52 } 53 void board_reset(void) __attribute__((weak, alias("__board_reset"))); 54 55 int checkcpu (void) 56 { 57 sys_info_t sysinfo; 58 uint pvr, svr; 59 uint ver; 60 uint major, minor; 61 struct cpu_type *cpu; 62 char buf1[32], buf2[32]; 63 #if (defined(CONFIG_DDR_CLK_FREQ) || \ 64 defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) 65 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 66 #endif /* CONFIG_FSL_CORENET */ 67 68 /* 69 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async 70 * mode. Previous platform use ddr ratio to do the same. This 71 * information is only for display here. 72 */ 73 #ifdef CONFIG_FSL_CORENET 74 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 75 u32 ddr_sync = 0; /* only async mode is supported */ 76 #else 77 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 78 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 79 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 80 #else /* CONFIG_FSL_CORENET */ 81 #ifdef CONFIG_DDR_CLK_FREQ 82 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 83 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 84 #else 85 u32 ddr_ratio = 0; 86 #endif /* CONFIG_DDR_CLK_FREQ */ 87 #endif /* CONFIG_FSL_CORENET */ 88 89 unsigned int i, core, nr_cores = cpu_numcores(); 90 u32 mask = cpu_mask(); 91 92 svr = get_svr(); 93 major = SVR_MAJ(svr); 94 minor = SVR_MIN(svr); 95 96 if (cpu_numcores() > 1) { 97 #ifndef CONFIG_MP 98 puts("Unicore software on multiprocessor system!!\n" 99 "To enable mutlticore build define CONFIG_MP\n"); 100 #endif 101 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 102 printf("CPU%d: ", pic->whoami); 103 } else { 104 puts("CPU: "); 105 } 106 107 cpu = gd->cpu; 108 109 puts(cpu->name); 110 if (IS_E_PROCESSOR(svr)) 111 puts("E"); 112 113 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 114 115 pvr = get_pvr(); 116 ver = PVR_VER(pvr); 117 major = PVR_MAJ(pvr); 118 minor = PVR_MIN(pvr); 119 120 printf("Core: "); 121 switch(ver) { 122 case PVR_VER_E500_V1: 123 case PVR_VER_E500_V2: 124 puts("E500"); 125 break; 126 case PVR_VER_E500MC: 127 puts("E500MC"); 128 break; 129 case PVR_VER_E5500: 130 puts("E5500"); 131 break; 132 case PVR_VER_E6500: 133 puts("E6500"); 134 break; 135 default: 136 puts("Unknown"); 137 break; 138 } 139 140 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 141 142 if (nr_cores > CONFIG_MAX_CPUS) { 143 panic("\nUnexpected number of cores: %d, max is %d\n", 144 nr_cores, CONFIG_MAX_CPUS); 145 } 146 147 get_sys_info(&sysinfo); 148 149 puts("Clock Configuration:"); 150 for_each_cpu(i, core, nr_cores, mask) { 151 if (!(i & 3)) 152 printf ("\n "); 153 printf("CPU%d:%-4s MHz, ", core, 154 strmhz(buf1, sysinfo.freqProcessor[core])); 155 } 156 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 157 158 #ifdef CONFIG_FSL_CORENET 159 if (ddr_sync == 1) { 160 printf(" DDR:%-4s MHz (%s MT/s data rate) " 161 "(Synchronous), ", 162 strmhz(buf1, sysinfo.freqDDRBus/2), 163 strmhz(buf2, sysinfo.freqDDRBus)); 164 } else { 165 printf(" DDR:%-4s MHz (%s MT/s data rate) " 166 "(Asynchronous), ", 167 strmhz(buf1, sysinfo.freqDDRBus/2), 168 strmhz(buf2, sysinfo.freqDDRBus)); 169 } 170 #else 171 switch (ddr_ratio) { 172 case 0x0: 173 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 174 strmhz(buf1, sysinfo.freqDDRBus/2), 175 strmhz(buf2, sysinfo.freqDDRBus)); 176 break; 177 case 0x7: 178 printf(" DDR:%-4s MHz (%s MT/s data rate) " 179 "(Synchronous), ", 180 strmhz(buf1, sysinfo.freqDDRBus/2), 181 strmhz(buf2, sysinfo.freqDDRBus)); 182 break; 183 default: 184 printf(" DDR:%-4s MHz (%s MT/s data rate) " 185 "(Asynchronous), ", 186 strmhz(buf1, sysinfo.freqDDRBus/2), 187 strmhz(buf2, sysinfo.freqDDRBus)); 188 break; 189 } 190 #endif 191 192 #if defined(CONFIG_FSL_LBC) 193 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 194 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 195 } else { 196 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 197 sysinfo.freqLocalBus); 198 } 199 #endif 200 201 #if defined(CONFIG_FSL_IFC) 202 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 203 #endif 204 205 #ifdef CONFIG_CPM2 206 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 207 #endif 208 209 #ifdef CONFIG_QE 210 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 211 #endif 212 213 #ifdef CONFIG_SYS_DPAA_FMAN 214 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 215 printf(" FMAN%d: %s MHz\n", i + 1, 216 strmhz(buf1, sysinfo.freqFMan[i])); 217 } 218 #endif 219 220 #ifdef CONFIG_SYS_DPAA_QBMAN 221 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); 222 #endif 223 224 #ifdef CONFIG_SYS_DPAA_PME 225 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 226 #endif 227 228 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 229 230 return 0; 231 } 232 233 234 /* ------------------------------------------------------------------------- */ 235 236 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 237 { 238 /* Everything after the first generation of PQ3 parts has RSTCR */ 239 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 240 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 241 unsigned long val, msr; 242 243 /* 244 * Initiate hard reset in debug control register DBCR0 245 * Make sure MSR[DE] = 1. This only resets the core. 246 */ 247 msr = mfmsr (); 248 msr |= MSR_DE; 249 mtmsr (msr); 250 251 val = mfspr(DBCR0); 252 val |= 0x70000000; 253 mtspr(DBCR0,val); 254 #else 255 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 256 257 /* Attempt board-specific reset */ 258 board_reset(); 259 260 /* Next try asserting HRESET_REQ */ 261 out_be32(&gur->rstcr, 0x2); 262 udelay(100); 263 #endif 264 265 return 1; 266 } 267 268 269 /* 270 * Get timebase clock frequency 271 */ 272 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 273 #define CONFIG_SYS_FSL_TBCLK_DIV 8 274 #endif 275 unsigned long get_tbclk (void) 276 { 277 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 278 279 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 280 } 281 282 283 #if defined(CONFIG_WATCHDOG) 284 void 285 watchdog_reset(void) 286 { 287 int re_enable = disable_interrupts(); 288 reset_85xx_watchdog(); 289 if (re_enable) enable_interrupts(); 290 } 291 292 void 293 reset_85xx_watchdog(void) 294 { 295 /* 296 * Clear TSR(WIS) bit by writing 1 297 */ 298 mtspr(SPRN_TSR, TSR_WIS); 299 } 300 #endif /* CONFIG_WATCHDOG */ 301 302 /* 303 * Initializes on-chip MMC controllers. 304 * to override, implement board_mmc_init() 305 */ 306 int cpu_mmc_init(bd_t *bis) 307 { 308 #ifdef CONFIG_FSL_ESDHC 309 return fsl_esdhc_mmc_init(bis); 310 #else 311 return 0; 312 #endif 313 } 314 315 /* 316 * Print out the state of various machine registers. 317 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 318 * parameters for IFC and TLBs 319 */ 320 void mpc85xx_reginfo(void) 321 { 322 print_tlbcam(); 323 print_laws(); 324 #if defined(CONFIG_FSL_LBC) 325 print_lbc_regs(); 326 #endif 327 #ifdef CONFIG_FSL_IFC 328 print_ifc_regs(); 329 #endif 330 331 } 332 333 /* Common ddr init for non-corenet fsl 85xx platforms */ 334 #ifndef CONFIG_FSL_CORENET 335 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 336 phys_size_t initdram(int board_type) 337 { 338 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 339 return fsl_ddr_sdram_size(); 340 #else 341 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 342 #endif 343 } 344 #else /* CONFIG_SYS_RAMBOOT */ 345 phys_size_t initdram(int board_type) 346 { 347 phys_size_t dram_size = 0; 348 349 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 350 { 351 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 352 unsigned int x = 10; 353 unsigned int i; 354 355 /* 356 * Work around to stabilize DDR DLL 357 */ 358 out_be32(&gur->ddrdllcr, 0x81000000); 359 asm("sync;isync;msync"); 360 udelay(200); 361 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 362 setbits_be32(&gur->devdisr, 0x00010000); 363 for (i = 0; i < x; i++) 364 ; 365 clrbits_be32(&gur->devdisr, 0x00010000); 366 x++; 367 } 368 } 369 #endif 370 371 #if defined(CONFIG_SPD_EEPROM) || \ 372 defined(CONFIG_DDR_SPD) || \ 373 defined(CONFIG_SYS_DDR_RAW_TIMING) 374 dram_size = fsl_ddr_sdram(); 375 #else 376 dram_size = fixed_sdram(); 377 #endif 378 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 379 dram_size *= 0x100000; 380 381 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 382 /* 383 * Initialize and enable DDR ECC. 384 */ 385 ddr_enable_ecc(dram_size); 386 #endif 387 388 #if defined(CONFIG_FSL_LBC) 389 /* Some boards also have sdram on the lbc */ 390 lbc_sdram_init(); 391 #endif 392 393 debug("DDR: "); 394 return dram_size; 395 } 396 #endif /* CONFIG_SYS_RAMBOOT */ 397 #endif 398 399 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 400 401 /* Board-specific functions defined in each board's ddr.c */ 402 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 403 unsigned int ctrl_num); 404 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 405 phys_addr_t *rpn); 406 unsigned int 407 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 408 409 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 410 411 static void dump_spd_ddr_reg(void) 412 { 413 int i, j, k, m; 414 u8 *p_8; 415 u32 *p_32; 416 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 417 generic_spd_eeprom_t 418 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 419 420 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 421 fsl_ddr_get_spd(spd[i], i); 422 423 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 424 puts("Byte (hex) "); 425 k = 1; 426 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 427 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 428 printf("Dimm%d ", k++); 429 } 430 puts("\n"); 431 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 432 m = 0; 433 printf("%3d (0x%02x) ", k, k); 434 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 435 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 436 p_8 = (u8 *) &spd[i][j]; 437 if (p_8[k]) { 438 printf("0x%02x ", p_8[k]); 439 m++; 440 } else 441 puts(" "); 442 } 443 } 444 if (m) 445 puts("\n"); 446 else 447 puts("\r"); 448 } 449 450 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 451 switch (i) { 452 case 0: 453 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 454 break; 455 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 456 case 1: 457 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 458 break; 459 #endif 460 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 461 case 2: 462 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; 463 break; 464 #endif 465 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 466 case 3: 467 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; 468 break; 469 #endif 470 default: 471 printf("%s unexpected controller number = %u\n", 472 __func__, i); 473 return; 474 } 475 } 476 printf("DDR registers dump for all controllers " 477 "(zero vaule is omitted)...\n"); 478 puts("Offset (hex) "); 479 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 480 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 481 puts("\n"); 482 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 483 m = 0; 484 printf("%6d (0x%04x)", k * 4, k * 4); 485 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 486 p_32 = (u32 *) ddr[i]; 487 if (p_32[k]) { 488 printf(" 0x%08x", p_32[k]); 489 m++; 490 } else 491 puts(" "); 492 } 493 if (m) 494 puts("\n"); 495 else 496 puts("\r"); 497 } 498 puts("\n"); 499 } 500 501 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 502 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 503 { 504 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 505 unsigned long epn; 506 u32 tsize, valid, ptr; 507 int ddr_esel; 508 509 clear_ddr_tlbs_phys(p_addr, size>>20); 510 511 /* Setup new tlb to cover the physical address */ 512 setup_ddr_tlbs_phys(p_addr, size>>20); 513 514 ptr = vstart; 515 ddr_esel = find_tlb_idx((void *)ptr, 1); 516 if (ddr_esel != -1) { 517 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 518 } else { 519 printf("TLB error in function %s\n", __func__); 520 return -1; 521 } 522 523 return 0; 524 } 525 526 /* 527 * slide the testing window up to test another area 528 * for 32_bit system, the maximum testable memory is limited to 529 * CONFIG_MAX_MEM_MAPPED 530 */ 531 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 532 { 533 phys_addr_t test_cap, p_addr; 534 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 535 536 #if !defined(CONFIG_PHYS_64BIT) || \ 537 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 538 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 539 test_cap = p_size; 540 #else 541 test_cap = gd->ram_size; 542 #endif 543 p_addr = (*vstart) + (*size) + (*phys_offset); 544 if (p_addr < test_cap - 1) { 545 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 546 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 547 return -1; 548 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 549 *size = (u32) p_size; 550 printf("Testing 0x%08llx - 0x%08llx\n", 551 (u64)(*vstart) + (*phys_offset), 552 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 553 } else 554 return 1; 555 556 return 0; 557 } 558 559 /* initialization for testing area */ 560 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 561 { 562 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 563 564 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 565 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 566 *phys_offset = 0; 567 568 #if !defined(CONFIG_PHYS_64BIT) || \ 569 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 570 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 571 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 572 puts("Cannot test more than "); 573 print_size(CONFIG_MAX_MEM_MAPPED, 574 " without proper 36BIT support.\n"); 575 } 576 #endif 577 printf("Testing 0x%08llx - 0x%08llx\n", 578 (u64)(*vstart) + (*phys_offset), 579 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 580 581 return 0; 582 } 583 584 /* invalid TLBs for DDR and remap as normal after testing */ 585 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 586 { 587 unsigned long epn; 588 u32 tsize, valid, ptr; 589 phys_addr_t rpn = 0; 590 int ddr_esel; 591 592 /* disable the TLBs for this testing */ 593 ptr = *vstart; 594 595 while (ptr < (*vstart) + (*size)) { 596 ddr_esel = find_tlb_idx((void *)ptr, 1); 597 if (ddr_esel != -1) { 598 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 599 disable_tlb(ddr_esel); 600 } 601 ptr += TSIZE_TO_BYTES(tsize); 602 } 603 604 puts("Remap DDR "); 605 setup_ddr_tlbs(gd->ram_size>>20); 606 puts("\n"); 607 608 return 0; 609 } 610 611 void arch_memory_failure_handle(void) 612 { 613 dump_spd_ddr_reg(); 614 } 615 #endif 616