1 /* 2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 #include <post.h> 38 #include <asm/processor.h> 39 #include <asm/fsl_ddr_sdram.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 int checkcpu (void) 44 { 45 sys_info_t sysinfo; 46 uint pvr, svr; 47 uint fam; 48 uint ver; 49 uint major, minor; 50 struct cpu_type *cpu; 51 char buf1[32], buf2[32]; 52 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 53 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 54 #endif /* CONFIG_FSL_CORENET */ 55 #ifdef CONFIG_DDR_CLK_FREQ 56 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 57 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 58 #else 59 #ifdef CONFIG_FSL_CORENET 60 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 61 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 62 #else 63 u32 ddr_ratio = 0; 64 #endif /* CONFIG_FSL_CORENET */ 65 #endif /* CONFIG_DDR_CLK_FREQ */ 66 int i; 67 68 svr = get_svr(); 69 major = SVR_MAJ(svr); 70 #ifdef CONFIG_MPC8536 71 major &= 0x7; /* the msb of this nibble is a mfg code */ 72 #endif 73 minor = SVR_MIN(svr); 74 75 if (cpu_numcores() > 1) { 76 #ifndef CONFIG_MP 77 puts("Unicore software on multiprocessor system!!\n" 78 "To enable mutlticore build define CONFIG_MP\n"); 79 #endif 80 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 81 printf("CPU%d: ", pic->whoami); 82 } else { 83 puts("CPU: "); 84 } 85 86 cpu = gd->cpu; 87 88 puts(cpu->name); 89 if (IS_E_PROCESSOR(svr)) 90 puts("E"); 91 92 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 93 94 pvr = get_pvr(); 95 fam = PVR_FAM(pvr); 96 ver = PVR_VER(pvr); 97 major = PVR_MAJ(pvr); 98 minor = PVR_MIN(pvr); 99 100 printf("Core: "); 101 if (PVR_FAM(PVR_85xx)) { 102 switch(PVR_MEM(pvr)) { 103 case 0x1: 104 case 0x2: 105 puts("E500"); 106 break; 107 case 0x3: 108 puts("E500MC"); 109 break; 110 case 0x4: 111 puts("E5500"); 112 break; 113 default: 114 puts("Unknown"); 115 break; 116 } 117 } else { 118 puts("Unknown"); 119 } 120 121 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 122 123 get_sys_info(&sysinfo); 124 125 puts("Clock Configuration:"); 126 for (i = 0; i < cpu_numcores(); i++) { 127 if (!(i & 3)) 128 printf ("\n "); 129 printf("CPU%d:%-4s MHz, ", 130 i,strmhz(buf1, sysinfo.freqProcessor[i])); 131 } 132 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 133 134 #ifdef CONFIG_FSL_CORENET 135 if (ddr_sync == 1) { 136 printf(" DDR:%-4s MHz (%s MT/s data rate) " 137 "(Synchronous), ", 138 strmhz(buf1, sysinfo.freqDDRBus/2), 139 strmhz(buf2, sysinfo.freqDDRBus)); 140 } else { 141 printf(" DDR:%-4s MHz (%s MT/s data rate) " 142 "(Asynchronous), ", 143 strmhz(buf1, sysinfo.freqDDRBus/2), 144 strmhz(buf2, sysinfo.freqDDRBus)); 145 } 146 #else 147 switch (ddr_ratio) { 148 case 0x0: 149 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 150 strmhz(buf1, sysinfo.freqDDRBus/2), 151 strmhz(buf2, sysinfo.freqDDRBus)); 152 break; 153 case 0x7: 154 printf(" DDR:%-4s MHz (%s MT/s data rate) " 155 "(Synchronous), ", 156 strmhz(buf1, sysinfo.freqDDRBus/2), 157 strmhz(buf2, sysinfo.freqDDRBus)); 158 break; 159 default: 160 printf(" DDR:%-4s MHz (%s MT/s data rate) " 161 "(Asynchronous), ", 162 strmhz(buf1, sysinfo.freqDDRBus/2), 163 strmhz(buf2, sysinfo.freqDDRBus)); 164 break; 165 } 166 #endif 167 168 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 169 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 170 } else { 171 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 172 sysinfo.freqLocalBus); 173 } 174 175 #ifdef CONFIG_CPM2 176 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 177 #endif 178 179 #ifdef CONFIG_QE 180 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 181 #endif 182 183 #ifdef CONFIG_SYS_DPAA_FMAN 184 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 185 printf(" FMAN%d: %s MHz\n", i + 1, 186 strmhz(buf1, sysinfo.freqFMan[i])); 187 } 188 #endif 189 190 #ifdef CONFIG_SYS_DPAA_PME 191 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 192 #endif 193 194 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 195 196 return 0; 197 } 198 199 200 /* ------------------------------------------------------------------------- */ 201 202 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) 203 { 204 /* Everything after the first generation of PQ3 parts has RSTCR */ 205 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 206 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 207 unsigned long val, msr; 208 209 /* 210 * Initiate hard reset in debug control register DBCR0 211 * Make sure MSR[DE] = 1. This only resets the core. 212 */ 213 msr = mfmsr (); 214 msr |= MSR_DE; 215 mtmsr (msr); 216 217 val = mfspr(DBCR0); 218 val |= 0x70000000; 219 mtspr(DBCR0,val); 220 #else 221 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 222 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 223 udelay(100); 224 #endif 225 226 return 1; 227 } 228 229 230 /* 231 * Get timebase clock frequency 232 */ 233 unsigned long get_tbclk (void) 234 { 235 #ifdef CONFIG_FSL_CORENET 236 return (gd->bus_clk + 8) / 16; 237 #else 238 return (gd->bus_clk + 4UL)/8UL; 239 #endif 240 } 241 242 243 #if defined(CONFIG_WATCHDOG) 244 void 245 watchdog_reset(void) 246 { 247 int re_enable = disable_interrupts(); 248 reset_85xx_watchdog(); 249 if (re_enable) enable_interrupts(); 250 } 251 252 void 253 reset_85xx_watchdog(void) 254 { 255 /* 256 * Clear TSR(WIS) bit by writing 1 257 */ 258 unsigned long val; 259 val = mfspr(SPRN_TSR); 260 val |= TSR_WIS; 261 mtspr(SPRN_TSR, val); 262 } 263 #endif /* CONFIG_WATCHDOG */ 264 265 /* 266 * Initializes on-chip MMC controllers. 267 * to override, implement board_mmc_init() 268 */ 269 int cpu_mmc_init(bd_t *bis) 270 { 271 #ifdef CONFIG_FSL_ESDHC 272 return fsl_esdhc_mmc_init(bis); 273 #else 274 return 0; 275 #endif 276 } 277 278 /* 279 * Print out the state of various machine registers. 280 * Currently prints out LAWs, BR0/OR0, and TLBs 281 */ 282 void mpc85xx_reginfo(void) 283 { 284 print_tlbcam(); 285 print_laws(); 286 print_lbc_regs(); 287 } 288 289 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 290 291 /* Board-specific functions defined in each board's ddr.c */ 292 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 293 unsigned int ctrl_num); 294 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 295 phys_addr_t *rpn); 296 unsigned int 297 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 298 299 static void dump_spd_ddr_reg(void) 300 { 301 int i, j, k, m; 302 u8 *p_8; 303 u32 *p_32; 304 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 305 generic_spd_eeprom_t 306 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 307 308 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 309 fsl_ddr_get_spd(spd[i], i); 310 311 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 312 puts("Byte (hex) "); 313 k = 1; 314 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 315 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 316 printf("Dimm%d ", k++); 317 } 318 puts("\n"); 319 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 320 m = 0; 321 printf("%3d (0x%02x) ", k, k); 322 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 323 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 324 p_8 = (u8 *) &spd[i][j]; 325 if (p_8[k]) { 326 printf("0x%02x ", p_8[k]); 327 m++; 328 } else 329 puts(" "); 330 } 331 } 332 if (m) 333 puts("\n"); 334 else 335 puts("\r"); 336 } 337 338 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 339 switch (i) { 340 case 0: 341 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 342 break; 343 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 344 case 1: 345 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 346 break; 347 #endif 348 default: 349 printf("%s unexpected controller number = %u\n", 350 __func__, i); 351 return; 352 } 353 } 354 printf("DDR registers dump for all controllers " 355 "(zero vaule is omitted)...\n"); 356 puts("Offset (hex) "); 357 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 358 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 359 puts("\n"); 360 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 361 m = 0; 362 printf("%6d (0x%04x)", k * 4, k * 4); 363 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 364 p_32 = (u32 *) ddr[i]; 365 if (p_32[k]) { 366 printf(" 0x%08x", p_32[k]); 367 m++; 368 } else 369 puts(" "); 370 } 371 if (m) 372 puts("\n"); 373 else 374 puts("\r"); 375 } 376 puts("\n"); 377 } 378 379 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 380 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 381 { 382 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 383 unsigned long epn; 384 u32 tsize, valid, ptr; 385 phys_addr_t rpn = 0; 386 int ddr_esel; 387 388 ptr = vstart; 389 390 while (ptr < (vstart + size)) { 391 ddr_esel = find_tlb_idx((void *)ptr, 1); 392 if (ddr_esel != -1) { 393 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 394 disable_tlb(ddr_esel); 395 } 396 ptr += TSIZE_TO_BYTES(tsize); 397 } 398 399 /* Setup new tlb to cover the physical address */ 400 setup_ddr_tlbs_phys(p_addr, size>>20); 401 402 ptr = vstart; 403 ddr_esel = find_tlb_idx((void *)ptr, 1); 404 if (ddr_esel != -1) { 405 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 406 } else { 407 printf("TLB error in function %s\n", __func__); 408 return -1; 409 } 410 411 return 0; 412 } 413 414 /* 415 * slide the testing window up to test another area 416 * for 32_bit system, the maximum testable memory is limited to 417 * CONFIG_MAX_MEM_MAPPED 418 */ 419 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 420 { 421 phys_addr_t test_cap, p_addr; 422 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 423 424 #if !defined(CONFIG_PHYS_64BIT) || \ 425 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 426 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 427 test_cap = p_size; 428 #else 429 test_cap = gd->ram_size; 430 #endif 431 p_addr = (*vstart) + (*size) + (*phys_offset); 432 if (p_addr < test_cap - 1) { 433 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 434 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 435 return -1; 436 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 437 *size = (u32) p_size; 438 printf("Testing 0x%08llx - 0x%08llx\n", 439 (u64)(*vstart) + (*phys_offset), 440 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 441 } else 442 return 1; 443 444 return 0; 445 } 446 447 /* initialization for testing area */ 448 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 449 { 450 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 451 452 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 453 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 454 *phys_offset = 0; 455 456 #if !defined(CONFIG_PHYS_64BIT) || \ 457 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 458 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 459 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 460 puts("Cannot test more than "); 461 print_size(CONFIG_MAX_MEM_MAPPED, 462 " without proper 36BIT support.\n"); 463 } 464 #endif 465 printf("Testing 0x%08llx - 0x%08llx\n", 466 (u64)(*vstart) + (*phys_offset), 467 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 468 469 return 0; 470 } 471 472 /* invalid TLBs for DDR and remap as normal after testing */ 473 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 474 { 475 unsigned long epn; 476 u32 tsize, valid, ptr; 477 phys_addr_t rpn = 0; 478 int ddr_esel; 479 480 /* disable the TLBs for this testing */ 481 ptr = *vstart; 482 483 while (ptr < (*vstart) + (*size)) { 484 ddr_esel = find_tlb_idx((void *)ptr, 1); 485 if (ddr_esel != -1) { 486 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 487 disable_tlb(ddr_esel); 488 } 489 ptr += TSIZE_TO_BYTES(tsize); 490 } 491 492 puts("Remap DDR "); 493 setup_ddr_tlbs(gd->ram_size>>20); 494 puts("\n"); 495 496 return 0; 497 } 498 499 void arch_memory_failure_handle(void) 500 { 501 dump_spd_ddr_reg(); 502 } 503 #endif 504