1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu (void) 46 { 47 sys_info_t sysinfo; 48 uint pvr, svr; 49 uint fam; 50 uint ver; 51 uint major, minor; 52 struct cpu_type *cpu; 53 char buf1[32], buf2[32]; 54 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 55 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 56 #endif /* CONFIG_FSL_CORENET */ 57 #ifdef CONFIG_DDR_CLK_FREQ 58 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 59 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 60 #else 61 #ifdef CONFIG_FSL_CORENET 62 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 63 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 64 #else 65 u32 ddr_ratio = 0; 66 #endif /* CONFIG_FSL_CORENET */ 67 #endif /* CONFIG_DDR_CLK_FREQ */ 68 int i; 69 70 svr = get_svr(); 71 major = SVR_MAJ(svr); 72 #ifdef CONFIG_MPC8536 73 major &= 0x7; /* the msb of this nibble is a mfg code */ 74 #endif 75 minor = SVR_MIN(svr); 76 77 if (cpu_numcores() > 1) { 78 #ifndef CONFIG_MP 79 puts("Unicore software on multiprocessor system!!\n" 80 "To enable mutlticore build define CONFIG_MP\n"); 81 #endif 82 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 83 printf("CPU%d: ", pic->whoami); 84 } else { 85 puts("CPU: "); 86 } 87 88 cpu = gd->cpu; 89 90 puts(cpu->name); 91 if (IS_E_PROCESSOR(svr)) 92 puts("E"); 93 94 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 95 96 pvr = get_pvr(); 97 fam = PVR_FAM(pvr); 98 ver = PVR_VER(pvr); 99 major = PVR_MAJ(pvr); 100 minor = PVR_MIN(pvr); 101 102 printf("Core: "); 103 if (PVR_FAM(PVR_85xx)) { 104 switch(PVR_MEM(pvr)) { 105 case 0x1: 106 case 0x2: 107 puts("E500"); 108 break; 109 case 0x3: 110 puts("E500MC"); 111 break; 112 case 0x4: 113 puts("E5500"); 114 break; 115 default: 116 puts("Unknown"); 117 break; 118 } 119 } else { 120 puts("Unknown"); 121 } 122 123 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 124 125 get_sys_info(&sysinfo); 126 127 puts("Clock Configuration:"); 128 for (i = 0; i < cpu_numcores(); i++) { 129 if (!(i & 3)) 130 printf ("\n "); 131 printf("CPU%d:%-4s MHz, ", 132 i,strmhz(buf1, sysinfo.freqProcessor[i])); 133 } 134 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 135 136 #ifdef CONFIG_FSL_CORENET 137 if (ddr_sync == 1) { 138 printf(" DDR:%-4s MHz (%s MT/s data rate) " 139 "(Synchronous), ", 140 strmhz(buf1, sysinfo.freqDDRBus/2), 141 strmhz(buf2, sysinfo.freqDDRBus)); 142 } else { 143 printf(" DDR:%-4s MHz (%s MT/s data rate) " 144 "(Asynchronous), ", 145 strmhz(buf1, sysinfo.freqDDRBus/2), 146 strmhz(buf2, sysinfo.freqDDRBus)); 147 } 148 #else 149 switch (ddr_ratio) { 150 case 0x0: 151 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 152 strmhz(buf1, sysinfo.freqDDRBus/2), 153 strmhz(buf2, sysinfo.freqDDRBus)); 154 break; 155 case 0x7: 156 printf(" DDR:%-4s MHz (%s MT/s data rate) " 157 "(Synchronous), ", 158 strmhz(buf1, sysinfo.freqDDRBus/2), 159 strmhz(buf2, sysinfo.freqDDRBus)); 160 break; 161 default: 162 printf(" DDR:%-4s MHz (%s MT/s data rate) " 163 "(Asynchronous), ", 164 strmhz(buf1, sysinfo.freqDDRBus/2), 165 strmhz(buf2, sysinfo.freqDDRBus)); 166 break; 167 } 168 #endif 169 170 #if defined(CONFIG_FSL_LBC) 171 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 172 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 173 } else { 174 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 175 sysinfo.freqLocalBus); 176 } 177 #endif 178 179 #ifdef CONFIG_CPM2 180 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 181 #endif 182 183 #ifdef CONFIG_QE 184 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 185 #endif 186 187 #ifdef CONFIG_SYS_DPAA_FMAN 188 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 189 printf(" FMAN%d: %s MHz\n", i + 1, 190 strmhz(buf1, sysinfo.freqFMan[i])); 191 } 192 #endif 193 194 #ifdef CONFIG_SYS_DPAA_PME 195 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 196 #endif 197 198 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 199 200 return 0; 201 } 202 203 204 /* ------------------------------------------------------------------------- */ 205 206 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 207 { 208 /* Everything after the first generation of PQ3 parts has RSTCR */ 209 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 210 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 211 unsigned long val, msr; 212 213 /* 214 * Initiate hard reset in debug control register DBCR0 215 * Make sure MSR[DE] = 1. This only resets the core. 216 */ 217 msr = mfmsr (); 218 msr |= MSR_DE; 219 mtmsr (msr); 220 221 val = mfspr(DBCR0); 222 val |= 0x70000000; 223 mtspr(DBCR0,val); 224 #else 225 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 226 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 227 udelay(100); 228 #endif 229 230 return 1; 231 } 232 233 234 /* 235 * Get timebase clock frequency 236 */ 237 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 238 #define CONFIG_SYS_FSL_TBCLK_DIV 8 239 #endif 240 unsigned long get_tbclk (void) 241 { 242 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 243 244 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 245 } 246 247 248 #if defined(CONFIG_WATCHDOG) 249 void 250 watchdog_reset(void) 251 { 252 int re_enable = disable_interrupts(); 253 reset_85xx_watchdog(); 254 if (re_enable) enable_interrupts(); 255 } 256 257 void 258 reset_85xx_watchdog(void) 259 { 260 /* 261 * Clear TSR(WIS) bit by writing 1 262 */ 263 unsigned long val; 264 val = mfspr(SPRN_TSR); 265 val |= TSR_WIS; 266 mtspr(SPRN_TSR, val); 267 } 268 #endif /* CONFIG_WATCHDOG */ 269 270 /* 271 * Initializes on-chip MMC controllers. 272 * to override, implement board_mmc_init() 273 */ 274 int cpu_mmc_init(bd_t *bis) 275 { 276 #ifdef CONFIG_FSL_ESDHC 277 return fsl_esdhc_mmc_init(bis); 278 #else 279 return 0; 280 #endif 281 } 282 283 /* 284 * Print out the state of various machine registers. 285 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 286 * parameters for IFC and TLBs 287 */ 288 void mpc85xx_reginfo(void) 289 { 290 print_tlbcam(); 291 print_laws(); 292 #if defined(CONFIG_FSL_LBC) 293 print_lbc_regs(); 294 #endif 295 #ifdef CONFIG_FSL_IFC 296 print_ifc_regs(); 297 #endif 298 299 } 300 301 /* Common ddr init for non-corenet fsl 85xx platforms */ 302 #ifndef CONFIG_FSL_CORENET 303 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 304 phys_size_t initdram(int board_type) 305 { 306 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 307 return fsl_ddr_sdram_size(); 308 #else 309 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 310 #endif 311 } 312 #else /* CONFIG_SYS_RAMBOOT */ 313 phys_size_t initdram(int board_type) 314 { 315 phys_size_t dram_size = 0; 316 317 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 318 { 319 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 320 unsigned int x = 10; 321 unsigned int i; 322 323 /* 324 * Work around to stabilize DDR DLL 325 */ 326 out_be32(&gur->ddrdllcr, 0x81000000); 327 asm("sync;isync;msync"); 328 udelay(200); 329 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 330 setbits_be32(&gur->devdisr, 0x00010000); 331 for (i = 0; i < x; i++) 332 ; 333 clrbits_be32(&gur->devdisr, 0x00010000); 334 x++; 335 } 336 } 337 #endif 338 339 #if defined(CONFIG_SPD_EEPROM) || \ 340 defined(CONFIG_DDR_SPD) || \ 341 defined(CONFIG_SYS_DDR_RAW_TIMING) 342 dram_size = fsl_ddr_sdram(); 343 #else 344 dram_size = fixed_sdram(); 345 #endif 346 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 347 dram_size *= 0x100000; 348 349 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 350 /* 351 * Initialize and enable DDR ECC. 352 */ 353 ddr_enable_ecc(dram_size); 354 #endif 355 356 #if defined(CONFIG_FSL_LBC) 357 /* Some boards also have sdram on the lbc */ 358 lbc_sdram_init(); 359 #endif 360 361 puts("DDR: "); 362 return dram_size; 363 } 364 #endif /* CONFIG_SYS_RAMBOOT */ 365 #endif 366 367 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 368 369 /* Board-specific functions defined in each board's ddr.c */ 370 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 371 unsigned int ctrl_num); 372 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 373 phys_addr_t *rpn); 374 unsigned int 375 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 376 377 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 378 379 static void dump_spd_ddr_reg(void) 380 { 381 int i, j, k, m; 382 u8 *p_8; 383 u32 *p_32; 384 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 385 generic_spd_eeprom_t 386 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 387 388 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 389 fsl_ddr_get_spd(spd[i], i); 390 391 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 392 puts("Byte (hex) "); 393 k = 1; 394 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 395 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 396 printf("Dimm%d ", k++); 397 } 398 puts("\n"); 399 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 400 m = 0; 401 printf("%3d (0x%02x) ", k, k); 402 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 403 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 404 p_8 = (u8 *) &spd[i][j]; 405 if (p_8[k]) { 406 printf("0x%02x ", p_8[k]); 407 m++; 408 } else 409 puts(" "); 410 } 411 } 412 if (m) 413 puts("\n"); 414 else 415 puts("\r"); 416 } 417 418 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 419 switch (i) { 420 case 0: 421 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 422 break; 423 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 424 case 1: 425 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 426 break; 427 #endif 428 default: 429 printf("%s unexpected controller number = %u\n", 430 __func__, i); 431 return; 432 } 433 } 434 printf("DDR registers dump for all controllers " 435 "(zero vaule is omitted)...\n"); 436 puts("Offset (hex) "); 437 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 438 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 439 puts("\n"); 440 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 441 m = 0; 442 printf("%6d (0x%04x)", k * 4, k * 4); 443 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 444 p_32 = (u32 *) ddr[i]; 445 if (p_32[k]) { 446 printf(" 0x%08x", p_32[k]); 447 m++; 448 } else 449 puts(" "); 450 } 451 if (m) 452 puts("\n"); 453 else 454 puts("\r"); 455 } 456 puts("\n"); 457 } 458 459 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 460 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 461 { 462 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 463 unsigned long epn; 464 u32 tsize, valid, ptr; 465 int ddr_esel; 466 467 clear_ddr_tlbs_phys(p_addr, size>>20); 468 469 /* Setup new tlb to cover the physical address */ 470 setup_ddr_tlbs_phys(p_addr, size>>20); 471 472 ptr = vstart; 473 ddr_esel = find_tlb_idx((void *)ptr, 1); 474 if (ddr_esel != -1) { 475 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 476 } else { 477 printf("TLB error in function %s\n", __func__); 478 return -1; 479 } 480 481 return 0; 482 } 483 484 /* 485 * slide the testing window up to test another area 486 * for 32_bit system, the maximum testable memory is limited to 487 * CONFIG_MAX_MEM_MAPPED 488 */ 489 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 490 { 491 phys_addr_t test_cap, p_addr; 492 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 493 494 #if !defined(CONFIG_PHYS_64BIT) || \ 495 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 496 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 497 test_cap = p_size; 498 #else 499 test_cap = gd->ram_size; 500 #endif 501 p_addr = (*vstart) + (*size) + (*phys_offset); 502 if (p_addr < test_cap - 1) { 503 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 504 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 505 return -1; 506 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 507 *size = (u32) p_size; 508 printf("Testing 0x%08llx - 0x%08llx\n", 509 (u64)(*vstart) + (*phys_offset), 510 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 511 } else 512 return 1; 513 514 return 0; 515 } 516 517 /* initialization for testing area */ 518 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 519 { 520 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 521 522 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 523 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 524 *phys_offset = 0; 525 526 #if !defined(CONFIG_PHYS_64BIT) || \ 527 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 528 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 529 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 530 puts("Cannot test more than "); 531 print_size(CONFIG_MAX_MEM_MAPPED, 532 " without proper 36BIT support.\n"); 533 } 534 #endif 535 printf("Testing 0x%08llx - 0x%08llx\n", 536 (u64)(*vstart) + (*phys_offset), 537 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 538 539 return 0; 540 } 541 542 /* invalid TLBs for DDR and remap as normal after testing */ 543 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 544 { 545 unsigned long epn; 546 u32 tsize, valid, ptr; 547 phys_addr_t rpn = 0; 548 int ddr_esel; 549 550 /* disable the TLBs for this testing */ 551 ptr = *vstart; 552 553 while (ptr < (*vstart) + (*size)) { 554 ddr_esel = find_tlb_idx((void *)ptr, 1); 555 if (ddr_esel != -1) { 556 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 557 disable_tlb(ddr_esel); 558 } 559 ptr += TSIZE_TO_BYTES(tsize); 560 } 561 562 puts("Remap DDR "); 563 setup_ddr_tlbs(gd->ram_size>>20); 564 puts("\n"); 565 566 return 0; 567 } 568 569 void arch_memory_failure_handle(void) 570 { 571 dump_spd_ddr_reg(); 572 } 573 #endif 574