1 /* 2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 int checkcpu (void) 39 { 40 sys_info_t sysinfo; 41 uint pvr, svr; 42 uint fam; 43 uint ver; 44 uint major, minor; 45 struct cpu_type *cpu; 46 char buf1[32], buf2[32]; 47 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49 #endif /* CONFIG_FSL_CORENET */ 50 #ifdef CONFIG_DDR_CLK_FREQ 51 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 52 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 53 #else 54 #ifdef CONFIG_FSL_CORENET 55 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 56 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 57 #else 58 u32 ddr_ratio = 0; 59 #endif /* CONFIG_FSL_CORENET */ 60 #endif /* CONFIG_DDR_CLK_FREQ */ 61 int i; 62 63 svr = get_svr(); 64 major = SVR_MAJ(svr); 65 #ifdef CONFIG_MPC8536 66 major &= 0x7; /* the msb of this nibble is a mfg code */ 67 #endif 68 minor = SVR_MIN(svr); 69 70 if (cpu_numcores() > 1) { 71 #ifndef CONFIG_MP 72 puts("Unicore software on multiprocessor system!!\n" 73 "To enable mutlticore build define CONFIG_MP\n"); 74 #endif 75 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); 76 printf("CPU%d: ", pic->whoami); 77 } else { 78 puts("CPU: "); 79 } 80 81 cpu = gd->cpu; 82 83 puts(cpu->name); 84 if (IS_E_PROCESSOR(svr)) 85 puts("E"); 86 87 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 88 89 pvr = get_pvr(); 90 fam = PVR_FAM(pvr); 91 ver = PVR_VER(pvr); 92 major = PVR_MAJ(pvr); 93 minor = PVR_MIN(pvr); 94 95 printf("Core: "); 96 switch (fam) { 97 case PVR_FAM(PVR_85xx): 98 puts("E500"); 99 break; 100 default: 101 puts("Unknown"); 102 break; 103 } 104 105 if (PVR_MEM(pvr) == 0x03) 106 puts("MC"); 107 108 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 109 110 get_sys_info(&sysinfo); 111 112 puts("Clock Configuration:"); 113 for (i = 0; i < cpu_numcores(); i++) { 114 if (!(i & 3)) 115 printf ("\n "); 116 printf("CPU%d:%-4s MHz, ", 117 i,strmhz(buf1, sysinfo.freqProcessor[i])); 118 } 119 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 120 121 #ifdef CONFIG_FSL_CORENET 122 if (ddr_sync == 1) { 123 printf(" DDR:%-4s MHz (%s MT/s data rate) " 124 "(Synchronous), ", 125 strmhz(buf1, sysinfo.freqDDRBus/2), 126 strmhz(buf2, sysinfo.freqDDRBus)); 127 } else { 128 printf(" DDR:%-4s MHz (%s MT/s data rate) " 129 "(Asynchronous), ", 130 strmhz(buf1, sysinfo.freqDDRBus/2), 131 strmhz(buf2, sysinfo.freqDDRBus)); 132 } 133 #else 134 switch (ddr_ratio) { 135 case 0x0: 136 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 137 strmhz(buf1, sysinfo.freqDDRBus/2), 138 strmhz(buf2, sysinfo.freqDDRBus)); 139 break; 140 case 0x7: 141 printf(" DDR:%-4s MHz (%s MT/s data rate) " 142 "(Synchronous), ", 143 strmhz(buf1, sysinfo.freqDDRBus/2), 144 strmhz(buf2, sysinfo.freqDDRBus)); 145 break; 146 default: 147 printf(" DDR:%-4s MHz (%s MT/s data rate) " 148 "(Asynchronous), ", 149 strmhz(buf1, sysinfo.freqDDRBus/2), 150 strmhz(buf2, sysinfo.freqDDRBus)); 151 break; 152 } 153 #endif 154 155 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 156 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 157 } else { 158 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 159 sysinfo.freqLocalBus); 160 } 161 162 #ifdef CONFIG_CPM2 163 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 164 #endif 165 166 #ifdef CONFIG_QE 167 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 168 #endif 169 170 #ifdef CONFIG_SYS_DPAA_FMAN 171 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 172 printf(" FMAN%d: %s MHz\n", i, 173 strmhz(buf1, sysinfo.freqFMan[i])); 174 } 175 #endif 176 177 #ifdef CONFIG_SYS_DPAA_PME 178 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 179 #endif 180 181 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 182 183 return 0; 184 } 185 186 187 /* ------------------------------------------------------------------------- */ 188 189 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) 190 { 191 /* Everything after the first generation of PQ3 parts has RSTCR */ 192 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 193 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 194 unsigned long val, msr; 195 196 /* 197 * Initiate hard reset in debug control register DBCR0 198 * Make sure MSR[DE] = 1. This only resets the core. 199 */ 200 msr = mfmsr (); 201 msr |= MSR_DE; 202 mtmsr (msr); 203 204 val = mfspr(DBCR0); 205 val |= 0x70000000; 206 mtspr(DBCR0,val); 207 #else 208 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 209 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 210 udelay(100); 211 #endif 212 213 return 1; 214 } 215 216 217 /* 218 * Get timebase clock frequency 219 */ 220 unsigned long get_tbclk (void) 221 { 222 #ifdef CONFIG_FSL_CORENET 223 return (gd->bus_clk + 8) / 16; 224 #else 225 return (gd->bus_clk + 4UL)/8UL; 226 #endif 227 } 228 229 230 #if defined(CONFIG_WATCHDOG) 231 void 232 watchdog_reset(void) 233 { 234 int re_enable = disable_interrupts(); 235 reset_85xx_watchdog(); 236 if (re_enable) enable_interrupts(); 237 } 238 239 void 240 reset_85xx_watchdog(void) 241 { 242 /* 243 * Clear TSR(WIS) bit by writing 1 244 */ 245 unsigned long val; 246 val = mfspr(SPRN_TSR); 247 val |= TSR_WIS; 248 mtspr(SPRN_TSR, val); 249 } 250 #endif /* CONFIG_WATCHDOG */ 251 252 /* 253 * Configures a UPM. The function requires the respective MxMR to be set 254 * before calling this function. "size" is the number or entries, not a sizeof. 255 */ 256 void upmconfig (uint upm, uint * table, uint size) 257 { 258 int i, mdr, mad, old_mad = 0; 259 volatile u32 *mxmr; 260 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); 261 volatile u32 *brp,*orp; 262 volatile u8* dummy = NULL; 263 int upmmask; 264 265 switch (upm) { 266 case UPMA: 267 mxmr = &lbc->mamr; 268 upmmask = BR_MS_UPMA; 269 break; 270 case UPMB: 271 mxmr = &lbc->mbmr; 272 upmmask = BR_MS_UPMB; 273 break; 274 case UPMC: 275 mxmr = &lbc->mcmr; 276 upmmask = BR_MS_UPMC; 277 break; 278 default: 279 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); 280 hang(); 281 } 282 283 /* Find the address for the dummy write transaction */ 284 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; 285 i++, brp += 2, orp += 2) { 286 287 /* Look for a valid BR with selected UPM */ 288 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { 289 dummy = (volatile u8*)(in_be32(brp) & BR_BA); 290 break; 291 } 292 } 293 294 if (i == 8) { 295 printf("Error: %s() could not find matching BR\n", __FUNCTION__); 296 hang(); 297 } 298 299 for (i = 0; i < size; i++) { 300 /* 1 */ 301 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); 302 /* 2 */ 303 out_be32(&lbc->mdr, table[i]); 304 /* 3 */ 305 mdr = in_be32(&lbc->mdr); 306 /* 4 */ 307 *(volatile u8 *)dummy = 0; 308 /* 5 */ 309 do { 310 mad = in_be32(mxmr) & MxMR_MAD_MSK; 311 } while (mad <= old_mad && !(!mad && i == (size-1))); 312 old_mad = mad; 313 } 314 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); 315 } 316 317 /* 318 * Initializes on-chip MMC controllers. 319 * to override, implement board_mmc_init() 320 */ 321 int cpu_mmc_init(bd_t *bis) 322 { 323 #ifdef CONFIG_FSL_ESDHC 324 return fsl_esdhc_mmc_init(bis); 325 #else 326 return 0; 327 #endif 328 } 329