1 /* 2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_ifc.h> 37 #include <asm/fsl_law.h> 38 #include <asm/fsl_lbc.h> 39 #include <post.h> 40 #include <asm/processor.h> 41 #include <asm/fsl_ddr_sdram.h> 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 int checkcpu (void) 46 { 47 sys_info_t sysinfo; 48 uint pvr, svr; 49 uint ver; 50 uint major, minor; 51 struct cpu_type *cpu; 52 char buf1[32], buf2[32]; 53 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 54 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 55 #endif /* CONFIG_FSL_CORENET */ 56 #ifdef CONFIG_DDR_CLK_FREQ 57 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 58 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 59 #else 60 #ifdef CONFIG_FSL_CORENET 61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 63 #else 64 u32 ddr_ratio = 0; 65 #endif /* CONFIG_FSL_CORENET */ 66 #endif /* CONFIG_DDR_CLK_FREQ */ 67 unsigned int i, core, nr_cores = cpu_numcores(); 68 u32 mask = cpu_mask(); 69 70 svr = get_svr(); 71 major = SVR_MAJ(svr); 72 minor = SVR_MIN(svr); 73 74 if (cpu_numcores() > 1) { 75 #ifndef CONFIG_MP 76 puts("Unicore software on multiprocessor system!!\n" 77 "To enable mutlticore build define CONFIG_MP\n"); 78 #endif 79 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 80 printf("CPU%d: ", pic->whoami); 81 } else { 82 puts("CPU: "); 83 } 84 85 cpu = gd->cpu; 86 87 puts(cpu->name); 88 if (IS_E_PROCESSOR(svr)) 89 puts("E"); 90 91 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 92 93 pvr = get_pvr(); 94 ver = PVR_VER(pvr); 95 major = PVR_MAJ(pvr); 96 minor = PVR_MIN(pvr); 97 98 printf("Core: "); 99 switch(ver) { 100 case PVR_VER_E500_V1: 101 case PVR_VER_E500_V2: 102 puts("E500"); 103 break; 104 case PVR_VER_E500MC: 105 puts("E500MC"); 106 break; 107 case PVR_VER_E5500: 108 puts("E5500"); 109 break; 110 default: 111 puts("Unknown"); 112 break; 113 } 114 115 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 116 117 get_sys_info(&sysinfo); 118 119 puts("Clock Configuration:"); 120 for_each_cpu(i, core, nr_cores, mask) { 121 if (!(i & 3)) 122 printf ("\n "); 123 printf("CPU%d:%-4s MHz, ", core, 124 strmhz(buf1, sysinfo.freqProcessor[core])); 125 } 126 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 127 128 #ifdef CONFIG_FSL_CORENET 129 if (ddr_sync == 1) { 130 printf(" DDR:%-4s MHz (%s MT/s data rate) " 131 "(Synchronous), ", 132 strmhz(buf1, sysinfo.freqDDRBus/2), 133 strmhz(buf2, sysinfo.freqDDRBus)); 134 } else { 135 printf(" DDR:%-4s MHz (%s MT/s data rate) " 136 "(Asynchronous), ", 137 strmhz(buf1, sysinfo.freqDDRBus/2), 138 strmhz(buf2, sysinfo.freqDDRBus)); 139 } 140 #else 141 switch (ddr_ratio) { 142 case 0x0: 143 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 144 strmhz(buf1, sysinfo.freqDDRBus/2), 145 strmhz(buf2, sysinfo.freqDDRBus)); 146 break; 147 case 0x7: 148 printf(" DDR:%-4s MHz (%s MT/s data rate) " 149 "(Synchronous), ", 150 strmhz(buf1, sysinfo.freqDDRBus/2), 151 strmhz(buf2, sysinfo.freqDDRBus)); 152 break; 153 default: 154 printf(" DDR:%-4s MHz (%s MT/s data rate) " 155 "(Asynchronous), ", 156 strmhz(buf1, sysinfo.freqDDRBus/2), 157 strmhz(buf2, sysinfo.freqDDRBus)); 158 break; 159 } 160 #endif 161 162 #if defined(CONFIG_FSL_LBC) 163 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 164 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 165 } else { 166 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 167 sysinfo.freqLocalBus); 168 } 169 #endif 170 171 #ifdef CONFIG_CPM2 172 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 173 #endif 174 175 #ifdef CONFIG_QE 176 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 177 #endif 178 179 #ifdef CONFIG_SYS_DPAA_FMAN 180 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 181 printf(" FMAN%d: %s MHz\n", i + 1, 182 strmhz(buf1, sysinfo.freqFMan[i])); 183 } 184 #endif 185 186 #ifdef CONFIG_SYS_DPAA_PME 187 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 188 #endif 189 190 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 191 192 return 0; 193 } 194 195 196 /* ------------------------------------------------------------------------- */ 197 198 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 199 { 200 /* Everything after the first generation of PQ3 parts has RSTCR */ 201 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 202 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 203 unsigned long val, msr; 204 205 /* 206 * Initiate hard reset in debug control register DBCR0 207 * Make sure MSR[DE] = 1. This only resets the core. 208 */ 209 msr = mfmsr (); 210 msr |= MSR_DE; 211 mtmsr (msr); 212 213 val = mfspr(DBCR0); 214 val |= 0x70000000; 215 mtspr(DBCR0,val); 216 #else 217 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 218 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 219 udelay(100); 220 #endif 221 222 return 1; 223 } 224 225 226 /* 227 * Get timebase clock frequency 228 */ 229 #ifndef CONFIG_SYS_FSL_TBCLK_DIV 230 #define CONFIG_SYS_FSL_TBCLK_DIV 8 231 #endif 232 unsigned long get_tbclk (void) 233 { 234 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; 235 236 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; 237 } 238 239 240 #if defined(CONFIG_WATCHDOG) 241 void 242 watchdog_reset(void) 243 { 244 int re_enable = disable_interrupts(); 245 reset_85xx_watchdog(); 246 if (re_enable) enable_interrupts(); 247 } 248 249 void 250 reset_85xx_watchdog(void) 251 { 252 /* 253 * Clear TSR(WIS) bit by writing 1 254 */ 255 unsigned long val; 256 val = mfspr(SPRN_TSR); 257 val |= TSR_WIS; 258 mtspr(SPRN_TSR, val); 259 } 260 #endif /* CONFIG_WATCHDOG */ 261 262 /* 263 * Initializes on-chip MMC controllers. 264 * to override, implement board_mmc_init() 265 */ 266 int cpu_mmc_init(bd_t *bis) 267 { 268 #ifdef CONFIG_FSL_ESDHC 269 return fsl_esdhc_mmc_init(bis); 270 #else 271 return 0; 272 #endif 273 } 274 275 /* 276 * Print out the state of various machine registers. 277 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing 278 * parameters for IFC and TLBs 279 */ 280 void mpc85xx_reginfo(void) 281 { 282 print_tlbcam(); 283 print_laws(); 284 #if defined(CONFIG_FSL_LBC) 285 print_lbc_regs(); 286 #endif 287 #ifdef CONFIG_FSL_IFC 288 print_ifc_regs(); 289 #endif 290 291 } 292 293 /* Common ddr init for non-corenet fsl 85xx platforms */ 294 #ifndef CONFIG_FSL_CORENET 295 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) 296 phys_size_t initdram(int board_type) 297 { 298 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) 299 return fsl_ddr_sdram_size(); 300 #else 301 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 302 #endif 303 } 304 #else /* CONFIG_SYS_RAMBOOT */ 305 phys_size_t initdram(int board_type) 306 { 307 phys_size_t dram_size = 0; 308 309 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 310 { 311 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 312 unsigned int x = 10; 313 unsigned int i; 314 315 /* 316 * Work around to stabilize DDR DLL 317 */ 318 out_be32(&gur->ddrdllcr, 0x81000000); 319 asm("sync;isync;msync"); 320 udelay(200); 321 while (in_be32(&gur->ddrdllcr) != 0x81000100) { 322 setbits_be32(&gur->devdisr, 0x00010000); 323 for (i = 0; i < x; i++) 324 ; 325 clrbits_be32(&gur->devdisr, 0x00010000); 326 x++; 327 } 328 } 329 #endif 330 331 #if defined(CONFIG_SPD_EEPROM) || \ 332 defined(CONFIG_DDR_SPD) || \ 333 defined(CONFIG_SYS_DDR_RAW_TIMING) 334 dram_size = fsl_ddr_sdram(); 335 #else 336 dram_size = fixed_sdram(); 337 #endif 338 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 339 dram_size *= 0x100000; 340 341 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 342 /* 343 * Initialize and enable DDR ECC. 344 */ 345 ddr_enable_ecc(dram_size); 346 #endif 347 348 #if defined(CONFIG_FSL_LBC) 349 /* Some boards also have sdram on the lbc */ 350 lbc_sdram_init(); 351 #endif 352 353 debug("DDR: "); 354 return dram_size; 355 } 356 #endif /* CONFIG_SYS_RAMBOOT */ 357 #endif 358 359 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY 360 361 /* Board-specific functions defined in each board's ddr.c */ 362 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 363 unsigned int ctrl_num); 364 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, 365 phys_addr_t *rpn); 366 unsigned int 367 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 368 369 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); 370 371 static void dump_spd_ddr_reg(void) 372 { 373 int i, j, k, m; 374 u8 *p_8; 375 u32 *p_32; 376 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; 377 generic_spd_eeprom_t 378 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; 379 380 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 381 fsl_ddr_get_spd(spd[i], i); 382 383 puts("SPD data of all dimms (zero vaule is omitted)...\n"); 384 puts("Byte (hex) "); 385 k = 1; 386 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 387 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) 388 printf("Dimm%d ", k++); 389 } 390 puts("\n"); 391 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { 392 m = 0; 393 printf("%3d (0x%02x) ", k, k); 394 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 395 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 396 p_8 = (u8 *) &spd[i][j]; 397 if (p_8[k]) { 398 printf("0x%02x ", p_8[k]); 399 m++; 400 } else 401 puts(" "); 402 } 403 } 404 if (m) 405 puts("\n"); 406 else 407 puts("\r"); 408 } 409 410 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 411 switch (i) { 412 case 0: 413 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; 414 break; 415 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR 416 case 1: 417 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; 418 break; 419 #endif 420 default: 421 printf("%s unexpected controller number = %u\n", 422 __func__, i); 423 return; 424 } 425 } 426 printf("DDR registers dump for all controllers " 427 "(zero vaule is omitted)...\n"); 428 puts("Offset (hex) "); 429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 430 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); 431 puts("\n"); 432 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { 433 m = 0; 434 printf("%6d (0x%04x)", k * 4, k * 4); 435 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 436 p_32 = (u32 *) ddr[i]; 437 if (p_32[k]) { 438 printf(" 0x%08x", p_32[k]); 439 m++; 440 } else 441 puts(" "); 442 } 443 if (m) 444 puts("\n"); 445 else 446 puts("\r"); 447 } 448 puts("\n"); 449 } 450 451 /* invalid the TLBs for DDR and setup new ones to cover p_addr */ 452 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) 453 { 454 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; 455 unsigned long epn; 456 u32 tsize, valid, ptr; 457 int ddr_esel; 458 459 clear_ddr_tlbs_phys(p_addr, size>>20); 460 461 /* Setup new tlb to cover the physical address */ 462 setup_ddr_tlbs_phys(p_addr, size>>20); 463 464 ptr = vstart; 465 ddr_esel = find_tlb_idx((void *)ptr, 1); 466 if (ddr_esel != -1) { 467 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); 468 } else { 469 printf("TLB error in function %s\n", __func__); 470 return -1; 471 } 472 473 return 0; 474 } 475 476 /* 477 * slide the testing window up to test another area 478 * for 32_bit system, the maximum testable memory is limited to 479 * CONFIG_MAX_MEM_MAPPED 480 */ 481 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 482 { 483 phys_addr_t test_cap, p_addr; 484 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 485 486 #if !defined(CONFIG_PHYS_64BIT) || \ 487 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 488 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 489 test_cap = p_size; 490 #else 491 test_cap = gd->ram_size; 492 #endif 493 p_addr = (*vstart) + (*size) + (*phys_offset); 494 if (p_addr < test_cap - 1) { 495 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); 496 if (reset_tlb(p_addr, p_size, phys_offset) == -1) 497 return -1; 498 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 499 *size = (u32) p_size; 500 printf("Testing 0x%08llx - 0x%08llx\n", 501 (u64)(*vstart) + (*phys_offset), 502 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 503 } else 504 return 1; 505 506 return 0; 507 } 508 509 /* initialization for testing area */ 510 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 511 { 512 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); 513 514 *vstart = CONFIG_SYS_DDR_SDRAM_BASE; 515 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ 516 *phys_offset = 0; 517 518 #if !defined(CONFIG_PHYS_64BIT) || \ 519 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ 520 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) 521 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { 522 puts("Cannot test more than "); 523 print_size(CONFIG_MAX_MEM_MAPPED, 524 " without proper 36BIT support.\n"); 525 } 526 #endif 527 printf("Testing 0x%08llx - 0x%08llx\n", 528 (u64)(*vstart) + (*phys_offset), 529 (u64)(*vstart) + (*phys_offset) + (*size) - 1); 530 531 return 0; 532 } 533 534 /* invalid TLBs for DDR and remap as normal after testing */ 535 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 536 { 537 unsigned long epn; 538 u32 tsize, valid, ptr; 539 phys_addr_t rpn = 0; 540 int ddr_esel; 541 542 /* disable the TLBs for this testing */ 543 ptr = *vstart; 544 545 while (ptr < (*vstart) + (*size)) { 546 ddr_esel = find_tlb_idx((void *)ptr, 1); 547 if (ddr_esel != -1) { 548 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); 549 disable_tlb(ddr_esel); 550 } 551 ptr += TSIZE_TO_BYTES(tsize); 552 } 553 554 puts("Remap DDR "); 555 setup_ddr_tlbs(gd->ram_size>>20); 556 puts("\n"); 557 558 return 0; 559 } 560 561 void arch_memory_failure_handle(void) 562 { 563 dump_spd_ddr_reg(); 564 } 565 #endif 566