1 /* 2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. 3 * (C) Copyright 2002, 2003 Motorola Inc. 4 * Xianghua Xiao (X.Xiao@motorola.com) 5 * 6 * (C) Copyright 2000 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <config.h> 29 #include <common.h> 30 #include <watchdog.h> 31 #include <command.h> 32 #include <fsl_esdhc.h> 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/mmu.h> 36 #include <asm/fsl_law.h> 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 int checkcpu (void) 41 { 42 sys_info_t sysinfo; 43 uint pvr, svr; 44 uint fam; 45 uint ver; 46 uint major, minor; 47 struct cpu_type *cpu; 48 char buf1[32], buf2[32]; 49 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 #endif /* CONFIG_FSL_CORENET */ 52 #ifdef CONFIG_DDR_CLK_FREQ 53 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) 54 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 55 #else 56 #ifdef CONFIG_FSL_CORENET 57 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) 58 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; 59 #else 60 u32 ddr_ratio = 0; 61 #endif /* CONFIG_FSL_CORENET */ 62 #endif /* CONFIG_DDR_CLK_FREQ */ 63 int i; 64 65 svr = get_svr(); 66 major = SVR_MAJ(svr); 67 #ifdef CONFIG_MPC8536 68 major &= 0x7; /* the msb of this nibble is a mfg code */ 69 #endif 70 minor = SVR_MIN(svr); 71 72 if (cpu_numcores() > 1) { 73 #ifndef CONFIG_MP 74 puts("Unicore software on multiprocessor system!!\n" 75 "To enable mutlticore build define CONFIG_MP\n"); 76 #endif 77 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 78 printf("CPU%d: ", pic->whoami); 79 } else { 80 puts("CPU: "); 81 } 82 83 cpu = gd->cpu; 84 85 puts(cpu->name); 86 if (IS_E_PROCESSOR(svr)) 87 puts("E"); 88 89 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); 90 91 pvr = get_pvr(); 92 fam = PVR_FAM(pvr); 93 ver = PVR_VER(pvr); 94 major = PVR_MAJ(pvr); 95 minor = PVR_MIN(pvr); 96 97 printf("Core: "); 98 if (PVR_FAM(PVR_85xx)) { 99 switch(PVR_MEM(pvr)) { 100 case 0x1: 101 case 0x2: 102 puts("E500"); 103 break; 104 case 0x3: 105 puts("E500MC"); 106 break; 107 case 0x4: 108 puts("E5500"); 109 break; 110 default: 111 puts("Unknown"); 112 break; 113 } 114 } else { 115 puts("Unknown"); 116 } 117 118 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); 119 120 get_sys_info(&sysinfo); 121 122 puts("Clock Configuration:"); 123 for (i = 0; i < cpu_numcores(); i++) { 124 if (!(i & 3)) 125 printf ("\n "); 126 printf("CPU%d:%-4s MHz, ", 127 i,strmhz(buf1, sysinfo.freqProcessor[i])); 128 } 129 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); 130 131 #ifdef CONFIG_FSL_CORENET 132 if (ddr_sync == 1) { 133 printf(" DDR:%-4s MHz (%s MT/s data rate) " 134 "(Synchronous), ", 135 strmhz(buf1, sysinfo.freqDDRBus/2), 136 strmhz(buf2, sysinfo.freqDDRBus)); 137 } else { 138 printf(" DDR:%-4s MHz (%s MT/s data rate) " 139 "(Asynchronous), ", 140 strmhz(buf1, sysinfo.freqDDRBus/2), 141 strmhz(buf2, sysinfo.freqDDRBus)); 142 } 143 #else 144 switch (ddr_ratio) { 145 case 0x0: 146 printf(" DDR:%-4s MHz (%s MT/s data rate), ", 147 strmhz(buf1, sysinfo.freqDDRBus/2), 148 strmhz(buf2, sysinfo.freqDDRBus)); 149 break; 150 case 0x7: 151 printf(" DDR:%-4s MHz (%s MT/s data rate) " 152 "(Synchronous), ", 153 strmhz(buf1, sysinfo.freqDDRBus/2), 154 strmhz(buf2, sysinfo.freqDDRBus)); 155 break; 156 default: 157 printf(" DDR:%-4s MHz (%s MT/s data rate) " 158 "(Asynchronous), ", 159 strmhz(buf1, sysinfo.freqDDRBus/2), 160 strmhz(buf2, sysinfo.freqDDRBus)); 161 break; 162 } 163 #endif 164 165 if (sysinfo.freqLocalBus > LCRR_CLKDIV) { 166 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); 167 } else { 168 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", 169 sysinfo.freqLocalBus); 170 } 171 172 #ifdef CONFIG_CPM2 173 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); 174 #endif 175 176 #ifdef CONFIG_QE 177 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); 178 #endif 179 180 #ifdef CONFIG_SYS_DPAA_FMAN 181 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { 182 printf(" FMAN%d: %s MHz\n", i + 1, 183 strmhz(buf1, sysinfo.freqFMan[i])); 184 } 185 #endif 186 187 #ifdef CONFIG_SYS_DPAA_PME 188 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); 189 #endif 190 191 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); 192 193 return 0; 194 } 195 196 197 /* ------------------------------------------------------------------------- */ 198 199 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) 200 { 201 /* Everything after the first generation of PQ3 parts has RSTCR */ 202 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ 203 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) 204 unsigned long val, msr; 205 206 /* 207 * Initiate hard reset in debug control register DBCR0 208 * Make sure MSR[DE] = 1. This only resets the core. 209 */ 210 msr = mfmsr (); 211 msr |= MSR_DE; 212 mtmsr (msr); 213 214 val = mfspr(DBCR0); 215 val |= 0x70000000; 216 mtspr(DBCR0,val); 217 #else 218 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 219 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ 220 udelay(100); 221 #endif 222 223 return 1; 224 } 225 226 227 /* 228 * Get timebase clock frequency 229 */ 230 unsigned long get_tbclk (void) 231 { 232 #ifdef CONFIG_FSL_CORENET 233 return (gd->bus_clk + 8) / 16; 234 #else 235 return (gd->bus_clk + 4UL)/8UL; 236 #endif 237 } 238 239 240 #if defined(CONFIG_WATCHDOG) 241 void 242 watchdog_reset(void) 243 { 244 int re_enable = disable_interrupts(); 245 reset_85xx_watchdog(); 246 if (re_enable) enable_interrupts(); 247 } 248 249 void 250 reset_85xx_watchdog(void) 251 { 252 /* 253 * Clear TSR(WIS) bit by writing 1 254 */ 255 unsigned long val; 256 val = mfspr(SPRN_TSR); 257 val |= TSR_WIS; 258 mtspr(SPRN_TSR, val); 259 } 260 #endif /* CONFIG_WATCHDOG */ 261 262 /* 263 * Initializes on-chip MMC controllers. 264 * to override, implement board_mmc_init() 265 */ 266 int cpu_mmc_init(bd_t *bis) 267 { 268 #ifdef CONFIG_FSL_ESDHC 269 return fsl_esdhc_mmc_init(bis); 270 #else 271 return 0; 272 #endif 273 } 274 275 /* 276 * Print out the state of various machine registers. 277 * Currently prints out LAWs, BR0/OR0, and TLBs 278 */ 279 void mpc85xx_reginfo(void) 280 { 281 print_tlbcam(); 282 print_laws(); 283 print_lbc_regs(); 284 } 285