1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <linux/compiler.h> 26 #include <asm/processor.h> 27 #include "fsl_corenet_serdes.h" 28 29 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 30 /* 31 * This work-around is implemented in PBI, so just check to see if the 32 * work-around was actually applied. To do this, we check for specific data 33 * at specific addresses in DCSR. 34 * 35 * Array offsets[] contains a list of offsets within DCSR. According to the 36 * erratum document, the value at each offset should be 2. 37 */ 38 static void check_erratum_a4849(uint32_t svr) 39 { 40 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; 41 unsigned int i; 42 43 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 44 static const uint8_t offsets[] = { 45 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 46 }; 47 #endif 48 #ifdef CONFIG_PPC_P4080 49 static const uint8_t offsets[] = { 50 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac 51 }; 52 #endif 53 uint32_t x108; /* The value that should be at offset 0x108 */ 54 55 for (i = 0; i < ARRAY_SIZE(offsets); i++) { 56 if (in_be32(dcsr + offsets[i]) != 2) { 57 printf("Work-around for Erratum A004849 is not enabled\n"); 58 return; 59 } 60 } 61 62 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 63 x108 = 0x12; 64 #endif 65 66 #ifdef CONFIG_PPC_P4080 67 /* 68 * For P4080, the erratum document says that the value at offset 0x108 69 * should be 0x12 on rev2, or 0x1c on rev3. 70 */ 71 if (SVR_MAJ(svr) == 2) 72 x108 = 0x12; 73 if (SVR_MAJ(svr) == 3) 74 x108 = 0x1c; 75 #endif 76 77 if (in_be32(dcsr + 0x108) != x108) { 78 printf("Work-around for Erratum A004849 is not enabled\n"); 79 return; 80 } 81 82 /* Everything matches, so the erratum work-around was applied */ 83 84 printf("Work-around for Erratum A004849 enabled\n"); 85 } 86 #endif 87 88 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580 89 /* 90 * This work-around is implemented in PBI, so just check to see if the 91 * work-around was actually applied. To do this, we check for specific data 92 * at specific addresses in the SerDes register block. 93 * 94 * The work-around says that for each SerDes lane, write BnTTLCRy0 = 95 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000. 96 97 */ 98 static void check_erratum_a4580(uint32_t svr) 99 { 100 const serdes_corenet_t __iomem *srds_regs = 101 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 102 unsigned int lane; 103 104 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 105 if (serdes_lane_enabled(lane)) { 106 const struct serdes_lane __iomem *srds_lane = 107 &srds_regs->lane[serdes_get_lane_idx(lane)]; 108 109 /* 110 * Verify that the values we were supposed to write in 111 * the PBI are actually there. Also, the lower 15 112 * bits of res4[3] should be the same as the upper 15 113 * bits of res4[1]. 114 */ 115 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || 116 (in_be32(&srds_lane->res4[1]) != 0x880000) || 117 (in_be32(&srds_lane->res4[3]) != 0x40000044)) { 118 printf("Work-around for Erratum A004580 is " 119 "not enabled\n"); 120 return; 121 } 122 } 123 } 124 125 /* Everything matches, so the erratum work-around was applied */ 126 127 printf("Work-around for Erratum A004580 enabled\n"); 128 } 129 #endif 130 131 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 132 { 133 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 134 extern int enable_cpu_a011_workaround; 135 #endif 136 __maybe_unused u32 svr = get_svr(); 137 138 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 139 if (IS_SVR_REV(svr, 1, 0)) { 140 switch (SVR_SOC_VER(svr)) { 141 case SVR_P1013: 142 case SVR_P1022: 143 puts("Work-around for Erratum SATA A001 enabled\n"); 144 } 145 } 146 #endif 147 148 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) 149 puts("Work-around for Erratum SERDES8 enabled\n"); 150 #endif 151 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) 152 puts("Work-around for Erratum SERDES9 enabled\n"); 153 #endif 154 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) 155 puts("Work-around for Erratum SERDES-A005 enabled\n"); 156 #endif 157 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 158 if (SVR_MAJ(svr) < 3) 159 puts("Work-around for Erratum CPU22 enabled\n"); 160 #endif 161 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 162 /* 163 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 164 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 165 * The SVR has been checked by cpu_init_r(). 166 */ 167 if (enable_cpu_a011_workaround) 168 puts("Work-around for Erratum CPU-A011 enabled\n"); 169 #endif 170 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) 171 puts("Work-around for Erratum CPU-A003999 enabled\n"); 172 #endif 173 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) 174 puts("Work-around for Erratum DDR-A003473 enabled\n"); 175 #endif 176 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 177 puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); 178 #endif 179 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) 180 puts("Work-around for Erratum ESDHC111 enabled\n"); 181 #endif 182 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 183 puts("Work-around for Erratum A004468 enabled\n"); 184 #endif 185 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) 186 puts("Work-around for Erratum ESDHC135 enabled\n"); 187 #endif 188 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13) 189 if (SVR_MAJ(svr) < 3) 190 puts("Work-around for Erratum ESDHC13 enabled\n"); 191 #endif 192 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) 193 puts("Work-around for Erratum ESDHC-A001 enabled\n"); 194 #endif 195 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 196 puts("Work-around for Erratum CPC-A002 enabled\n"); 197 #endif 198 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 199 puts("Work-around for Erratum CPC-A003 enabled\n"); 200 #endif 201 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 202 puts("Work-around for Erratum ELBC-A001 enabled\n"); 203 #endif 204 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 205 puts("Work-around for Erratum DDR-A003 enabled\n"); 206 #endif 207 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 208 puts("Work-around for Erratum DDR115 enabled\n"); 209 #endif 210 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 211 puts("Work-around for Erratum DDR111 enabled\n"); 212 puts("Work-around for Erratum DDR134 enabled\n"); 213 #endif 214 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 215 puts("Work-around for Erratum IFC-A002769 enabled\n"); 216 #endif 217 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 218 puts("Work-around for Erratum P1010-A003549 enabled\n"); 219 #endif 220 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 221 puts("Work-around for Erratum IFC A-003399 enabled\n"); 222 #endif 223 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 224 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 225 puts("Work-around for Erratum NMG DDR120 enabled\n"); 226 #endif 227 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 228 puts("Work-around for Erratum NMG_LBC103 enabled\n"); 229 #endif 230 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 231 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 232 puts("Work-around for Erratum NMG ETSEC129 enabled\n"); 233 #endif 234 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 235 puts("Work-around for Erratum A004510 enabled\n"); 236 #endif 237 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 238 puts("Work-around for Erratum SRIO-A004034 enabled\n"); 239 #endif 240 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 241 puts("Work-around for Erratum A004934 enabled\n"); 242 #endif 243 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 244 /* This work-around is implemented in PBI, so just check for it */ 245 check_erratum_a4849(svr); 246 #endif 247 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580 248 /* This work-around is implemented in PBI, so just check for it */ 249 check_erratum_a4580(svr); 250 #endif 251 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 252 puts("Work-around for Erratum PCIe-A003 enabled\n"); 253 #endif 254 return 0; 255 } 256 257 U_BOOT_CMD( 258 errata, 1, 0, do_errata, 259 "Report errata workarounds", 260 "" 261 ); 262