1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include "fsl_corenet2_serdes.h" 28 29 struct serdes_config { 30 u8 protocol; 31 u8 lanes[SRDS_MAX_LANES]; 32 }; 33 34 #ifdef CONFIG_PPC_B4860 35 static struct serdes_config serdes1_cfg_tbl[] = { 36 /* SerDes 1 */ 37 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, 38 CPRI4, CPRI3, CPRI2, CPRI1}}, 39 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, 40 CPRI4, CPRI3, CPRI2, CPRI1}}, 41 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, 42 CPRI4, CPRI3, CPRI2, CPRI1}}, 43 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 44 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 45 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 46 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 47 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 48 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 49 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 50 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 51 {0x30, {AURORA, AURORA, 52 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 53 CPRI4, CPRI3, CPRI2, CPRI1}}, 54 {0x32, {AURORA, AURORA, 55 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 56 CPRI4, CPRI3, CPRI2, CPRI1}}, 57 {0x33, {AURORA, AURORA, 58 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 59 CPRI4, CPRI3, CPRI2, CPRI1}}, 60 {0x34, {AURORA, AURORA, 61 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 62 CPRI4, CPRI3, CPRI2, CPRI1}}, 63 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, 64 CPRI4, CPRI3, CPRI2, CPRI1}}, 65 {} 66 }; 67 static struct serdes_config serdes2_cfg_tbl[] = { 68 /* SerDes 2 */ 69 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 70 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 71 AURORA, AURORA, SRIO1, SRIO1}}, 72 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 73 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 74 AURORA, AURORA, SRIO1, SRIO1}}, 75 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 76 SRIO2, SRIO2, 77 AURORA, AURORA, SRIO1, SRIO1}}, 78 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 79 SRIO2, SRIO2, 80 AURORA, AURORA, 81 SRIO1, SRIO1}}, 82 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 83 SGMII_FM1_DTSEC3, AURORA, 84 SRIO1, SRIO1, SRIO1, SRIO1}}, 85 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 86 SGMII_FM1_DTSEC3, AURORA, 87 SRIO1, SRIO1, SRIO1, SRIO1}}, 88 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 89 SGMII_FM1_DTSEC3, AURORA, 90 SRIO1, SRIO1, SRIO1, SRIO1}}, 91 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 92 SGMII_FM1_DTSEC3, AURORA, 93 SRIO1, SRIO1, SRIO1, SRIO1}}, 94 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, 95 SRIO1, SRIO1, SRIO1, SRIO1}}, 96 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 97 SRIO2, SRIO2, AURORA, AURORA, 98 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 99 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 100 SRIO2, SRIO2, AURORA, AURORA, 101 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 102 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 103 SRIO2, SRIO2, 104 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 105 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 106 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, 107 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 108 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 109 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 110 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 111 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 112 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 113 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 114 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 115 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 116 {0x9A, {PCIE1, PCIE1, 117 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 118 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 119 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 120 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, 121 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 122 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 123 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 124 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 125 SRIO1, SRIO1, SRIO1, SRIO1}}, 126 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 127 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 128 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 129 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 130 {} 131 }; 132 #endif 133 134 #ifdef CONFIG_PPC_B4420 135 static struct serdes_config serdes1_cfg_tbl[] = { 136 {0x0D, {NONE, NONE, CPRI6, CPRI5, 137 CPRI4, CPRI3, NONE, NONE} }, 138 {0x0E, {NONE, NONE, CPRI8, CPRI5, 139 CPRI4, CPRI3, NONE, NONE} }, 140 {0x0F, {NONE, NONE, CPRI6, CPRI5, 141 CPRI4, CPRI3, NONE, NONE} }, 142 {0x18, {NONE, NONE, 143 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 144 NONE, NONE, NONE, NONE} }, 145 {0x1B, {NONE, NONE, 146 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 147 NONE, NONE, NONE, NONE} }, 148 {0x1E, {NONE, NONE, AURORA, AURORA, 149 NONE, NONE, NONE, NONE} }, 150 {0x21, {NONE, NONE, AURORA, AURORA, 151 NONE, NONE, NONE, NONE} }, 152 {0x3E, {NONE, NONE, CPRI6, CPRI5, 153 CPRI4, CPRI3, NONE, NONE} }, 154 {} 155 }; 156 static struct serdes_config serdes2_cfg_tbl[] = { 157 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 158 SGMII_FM1_DTSEC3, AURORA, 159 NONE, NONE, NONE, NONE} }, 160 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 161 SGMII_FM1_DTSEC3, AURORA, 162 NONE, NONE, NONE, NONE} }, 163 {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 164 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 165 {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 166 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 167 {0x9A, {PCIE1, PCIE1, 168 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 169 NONE, NONE, NONE, NONE} }, 170 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 171 NONE, NONE, NONE, NONE} }, 172 {} 173 }; 174 #endif 175 176 static struct serdes_config *serdes_cfg_tbl[] = { 177 serdes1_cfg_tbl, 178 serdes2_cfg_tbl, 179 }; 180 181 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 182 { 183 struct serdes_config *ptr; 184 185 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 186 return 0; 187 188 ptr = serdes_cfg_tbl[serdes]; 189 while (ptr->protocol) { 190 if (ptr->protocol == cfg) 191 return ptr->lanes[lane]; 192 ptr++; 193 } 194 195 return 0; 196 } 197 198 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 199 { 200 int i; 201 struct serdes_config *ptr; 202 203 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 204 return 0; 205 206 ptr = serdes_cfg_tbl[serdes]; 207 while (ptr->protocol) { 208 if (ptr->protocol == prtcl) 209 break; 210 ptr++; 211 } 212 213 if (!ptr->protocol) 214 return 0; 215 216 for (i = 0; i < SRDS_MAX_LANES; i++) { 217 if (ptr->lanes[i] != NONE) 218 return 1; 219 } 220 221 return 0; 222 } 223