1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/fsl_serdes.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include "fsl_corenet2_serdes.h" 28 29 struct serdes_config { 30 u8 protocol; 31 u8 lanes[SRDS_MAX_LANES]; 32 }; 33 34 static struct serdes_config serdes1_cfg_tbl[] = { 35 /* SerDes 1 */ 36 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, 37 CPRI4, CPRI3, CPRI2, CPRI1}}, 38 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, 39 CPRI4, CPRI3, CPRI2, CPRI1}}, 40 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, 41 CPRI4, CPRI3, CPRI2, CPRI1}}, 42 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 43 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 44 {0x30, {AURORA, AURORA, 45 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 46 CPRI4, CPRI3, CPRI2, CPRI1}}, 47 {0x32, {AURORA, AURORA, 48 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 49 CPRI4, CPRI3, CPRI2, CPRI1}}, 50 {0x33, {AURORA, AURORA, 51 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 52 CPRI4, CPRI3, CPRI2, CPRI1}}, 53 {0x34, {AURORA, AURORA, 54 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 55 CPRI4, CPRI3, CPRI2, CPRI1}}, 56 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, 57 CPRI4, CPRI3, CPRI2, CPRI1}}, 58 {} 59 }; 60 static struct serdes_config serdes2_cfg_tbl[] = { 61 /* SerDes 2 */ 62 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 63 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 64 AURORA, AURORA, SRIO1, SRIO1}}, 65 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 66 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 67 AURORA, AURORA, SRIO1, SRIO1}}, 68 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 69 SRIO2, SRIO2, 70 AURORA, AURORA, SRIO1, SRIO1}}, 71 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 72 SRIO2, SRIO2, 73 AURORA, AURORA, 74 SRIO1, SRIO1}}, 75 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 76 SGMII_FM1_DTSEC3, AURORA, 77 SRIO1, SRIO1, SRIO1, SRIO1}}, 78 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 79 SGMII_FM1_DTSEC3, AURORA, 80 SRIO1, SRIO1, SRIO1, SRIO1}}, 81 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 82 SGMII_FM1_DTSEC3, AURORA, 83 SRIO1, SRIO1, SRIO1, SRIO1}}, 84 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 85 SGMII_FM1_DTSEC3, AURORA, 86 SRIO1, SRIO1, SRIO1, SRIO1}}, 87 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 88 SRIO2, SRIO2, AURORA, AURORA, 89 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 90 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 91 SRIO2, SRIO2, AURORA, AURORA, 92 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 93 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 94 SRIO2, SRIO2, 95 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 96 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 97 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 98 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 99 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 100 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 101 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 102 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 103 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 104 {0x9A, {PCIE1, PCIE1, 105 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 106 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 107 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 108 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, 109 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 110 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 111 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 112 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 113 SRIO1, SRIO1, SRIO1, SRIO1}}, 114 {} 115 }; 116 static struct serdes_config *serdes_cfg_tbl[] = { 117 serdes1_cfg_tbl, 118 serdes2_cfg_tbl, 119 }; 120 121 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 122 { 123 struct serdes_config *ptr; 124 125 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 126 return 0; 127 128 ptr = serdes_cfg_tbl[serdes]; 129 while (ptr->protocol) { 130 if (ptr->protocol == cfg) 131 return ptr->lanes[lane]; 132 ptr++; 133 } 134 135 return 0; 136 } 137 138 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 139 { 140 int i; 141 struct serdes_config *ptr; 142 143 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 144 return 0; 145 146 ptr = serdes_cfg_tbl[serdes]; 147 while (ptr->protocol) { 148 if (ptr->protocol == prtcl) 149 break; 150 ptr++; 151 } 152 153 if (!ptr->protocol) 154 return 0; 155 156 for (i = 0; i < SRDS_MAX_LANES; i++) { 157 if (ptr->lanes[i] != NONE) 158 return 1; 159 } 160 161 return 0; 162 } 163