1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/fsl_serdes.h> 9 #include <asm/processor.h> 10 #include <asm/io.h> 11 #include "fsl_corenet2_serdes.h" 12 13 struct serdes_config { 14 u8 protocol; 15 u8 lanes[SRDS_MAX_LANES]; 16 }; 17 18 #ifdef CONFIG_PPC_B4860 19 static struct serdes_config serdes1_cfg_tbl[] = { 20 /* SerDes 1 */ 21 {0x01, {AURORA, AURORA, CPRI6, CPRI5, 22 CPRI4, CPRI3, CPRI2, CPRI1} }, 23 {0x02, {AURORA, AURORA, CPRI6, CPRI5, 24 CPRI4, CPRI3, CPRI2, CPRI1} }, 25 {0x04, {AURORA, AURORA, CPRI6, CPRI5, 26 CPRI4, CPRI3, CPRI2, CPRI1} }, 27 {0x05, {AURORA, AURORA, CPRI6, CPRI5, 28 CPRI4, CPRI3, CPRI2, CPRI1} }, 29 {0x06, {AURORA, AURORA, CPRI6, CPRI5, 30 CPRI4, CPRI3, CPRI2, CPRI1} }, 31 {0x07, {AURORA, AURORA, CPRI6, CPRI5, 32 CPRI4, CPRI3, CPRI2, CPRI1} }, 33 {0x08, {AURORA, AURORA, CPRI6, CPRI5, 34 CPRI4, CPRI3, CPRI2, CPRI1} }, 35 {0x09, {AURORA, AURORA, CPRI6, CPRI5, 36 CPRI4, CPRI3, CPRI2, CPRI1} }, 37 {0x0A, {AURORA, AURORA, CPRI6, CPRI5, 38 CPRI4, CPRI3, CPRI2, CPRI1} }, 39 {0x0B, {AURORA, AURORA, CPRI6, CPRI5, 40 CPRI4, CPRI3, CPRI2, CPRI1} }, 41 {0x0C, {AURORA, AURORA, CPRI6, CPRI5, 42 CPRI4, CPRI3, CPRI2, CPRI1} }, 43 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, 44 CPRI4, CPRI3, CPRI2, CPRI1}}, 45 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, 46 CPRI4, CPRI3, CPRI2, CPRI1}}, 47 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, 48 CPRI4, CPRI3, CPRI2, CPRI1}}, 49 {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 50 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, 51 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 52 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 53 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 54 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 55 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 56 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 57 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 58 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 59 {0x2F, {AURORA, AURORA, 60 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 61 CPRI4, CPRI3, CPRI2, CPRI1} }, 62 {0x30, {AURORA, AURORA, 63 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 64 CPRI4, CPRI3, CPRI2, CPRI1}}, 65 {0x32, {AURORA, AURORA, 66 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 67 CPRI4, CPRI3, CPRI2, CPRI1}}, 68 {0x33, {AURORA, AURORA, 69 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 70 CPRI4, CPRI3, CPRI2, CPRI1}}, 71 {0x34, {AURORA, AURORA, 72 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 73 CPRI4, CPRI3, CPRI2, CPRI1}}, 74 {0x39, {AURORA, AURORA, CPRI6, CPRI5, 75 CPRI4, CPRI3, CPRI2, CPRI1} }, 76 {0x3A, {AURORA, AURORA, CPRI6, CPRI5, 77 CPRI4, CPRI3, CPRI2, CPRI1} }, 78 {0x3C, {AURORA, AURORA, CPRI6, CPRI5, 79 CPRI4, CPRI3, CPRI2, CPRI1} }, 80 {0x3D, {AURORA, AURORA, CPRI6, CPRI5, 81 CPRI4, CPRI3, CPRI2, CPRI1} }, 82 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, 83 CPRI4, CPRI3, CPRI2, CPRI1}}, 84 {0x5C, {AURORA, AURORA, 85 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 86 CPRI4, CPRI3, CPRI2, CPRI1} }, 87 {0x5D, {AURORA, AURORA, 88 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 89 CPRI4, CPRI3, CPRI2, CPRI1} }, 90 {} 91 }; 92 static struct serdes_config serdes2_cfg_tbl[] = { 93 /* SerDes 2 */ 94 {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 95 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 96 AURORA, AURORA, SRIO1, SRIO1} }, 97 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 98 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 99 AURORA, AURORA, SRIO1, SRIO1}}, 100 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 101 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 102 AURORA, AURORA, SRIO1, SRIO1}}, 103 {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 104 SRIO2, SRIO2, 105 AURORA, AURORA, SRIO1, SRIO1} }, 106 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 107 SRIO2, SRIO2, 108 AURORA, AURORA, SRIO1, SRIO1}}, 109 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 110 SRIO2, SRIO2, 111 AURORA, AURORA, 112 SRIO1, SRIO1}}, 113 {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 114 SGMII_FM1_DTSEC3, AURORA, 115 SRIO1, SRIO1, SRIO1, SRIO1} }, 116 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 117 SGMII_FM1_DTSEC3, AURORA, 118 SRIO1, SRIO1, SRIO1, SRIO1}}, 119 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 120 SGMII_FM1_DTSEC3, AURORA, 121 SRIO1, SRIO1, SRIO1, SRIO1}}, 122 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 123 SGMII_FM1_DTSEC3, AURORA, 124 SRIO1, SRIO1, SRIO1, SRIO1}}, 125 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 126 SGMII_FM1_DTSEC3, AURORA, 127 SRIO1, SRIO1, SRIO1, SRIO1}}, 128 {0x79, {SRIO2, SRIO2, SRIO2, SRIO2, 129 SRIO1, SRIO1, SRIO1, SRIO1} }, 130 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, 131 SRIO1, SRIO1, SRIO1, SRIO1}}, 132 {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 133 SRIO2, SRIO2, AURORA, AURORA, 134 XFI_FM1_MAC9, XFI_FM1_MAC10} }, 135 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 136 SRIO2, SRIO2, AURORA, AURORA, 137 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 138 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 139 SRIO2, SRIO2, AURORA, AURORA, 140 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 141 {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 142 SRIO2, SRIO2, 143 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 144 XFI_FM1_MAC9, XFI_FM1_MAC10} }, 145 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 146 SRIO2, SRIO2, 147 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 148 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 149 {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2, 150 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 151 XFI_FM1_MAC9, XFI_FM1_MAC10} }, 152 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, 153 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 154 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 155 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 156 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 157 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 158 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 159 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 160 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 161 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 162 {0x9A, {PCIE1, PCIE1, 163 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 164 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 165 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 166 {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1, 167 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 168 XFI_FM1_MAC9, XFI_FM1_MAC10} }, 169 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, 170 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 171 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 172 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 173 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 174 SRIO1, SRIO1, SRIO1, SRIO1}}, 175 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 176 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 177 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 178 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 179 {} 180 }; 181 #endif 182 183 #ifdef CONFIG_PPC_B4420 184 static struct serdes_config serdes1_cfg_tbl[] = { 185 {0x0D, {NONE, NONE, CPRI6, CPRI5, 186 CPRI4, CPRI3, NONE, NONE} }, 187 {0x0E, {NONE, NONE, CPRI8, CPRI5, 188 CPRI4, CPRI3, NONE, NONE} }, 189 {0x0F, {NONE, NONE, CPRI6, CPRI5, 190 CPRI4, CPRI3, NONE, NONE} }, 191 {0x17, {NONE, NONE, 192 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 193 NONE, NONE, NONE, NONE} }, 194 {0x18, {NONE, NONE, 195 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 196 NONE, NONE, NONE, NONE} }, 197 {0x1B, {NONE, NONE, 198 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 199 NONE, NONE, NONE, NONE} }, 200 {0x1D, {NONE, NONE, AURORA, AURORA, 201 NONE, NONE, NONE, NONE} }, 202 {0x1E, {NONE, NONE, AURORA, AURORA, 203 NONE, NONE, NONE, NONE} }, 204 {0x21, {NONE, NONE, AURORA, AURORA, 205 NONE, NONE, NONE, NONE} }, 206 {0x3E, {NONE, NONE, CPRI6, CPRI5, 207 CPRI4, CPRI3, NONE, NONE} }, 208 {} 209 }; 210 static struct serdes_config serdes2_cfg_tbl[] = { 211 {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 212 SGMII_FM1_DTSEC3, AURORA, 213 NONE, NONE, NONE, NONE} }, 214 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 215 SGMII_FM1_DTSEC3, AURORA, 216 NONE, NONE, NONE, NONE} }, 217 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 218 SGMII_FM1_DTSEC3, AURORA, 219 NONE, NONE, NONE, NONE} }, 220 {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 221 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 222 {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 223 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 224 {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 225 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 226 {0x99, {PCIE1, PCIE1, 227 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 228 NONE, NONE, NONE, NONE} }, 229 {0x9A, {PCIE1, PCIE1, 230 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 231 NONE, NONE, NONE, NONE} }, 232 {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1, 233 NONE, NONE, NONE, NONE} }, 234 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 235 NONE, NONE, NONE, NONE} }, 236 {} 237 }; 238 #endif 239 240 static struct serdes_config *serdes_cfg_tbl[] = { 241 serdes1_cfg_tbl, 242 serdes2_cfg_tbl, 243 }; 244 245 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 246 { 247 struct serdes_config *ptr; 248 249 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 250 return 0; 251 252 ptr = serdes_cfg_tbl[serdes]; 253 while (ptr->protocol) { 254 if (ptr->protocol == cfg) 255 return ptr->lanes[lane]; 256 ptr++; 257 } 258 259 return 0; 260 } 261 262 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 263 { 264 int i; 265 struct serdes_config *ptr; 266 267 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 268 return 0; 269 270 ptr = serdes_cfg_tbl[serdes]; 271 while (ptr->protocol) { 272 if (ptr->protocol == prtcl) 273 break; 274 ptr++; 275 } 276 277 if (!ptr->protocol) 278 return 0; 279 280 for (i = 0; i < SRDS_MAX_LANES; i++) { 281 if (ptr->lanes[i] != NONE) 282 return 1; 283 } 284 285 return 0; 286 } 287