1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 imply ENV_IS_IN_FLASH 23 24config TARGET_SOCRATES 25 bool "Support socrates" 26 select ARCH_MPC8544 27 28config TARGET_B4420QDS 29 bool "Support B4420QDS" 30 select ARCH_B4420 31 select SUPPORT_SPL 32 select PHYS_64BIT 33 34config TARGET_B4860QDS 35 bool "Support B4860QDS" 36 select ARCH_B4860 37 select BOARD_LATE_INIT if CHAIN_OF_TRUST 38 select SUPPORT_SPL 39 select PHYS_64BIT 40 41config TARGET_BSC9131RDB 42 bool "Support BSC9131RDB" 43 select ARCH_BSC9131 44 select SUPPORT_SPL 45 select BOARD_EARLY_INIT_F 46 47config TARGET_BSC9132QDS 48 bool "Support BSC9132QDS" 49 select ARCH_BSC9132 50 select BOARD_LATE_INIT if CHAIN_OF_TRUST 51 select SUPPORT_SPL 52 select BOARD_EARLY_INIT_F 53 54config TARGET_C29XPCIE 55 bool "Support C29XPCIE" 56 select ARCH_C29X 57 select BOARD_LATE_INIT if CHAIN_OF_TRUST 58 select SUPPORT_SPL 59 select SUPPORT_TPL 60 select PHYS_64BIT 61 62config TARGET_P3041DS 63 bool "Support P3041DS" 64 select PHYS_64BIT 65 select ARCH_P3041 66 select BOARD_LATE_INIT if CHAIN_OF_TRUST 67 imply CMD_SATA 68 69config TARGET_P4080DS 70 bool "Support P4080DS" 71 select PHYS_64BIT 72 select ARCH_P4080 73 select BOARD_LATE_INIT if CHAIN_OF_TRUST 74 imply CMD_SATA 75 76config TARGET_P5020DS 77 bool "Support P5020DS" 78 select PHYS_64BIT 79 select ARCH_P5020 80 select BOARD_LATE_INIT if CHAIN_OF_TRUST 81 imply CMD_SATA 82 83config TARGET_P5040DS 84 bool "Support P5040DS" 85 select PHYS_64BIT 86 select ARCH_P5040 87 select BOARD_LATE_INIT if CHAIN_OF_TRUST 88 imply CMD_SATA 89 90config TARGET_MPC8536DS 91 bool "Support MPC8536DS" 92 select ARCH_MPC8536 93# Use DDR3 controller with DDR2 DIMMs on this board 94 select SYS_FSL_DDRC_GEN3 95 imply CMD_SATA 96 97config TARGET_MPC8541CDS 98 bool "Support MPC8541CDS" 99 select ARCH_MPC8541 100 101config TARGET_MPC8544DS 102 bool "Support MPC8544DS" 103 select ARCH_MPC8544 104 105config TARGET_MPC8548CDS 106 bool "Support MPC8548CDS" 107 select ARCH_MPC8548 108 imply ENV_IS_IN_FLASH 109 110config TARGET_MPC8555CDS 111 bool "Support MPC8555CDS" 112 select ARCH_MPC8555 113 114config TARGET_MPC8568MDS 115 bool "Support MPC8568MDS" 116 select ARCH_MPC8568 117 118config TARGET_MPC8569MDS 119 bool "Support MPC8569MDS" 120 select ARCH_MPC8569 121 122config TARGET_MPC8572DS 123 bool "Support MPC8572DS" 124 select ARCH_MPC8572 125# Use DDR3 controller with DDR2 DIMMs on this board 126 select SYS_FSL_DDRC_GEN3 127 imply SCSI 128 129config TARGET_P1010RDB_PA 130 bool "Support P1010RDB_PA" 131 select ARCH_P1010 132 select BOARD_LATE_INIT if CHAIN_OF_TRUST 133 select SUPPORT_SPL 134 select SUPPORT_TPL 135 imply CMD_EEPROM 136 imply CMD_SATA 137 138config TARGET_P1010RDB_PB 139 bool "Support P1010RDB_PB" 140 select ARCH_P1010 141 select BOARD_LATE_INIT if CHAIN_OF_TRUST 142 select SUPPORT_SPL 143 select SUPPORT_TPL 144 imply CMD_EEPROM 145 imply CMD_SATA 146 147config TARGET_P1022DS 148 bool "Support P1022DS" 149 select ARCH_P1022 150 select SUPPORT_SPL 151 select SUPPORT_TPL 152 imply CMD_SATA 153 154config TARGET_P1023RDB 155 bool "Support P1023RDB" 156 select ARCH_P1023 157 imply CMD_EEPROM 158 159config TARGET_P1020MBG 160 bool "Support P1020MBG-PC" 161 select SUPPORT_SPL 162 select SUPPORT_TPL 163 select ARCH_P1020 164 imply CMD_EEPROM 165 imply CMD_SATA 166 167config TARGET_P1020RDB_PC 168 bool "Support P1020RDB-PC" 169 select SUPPORT_SPL 170 select SUPPORT_TPL 171 select ARCH_P1020 172 imply CMD_EEPROM 173 imply CMD_SATA 174 175config TARGET_P1020RDB_PD 176 bool "Support P1020RDB-PD" 177 select SUPPORT_SPL 178 select SUPPORT_TPL 179 select ARCH_P1020 180 imply CMD_EEPROM 181 imply CMD_SATA 182 183config TARGET_P1020UTM 184 bool "Support P1020UTM" 185 select SUPPORT_SPL 186 select SUPPORT_TPL 187 select ARCH_P1020 188 imply CMD_EEPROM 189 imply CMD_SATA 190 191config TARGET_P1021RDB 192 bool "Support P1021RDB" 193 select SUPPORT_SPL 194 select SUPPORT_TPL 195 select ARCH_P1021 196 imply CMD_EEPROM 197 imply CMD_SATA 198 199config TARGET_P1024RDB 200 bool "Support P1024RDB" 201 select SUPPORT_SPL 202 select SUPPORT_TPL 203 select ARCH_P1024 204 imply CMD_EEPROM 205 imply CMD_SATA 206 207config TARGET_P1025RDB 208 bool "Support P1025RDB" 209 select SUPPORT_SPL 210 select SUPPORT_TPL 211 select ARCH_P1025 212 imply CMD_EEPROM 213 imply CMD_SATA 214 215config TARGET_P2020RDB 216 bool "Support P2020RDB-PC" 217 select SUPPORT_SPL 218 select SUPPORT_TPL 219 select ARCH_P2020 220 imply CMD_EEPROM 221 imply CMD_SATA 222 223config TARGET_P1_TWR 224 bool "Support p1_twr" 225 select ARCH_P1025 226 227config TARGET_P2041RDB 228 bool "Support P2041RDB" 229 select ARCH_P2041 230 select BOARD_LATE_INIT if CHAIN_OF_TRUST 231 select PHYS_64BIT 232 imply CMD_SATA 233 234config TARGET_QEMU_PPCE500 235 bool "Support qemu-ppce500" 236 select ARCH_QEMU_E500 237 select PHYS_64BIT 238 239config TARGET_T1024QDS 240 bool "Support T1024QDS" 241 select ARCH_T1024 242 select BOARD_LATE_INIT if CHAIN_OF_TRUST 243 select SUPPORT_SPL 244 select PHYS_64BIT 245 imply CMD_EEPROM 246 imply CMD_SATA 247 248config TARGET_T1023RDB 249 bool "Support T1023RDB" 250 select ARCH_T1023 251 select BOARD_LATE_INIT if CHAIN_OF_TRUST 252 select SUPPORT_SPL 253 select PHYS_64BIT 254 imply CMD_EEPROM 255 256config TARGET_T1024RDB 257 bool "Support T1024RDB" 258 select ARCH_T1024 259 select BOARD_LATE_INIT if CHAIN_OF_TRUST 260 select SUPPORT_SPL 261 select PHYS_64BIT 262 imply CMD_EEPROM 263 264config TARGET_T1040QDS 265 bool "Support T1040QDS" 266 select ARCH_T1040 267 select BOARD_LATE_INIT if CHAIN_OF_TRUST 268 select PHYS_64BIT 269 imply CMD_EEPROM 270 imply CMD_SATA 271 272config TARGET_T1040RDB 273 bool "Support T1040RDB" 274 select ARCH_T1040 275 select BOARD_LATE_INIT if CHAIN_OF_TRUST 276 select SUPPORT_SPL 277 select PHYS_64BIT 278 imply CMD_SATA 279 280config TARGET_T1040D4RDB 281 bool "Support T1040D4RDB" 282 select ARCH_T1040 283 select BOARD_LATE_INIT if CHAIN_OF_TRUST 284 select SUPPORT_SPL 285 select PHYS_64BIT 286 imply CMD_SATA 287 288config TARGET_T1042RDB 289 bool "Support T1042RDB" 290 select ARCH_T1042 291 select BOARD_LATE_INIT if CHAIN_OF_TRUST 292 select SUPPORT_SPL 293 select PHYS_64BIT 294 imply CMD_SATA 295 296config TARGET_T1042D4RDB 297 bool "Support T1042D4RDB" 298 select ARCH_T1042 299 select BOARD_LATE_INIT if CHAIN_OF_TRUST 300 select SUPPORT_SPL 301 select PHYS_64BIT 302 imply CMD_SATA 303 304config TARGET_T1042RDB_PI 305 bool "Support T1042RDB_PI" 306 select ARCH_T1042 307 select BOARD_LATE_INIT if CHAIN_OF_TRUST 308 select SUPPORT_SPL 309 select PHYS_64BIT 310 imply CMD_SATA 311 312config TARGET_T2080QDS 313 bool "Support T2080QDS" 314 select ARCH_T2080 315 select BOARD_LATE_INIT if CHAIN_OF_TRUST 316 select SUPPORT_SPL 317 select PHYS_64BIT 318 imply CMD_SATA 319 320config TARGET_T2080RDB 321 bool "Support T2080RDB" 322 select ARCH_T2080 323 select BOARD_LATE_INIT if CHAIN_OF_TRUST 324 select SUPPORT_SPL 325 select PHYS_64BIT 326 imply CMD_SATA 327 328config TARGET_T2081QDS 329 bool "Support T2081QDS" 330 select ARCH_T2081 331 select SUPPORT_SPL 332 select PHYS_64BIT 333 334config TARGET_T4160QDS 335 bool "Support T4160QDS" 336 select ARCH_T4160 337 select BOARD_LATE_INIT if CHAIN_OF_TRUST 338 select SUPPORT_SPL 339 select PHYS_64BIT 340 imply CMD_SATA 341 342config TARGET_T4160RDB 343 bool "Support T4160RDB" 344 select ARCH_T4160 345 select SUPPORT_SPL 346 select PHYS_64BIT 347 348config TARGET_T4240QDS 349 bool "Support T4240QDS" 350 select ARCH_T4240 351 select BOARD_LATE_INIT if CHAIN_OF_TRUST 352 select SUPPORT_SPL 353 select PHYS_64BIT 354 imply CMD_SATA 355 356config TARGET_T4240RDB 357 bool "Support T4240RDB" 358 select ARCH_T4240 359 select SUPPORT_SPL 360 select PHYS_64BIT 361 imply CMD_SATA 362 363config TARGET_CONTROLCENTERD 364 bool "Support controlcenterd" 365 select ARCH_P1022 366 367config TARGET_KMP204X 368 bool "Support kmp204x" 369 select ARCH_P2041 370 select PHYS_64BIT 371 imply CMD_CRAMFS 372 imply FS_CRAMFS 373 374config TARGET_XPEDITE520X 375 bool "Support xpedite520x" 376 select ARCH_MPC8548 377 378config TARGET_XPEDITE537X 379 bool "Support xpedite537x" 380 select ARCH_MPC8572 381# Use DDR3 controller with DDR2 DIMMs on this board 382 select SYS_FSL_DDRC_GEN3 383 384config TARGET_XPEDITE550X 385 bool "Support xpedite550x" 386 select ARCH_P2020 387 388config TARGET_UCP1020 389 bool "Support uCP1020" 390 select ARCH_P1020 391 imply CMD_SATA 392 393config TARGET_CYRUS_P5020 394 bool "Support Varisys Cyrus P5020" 395 select ARCH_P5020 396 select PHYS_64BIT 397 398config TARGET_CYRUS_P5040 399 bool "Support Varisys Cyrus P5040" 400 select ARCH_P5040 401 select PHYS_64BIT 402 403endchoice 404 405config ARCH_B4420 406 bool 407 select E500MC 408 select E6500 409 select FSL_LAW 410 select SYS_FSL_DDR_VER_47 411 select SYS_FSL_ERRATUM_A004477 412 select SYS_FSL_ERRATUM_A005871 413 select SYS_FSL_ERRATUM_A006379 414 select SYS_FSL_ERRATUM_A006384 415 select SYS_FSL_ERRATUM_A006475 416 select SYS_FSL_ERRATUM_A006593 417 select SYS_FSL_ERRATUM_A007075 418 select SYS_FSL_ERRATUM_A007186 419 select SYS_FSL_ERRATUM_A007212 420 select SYS_FSL_ERRATUM_A009942 421 select SYS_FSL_HAS_DDR3 422 select SYS_FSL_HAS_SEC 423 select SYS_FSL_QORIQ_CHASSIS2 424 select SYS_FSL_SEC_BE 425 select SYS_FSL_SEC_COMPAT_4 426 select SYS_PPC64 427 select FSL_IFC 428 imply CMD_EEPROM 429 430config ARCH_B4860 431 bool 432 select E500MC 433 select E6500 434 select FSL_LAW 435 select SYS_FSL_DDR_VER_47 436 select SYS_FSL_ERRATUM_A004477 437 select SYS_FSL_ERRATUM_A005871 438 select SYS_FSL_ERRATUM_A006379 439 select SYS_FSL_ERRATUM_A006384 440 select SYS_FSL_ERRATUM_A006475 441 select SYS_FSL_ERRATUM_A006593 442 select SYS_FSL_ERRATUM_A007075 443 select SYS_FSL_ERRATUM_A007186 444 select SYS_FSL_ERRATUM_A007212 445 select SYS_FSL_ERRATUM_A007907 446 select SYS_FSL_ERRATUM_A009942 447 select SYS_FSL_HAS_DDR3 448 select SYS_FSL_HAS_SEC 449 select SYS_FSL_QORIQ_CHASSIS2 450 select SYS_FSL_SEC_BE 451 select SYS_FSL_SEC_COMPAT_4 452 select SYS_PPC64 453 select FSL_IFC 454 imply CMD_EEPROM 455 456config ARCH_BSC9131 457 bool 458 select FSL_LAW 459 select SYS_FSL_DDR_VER_44 460 select SYS_FSL_ERRATUM_A004477 461 select SYS_FSL_ERRATUM_A005125 462 select SYS_FSL_ERRATUM_ESDHC111 463 select SYS_FSL_HAS_DDR3 464 select SYS_FSL_HAS_SEC 465 select SYS_FSL_SEC_BE 466 select SYS_FSL_SEC_COMPAT_4 467 select FSL_IFC 468 imply CMD_EEPROM 469 470config ARCH_BSC9132 471 bool 472 select FSL_LAW 473 select SYS_FSL_DDR_VER_46 474 select SYS_FSL_ERRATUM_A004477 475 select SYS_FSL_ERRATUM_A005125 476 select SYS_FSL_ERRATUM_A005434 477 select SYS_FSL_ERRATUM_ESDHC111 478 select SYS_FSL_ERRATUM_I2C_A004447 479 select SYS_FSL_ERRATUM_IFC_A002769 480 select SYS_FSL_HAS_DDR3 481 select SYS_FSL_HAS_SEC 482 select SYS_FSL_SEC_BE 483 select SYS_FSL_SEC_COMPAT_4 484 select SYS_PPC_E500_USE_DEBUG_TLB 485 select FSL_IFC 486 imply CMD_EEPROM 487 imply CMD_MTDPARTS 488 489config ARCH_C29X 490 bool 491 select FSL_LAW 492 select SYS_FSL_DDR_VER_46 493 select SYS_FSL_ERRATUM_A005125 494 select SYS_FSL_ERRATUM_ESDHC111 495 select SYS_FSL_HAS_DDR3 496 select SYS_FSL_HAS_SEC 497 select SYS_FSL_SEC_BE 498 select SYS_FSL_SEC_COMPAT_6 499 select SYS_PPC_E500_USE_DEBUG_TLB 500 select FSL_IFC 501 502config ARCH_MPC8536 503 bool 504 select FSL_LAW 505 select SYS_FSL_ERRATUM_A004508 506 select SYS_FSL_ERRATUM_A005125 507 select SYS_FSL_HAS_DDR2 508 select SYS_FSL_HAS_DDR3 509 select SYS_FSL_HAS_SEC 510 select SYS_FSL_SEC_BE 511 select SYS_FSL_SEC_COMPAT_2 512 select SYS_PPC_E500_USE_DEBUG_TLB 513 select FSL_ELBC 514 imply CMD_SATA 515 516config ARCH_MPC8540 517 bool 518 select FSL_LAW 519 select SYS_FSL_HAS_DDR1 520 521config ARCH_MPC8541 522 bool 523 select FSL_LAW 524 select SYS_FSL_HAS_DDR1 525 select SYS_FSL_HAS_SEC 526 select SYS_FSL_SEC_BE 527 select SYS_FSL_SEC_COMPAT_2 528 529config ARCH_MPC8544 530 bool 531 select FSL_LAW 532 select SYS_FSL_ERRATUM_A005125 533 select SYS_FSL_HAS_DDR2 534 select SYS_FSL_HAS_SEC 535 select SYS_FSL_SEC_BE 536 select SYS_FSL_SEC_COMPAT_2 537 select SYS_PPC_E500_USE_DEBUG_TLB 538 select FSL_ELBC 539 540config ARCH_MPC8548 541 bool 542 select FSL_LAW 543 select SYS_FSL_ERRATUM_A005125 544 select SYS_FSL_ERRATUM_NMG_DDR120 545 select SYS_FSL_ERRATUM_NMG_LBC103 546 select SYS_FSL_ERRATUM_NMG_ETSEC129 547 select SYS_FSL_ERRATUM_I2C_A004447 548 select SYS_FSL_HAS_DDR2 549 select SYS_FSL_HAS_DDR1 550 select SYS_FSL_HAS_SEC 551 select SYS_FSL_SEC_BE 552 select SYS_FSL_SEC_COMPAT_2 553 select SYS_PPC_E500_USE_DEBUG_TLB 554 imply ENV_IS_IN_FLASH 555 556config ARCH_MPC8555 557 bool 558 select FSL_LAW 559 select SYS_FSL_HAS_DDR1 560 select SYS_FSL_HAS_SEC 561 select SYS_FSL_SEC_BE 562 select SYS_FSL_SEC_COMPAT_2 563 564config ARCH_MPC8560 565 bool 566 select FSL_LAW 567 select SYS_FSL_HAS_DDR1 568 569config ARCH_MPC8568 570 bool 571 select FSL_LAW 572 select SYS_FSL_HAS_DDR2 573 select SYS_FSL_HAS_SEC 574 select SYS_FSL_SEC_BE 575 select SYS_FSL_SEC_COMPAT_2 576 577config ARCH_MPC8569 578 bool 579 select FSL_LAW 580 select SYS_FSL_ERRATUM_A004508 581 select SYS_FSL_ERRATUM_A005125 582 select SYS_FSL_HAS_DDR3 583 select SYS_FSL_HAS_SEC 584 select SYS_FSL_SEC_BE 585 select SYS_FSL_SEC_COMPAT_2 586 select FSL_ELBC 587 588config ARCH_MPC8572 589 bool 590 select FSL_LAW 591 select SYS_FSL_ERRATUM_A004508 592 select SYS_FSL_ERRATUM_A005125 593 select SYS_FSL_ERRATUM_DDR_115 594 select SYS_FSL_ERRATUM_DDR111_DDR134 595 select SYS_FSL_HAS_DDR2 596 select SYS_FSL_HAS_DDR3 597 select SYS_FSL_HAS_SEC 598 select SYS_FSL_SEC_BE 599 select SYS_FSL_SEC_COMPAT_2 600 select SYS_PPC_E500_USE_DEBUG_TLB 601 select FSL_ELBC 602 imply ENV_IS_IN_FLASH 603 604config ARCH_P1010 605 bool 606 select FSL_LAW 607 select SYS_FSL_ERRATUM_A004477 608 select SYS_FSL_ERRATUM_A004508 609 select SYS_FSL_ERRATUM_A005125 610 select SYS_FSL_ERRATUM_A006261 611 select SYS_FSL_ERRATUM_A007075 612 select SYS_FSL_ERRATUM_ESDHC111 613 select SYS_FSL_ERRATUM_I2C_A004447 614 select SYS_FSL_ERRATUM_IFC_A002769 615 select SYS_FSL_ERRATUM_P1010_A003549 616 select SYS_FSL_ERRATUM_SEC_A003571 617 select SYS_FSL_ERRATUM_IFC_A003399 618 select SYS_FSL_HAS_DDR3 619 select SYS_FSL_HAS_SEC 620 select SYS_FSL_SEC_BE 621 select SYS_FSL_SEC_COMPAT_4 622 select SYS_PPC_E500_USE_DEBUG_TLB 623 select FSL_IFC 624 imply CMD_EEPROM 625 imply CMD_MTDPARTS 626 imply CMD_SATA 627 628config ARCH_P1011 629 bool 630 select FSL_LAW 631 select SYS_FSL_ERRATUM_A004508 632 select SYS_FSL_ERRATUM_A005125 633 select SYS_FSL_ERRATUM_ELBC_A001 634 select SYS_FSL_ERRATUM_ESDHC111 635 select SYS_FSL_HAS_DDR3 636 select SYS_FSL_HAS_SEC 637 select SYS_FSL_SEC_BE 638 select SYS_FSL_SEC_COMPAT_2 639 select SYS_PPC_E500_USE_DEBUG_TLB 640 select FSL_ELBC 641 642config ARCH_P1020 643 bool 644 select FSL_LAW 645 select SYS_FSL_ERRATUM_A004508 646 select SYS_FSL_ERRATUM_A005125 647 select SYS_FSL_ERRATUM_ELBC_A001 648 select SYS_FSL_ERRATUM_ESDHC111 649 select SYS_FSL_HAS_DDR3 650 select SYS_FSL_HAS_SEC 651 select SYS_FSL_SEC_BE 652 select SYS_FSL_SEC_COMPAT_2 653 select SYS_PPC_E500_USE_DEBUG_TLB 654 select FSL_ELBC 655 imply CMD_SATA 656 657config ARCH_P1021 658 bool 659 select FSL_LAW 660 select SYS_FSL_ERRATUM_A004508 661 select SYS_FSL_ERRATUM_A005125 662 select SYS_FSL_ERRATUM_ELBC_A001 663 select SYS_FSL_ERRATUM_ESDHC111 664 select SYS_FSL_HAS_DDR3 665 select SYS_FSL_HAS_SEC 666 select SYS_FSL_SEC_BE 667 select SYS_FSL_SEC_COMPAT_2 668 select SYS_PPC_E500_USE_DEBUG_TLB 669 select FSL_ELBC 670 imply CMD_SATA 671 672config ARCH_P1022 673 bool 674 select FSL_LAW 675 select SYS_FSL_ERRATUM_A004477 676 select SYS_FSL_ERRATUM_A004508 677 select SYS_FSL_ERRATUM_A005125 678 select SYS_FSL_ERRATUM_ELBC_A001 679 select SYS_FSL_ERRATUM_ESDHC111 680 select SYS_FSL_ERRATUM_SATA_A001 681 select SYS_FSL_HAS_DDR3 682 select SYS_FSL_HAS_SEC 683 select SYS_FSL_SEC_BE 684 select SYS_FSL_SEC_COMPAT_2 685 select SYS_PPC_E500_USE_DEBUG_TLB 686 select FSL_ELBC 687 688config ARCH_P1023 689 bool 690 select FSL_LAW 691 select SYS_FSL_ERRATUM_A004508 692 select SYS_FSL_ERRATUM_A005125 693 select SYS_FSL_ERRATUM_I2C_A004447 694 select SYS_FSL_HAS_DDR3 695 select SYS_FSL_HAS_SEC 696 select SYS_FSL_SEC_BE 697 select SYS_FSL_SEC_COMPAT_4 698 select FSL_ELBC 699 700config ARCH_P1024 701 bool 702 select FSL_LAW 703 select SYS_FSL_ERRATUM_A004508 704 select SYS_FSL_ERRATUM_A005125 705 select SYS_FSL_ERRATUM_ELBC_A001 706 select SYS_FSL_ERRATUM_ESDHC111 707 select SYS_FSL_HAS_DDR3 708 select SYS_FSL_HAS_SEC 709 select SYS_FSL_SEC_BE 710 select SYS_FSL_SEC_COMPAT_2 711 select SYS_PPC_E500_USE_DEBUG_TLB 712 select FSL_ELBC 713 imply CMD_EEPROM 714 imply CMD_SATA 715 716config ARCH_P1025 717 bool 718 select FSL_LAW 719 select SYS_FSL_ERRATUM_A004508 720 select SYS_FSL_ERRATUM_A005125 721 select SYS_FSL_ERRATUM_ELBC_A001 722 select SYS_FSL_ERRATUM_ESDHC111 723 select SYS_FSL_HAS_DDR3 724 select SYS_FSL_HAS_SEC 725 select SYS_FSL_SEC_BE 726 select SYS_FSL_SEC_COMPAT_2 727 select SYS_PPC_E500_USE_DEBUG_TLB 728 select FSL_ELBC 729 imply CMD_SATA 730 731config ARCH_P2020 732 bool 733 select FSL_LAW 734 select SYS_FSL_ERRATUM_A004477 735 select SYS_FSL_ERRATUM_A004508 736 select SYS_FSL_ERRATUM_A005125 737 select SYS_FSL_ERRATUM_ESDHC111 738 select SYS_FSL_ERRATUM_ESDHC_A001 739 select SYS_FSL_HAS_DDR3 740 select SYS_FSL_HAS_SEC 741 select SYS_FSL_SEC_BE 742 select SYS_FSL_SEC_COMPAT_2 743 select SYS_PPC_E500_USE_DEBUG_TLB 744 select FSL_ELBC 745 imply CMD_EEPROM 746 747config ARCH_P2041 748 bool 749 select E500MC 750 select FSL_LAW 751 select SYS_FSL_ERRATUM_A004510 752 select SYS_FSL_ERRATUM_A004849 753 select SYS_FSL_ERRATUM_A006261 754 select SYS_FSL_ERRATUM_CPU_A003999 755 select SYS_FSL_ERRATUM_DDR_A003 756 select SYS_FSL_ERRATUM_DDR_A003474 757 select SYS_FSL_ERRATUM_ESDHC111 758 select SYS_FSL_ERRATUM_I2C_A004447 759 select SYS_FSL_ERRATUM_NMG_CPU_A011 760 select SYS_FSL_ERRATUM_SRIO_A004034 761 select SYS_FSL_ERRATUM_USB14 762 select SYS_FSL_HAS_DDR3 763 select SYS_FSL_HAS_SEC 764 select SYS_FSL_QORIQ_CHASSIS1 765 select SYS_FSL_SEC_BE 766 select SYS_FSL_SEC_COMPAT_4 767 select FSL_ELBC 768 769config ARCH_P3041 770 bool 771 select E500MC 772 select FSL_LAW 773 select SYS_FSL_DDR_VER_44 774 select SYS_FSL_ERRATUM_A004510 775 select SYS_FSL_ERRATUM_A004849 776 select SYS_FSL_ERRATUM_A005812 777 select SYS_FSL_ERRATUM_A006261 778 select SYS_FSL_ERRATUM_CPU_A003999 779 select SYS_FSL_ERRATUM_DDR_A003 780 select SYS_FSL_ERRATUM_DDR_A003474 781 select SYS_FSL_ERRATUM_ESDHC111 782 select SYS_FSL_ERRATUM_I2C_A004447 783 select SYS_FSL_ERRATUM_NMG_CPU_A011 784 select SYS_FSL_ERRATUM_SRIO_A004034 785 select SYS_FSL_ERRATUM_USB14 786 select SYS_FSL_HAS_DDR3 787 select SYS_FSL_HAS_SEC 788 select SYS_FSL_QORIQ_CHASSIS1 789 select SYS_FSL_SEC_BE 790 select SYS_FSL_SEC_COMPAT_4 791 select FSL_ELBC 792 imply CMD_SATA 793 794config ARCH_P4080 795 bool 796 select E500MC 797 select FSL_LAW 798 select SYS_FSL_DDR_VER_44 799 select SYS_FSL_ERRATUM_A004510 800 select SYS_FSL_ERRATUM_A004580 801 select SYS_FSL_ERRATUM_A004849 802 select SYS_FSL_ERRATUM_A005812 803 select SYS_FSL_ERRATUM_A007075 804 select SYS_FSL_ERRATUM_CPC_A002 805 select SYS_FSL_ERRATUM_CPC_A003 806 select SYS_FSL_ERRATUM_CPU_A003999 807 select SYS_FSL_ERRATUM_DDR_A003 808 select SYS_FSL_ERRATUM_DDR_A003474 809 select SYS_FSL_ERRATUM_ELBC_A001 810 select SYS_FSL_ERRATUM_ESDHC111 811 select SYS_FSL_ERRATUM_ESDHC13 812 select SYS_FSL_ERRATUM_ESDHC135 813 select SYS_FSL_ERRATUM_I2C_A004447 814 select SYS_FSL_ERRATUM_NMG_CPU_A011 815 select SYS_FSL_ERRATUM_SRIO_A004034 816 select SYS_P4080_ERRATUM_CPU22 817 select SYS_P4080_ERRATUM_PCIE_A003 818 select SYS_P4080_ERRATUM_SERDES8 819 select SYS_P4080_ERRATUM_SERDES9 820 select SYS_P4080_ERRATUM_SERDES_A001 821 select SYS_P4080_ERRATUM_SERDES_A005 822 select SYS_FSL_HAS_DDR3 823 select SYS_FSL_HAS_SEC 824 select SYS_FSL_QORIQ_CHASSIS1 825 select SYS_FSL_SEC_BE 826 select SYS_FSL_SEC_COMPAT_4 827 select FSL_ELBC 828 imply CMD_SATA 829 830config ARCH_P5020 831 bool 832 select E500MC 833 select FSL_LAW 834 select SYS_FSL_DDR_VER_44 835 select SYS_FSL_ERRATUM_A004510 836 select SYS_FSL_ERRATUM_A006261 837 select SYS_FSL_ERRATUM_DDR_A003 838 select SYS_FSL_ERRATUM_DDR_A003474 839 select SYS_FSL_ERRATUM_ESDHC111 840 select SYS_FSL_ERRATUM_I2C_A004447 841 select SYS_FSL_ERRATUM_SRIO_A004034 842 select SYS_FSL_ERRATUM_USB14 843 select SYS_FSL_HAS_DDR3 844 select SYS_FSL_HAS_SEC 845 select SYS_FSL_QORIQ_CHASSIS1 846 select SYS_FSL_SEC_BE 847 select SYS_FSL_SEC_COMPAT_4 848 select SYS_PPC64 849 select FSL_ELBC 850 imply CMD_SATA 851 852config ARCH_P5040 853 bool 854 select E500MC 855 select FSL_LAW 856 select SYS_FSL_DDR_VER_44 857 select SYS_FSL_ERRATUM_A004510 858 select SYS_FSL_ERRATUM_A004699 859 select SYS_FSL_ERRATUM_A005812 860 select SYS_FSL_ERRATUM_A006261 861 select SYS_FSL_ERRATUM_DDR_A003 862 select SYS_FSL_ERRATUM_DDR_A003474 863 select SYS_FSL_ERRATUM_ESDHC111 864 select SYS_FSL_ERRATUM_USB14 865 select SYS_FSL_HAS_DDR3 866 select SYS_FSL_HAS_SEC 867 select SYS_FSL_QORIQ_CHASSIS1 868 select SYS_FSL_SEC_BE 869 select SYS_FSL_SEC_COMPAT_4 870 select SYS_PPC64 871 select FSL_ELBC 872 imply CMD_SATA 873 874config ARCH_QEMU_E500 875 bool 876 877config ARCH_T1023 878 bool 879 select E500MC 880 select FSL_LAW 881 select SYS_FSL_DDR_VER_50 882 select SYS_FSL_ERRATUM_A008378 883 select SYS_FSL_ERRATUM_A009663 884 select SYS_FSL_ERRATUM_A009942 885 select SYS_FSL_ERRATUM_ESDHC111 886 select SYS_FSL_HAS_DDR3 887 select SYS_FSL_HAS_DDR4 888 select SYS_FSL_HAS_SEC 889 select SYS_FSL_QORIQ_CHASSIS2 890 select SYS_FSL_SEC_BE 891 select SYS_FSL_SEC_COMPAT_5 892 select FSL_IFC 893 imply CMD_EEPROM 894 895config ARCH_T1024 896 bool 897 select E500MC 898 select FSL_LAW 899 select SYS_FSL_DDR_VER_50 900 select SYS_FSL_ERRATUM_A008378 901 select SYS_FSL_ERRATUM_A009663 902 select SYS_FSL_ERRATUM_A009942 903 select SYS_FSL_ERRATUM_ESDHC111 904 select SYS_FSL_HAS_DDR3 905 select SYS_FSL_HAS_DDR4 906 select SYS_FSL_HAS_SEC 907 select SYS_FSL_QORIQ_CHASSIS2 908 select SYS_FSL_SEC_BE 909 select SYS_FSL_SEC_COMPAT_5 910 select FSL_IFC 911 imply CMD_EEPROM 912 imply CMD_MTDPARTS 913 914config ARCH_T1040 915 bool 916 select E500MC 917 select FSL_LAW 918 select SYS_FSL_DDR_VER_50 919 select SYS_FSL_ERRATUM_A008044 920 select SYS_FSL_ERRATUM_A008378 921 select SYS_FSL_ERRATUM_A009663 922 select SYS_FSL_ERRATUM_A009942 923 select SYS_FSL_ERRATUM_ESDHC111 924 select SYS_FSL_HAS_DDR3 925 select SYS_FSL_HAS_DDR4 926 select SYS_FSL_HAS_SEC 927 select SYS_FSL_QORIQ_CHASSIS2 928 select SYS_FSL_SEC_BE 929 select SYS_FSL_SEC_COMPAT_5 930 select FSL_IFC 931 imply CMD_MTDPARTS 932 imply CMD_SATA 933 934config ARCH_T1042 935 bool 936 select E500MC 937 select FSL_LAW 938 select SYS_FSL_DDR_VER_50 939 select SYS_FSL_ERRATUM_A008044 940 select SYS_FSL_ERRATUM_A008378 941 select SYS_FSL_ERRATUM_A009663 942 select SYS_FSL_ERRATUM_A009942 943 select SYS_FSL_ERRATUM_ESDHC111 944 select SYS_FSL_HAS_DDR3 945 select SYS_FSL_HAS_DDR4 946 select SYS_FSL_HAS_SEC 947 select SYS_FSL_QORIQ_CHASSIS2 948 select SYS_FSL_SEC_BE 949 select SYS_FSL_SEC_COMPAT_5 950 select FSL_IFC 951 imply CMD_MTDPARTS 952 imply CMD_SATA 953 954config ARCH_T2080 955 bool 956 select E500MC 957 select E6500 958 select FSL_LAW 959 select SYS_FSL_DDR_VER_47 960 select SYS_FSL_ERRATUM_A006379 961 select SYS_FSL_ERRATUM_A006593 962 select SYS_FSL_ERRATUM_A007186 963 select SYS_FSL_ERRATUM_A007212 964 select SYS_FSL_ERRATUM_A007815 965 select SYS_FSL_ERRATUM_A007907 966 select SYS_FSL_ERRATUM_A009942 967 select SYS_FSL_ERRATUM_ESDHC111 968 select SYS_FSL_HAS_DDR3 969 select SYS_FSL_HAS_SEC 970 select SYS_FSL_QORIQ_CHASSIS2 971 select SYS_FSL_SEC_BE 972 select SYS_FSL_SEC_COMPAT_4 973 select SYS_PPC64 974 select FSL_IFC 975 imply CMD_SATA 976 977config ARCH_T2081 978 bool 979 select E500MC 980 select E6500 981 select FSL_LAW 982 select SYS_FSL_DDR_VER_47 983 select SYS_FSL_ERRATUM_A006379 984 select SYS_FSL_ERRATUM_A006593 985 select SYS_FSL_ERRATUM_A007186 986 select SYS_FSL_ERRATUM_A007212 987 select SYS_FSL_ERRATUM_A009942 988 select SYS_FSL_ERRATUM_ESDHC111 989 select SYS_FSL_HAS_DDR3 990 select SYS_FSL_HAS_SEC 991 select SYS_FSL_QORIQ_CHASSIS2 992 select SYS_FSL_SEC_BE 993 select SYS_FSL_SEC_COMPAT_4 994 select SYS_PPC64 995 select FSL_IFC 996 997config ARCH_T4160 998 bool 999 select E500MC 1000 select E6500 1001 select FSL_LAW 1002 select SYS_FSL_DDR_VER_47 1003 select SYS_FSL_ERRATUM_A004468 1004 select SYS_FSL_ERRATUM_A005871 1005 select SYS_FSL_ERRATUM_A006379 1006 select SYS_FSL_ERRATUM_A006593 1007 select SYS_FSL_ERRATUM_A007186 1008 select SYS_FSL_ERRATUM_A007798 1009 select SYS_FSL_ERRATUM_A009942 1010 select SYS_FSL_HAS_DDR3 1011 select SYS_FSL_HAS_SEC 1012 select SYS_FSL_QORIQ_CHASSIS2 1013 select SYS_FSL_SEC_BE 1014 select SYS_FSL_SEC_COMPAT_4 1015 select SYS_PPC64 1016 select FSL_IFC 1017 imply CMD_SATA 1018 1019config ARCH_T4240 1020 bool 1021 select E500MC 1022 select E6500 1023 select FSL_LAW 1024 select SYS_FSL_DDR_VER_47 1025 select SYS_FSL_ERRATUM_A004468 1026 select SYS_FSL_ERRATUM_A005871 1027 select SYS_FSL_ERRATUM_A006261 1028 select SYS_FSL_ERRATUM_A006379 1029 select SYS_FSL_ERRATUM_A006593 1030 select SYS_FSL_ERRATUM_A007186 1031 select SYS_FSL_ERRATUM_A007798 1032 select SYS_FSL_ERRATUM_A007815 1033 select SYS_FSL_ERRATUM_A007907 1034 select SYS_FSL_ERRATUM_A009942 1035 select SYS_FSL_HAS_DDR3 1036 select SYS_FSL_HAS_SEC 1037 select SYS_FSL_QORIQ_CHASSIS2 1038 select SYS_FSL_SEC_BE 1039 select SYS_FSL_SEC_COMPAT_4 1040 select SYS_PPC64 1041 select FSL_IFC 1042 imply CMD_SATA 1043 1044config BOOKE 1045 bool 1046 default y 1047 1048config E500 1049 bool 1050 default y 1051 help 1052 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 1053 1054config E500MC 1055 bool 1056 help 1057 Enble PowerPC E500MC core 1058 1059config E6500 1060 bool 1061 help 1062 Enable PowerPC E6500 core 1063 1064config FSL_LAW 1065 bool 1066 help 1067 Use Freescale common code for Local Access Window 1068 1069config SECURE_BOOT 1070 bool "Secure Boot" 1071 help 1072 Enable Freescale Secure Boot feature. Normally selected 1073 by defconfig. If unsure, do not change. 1074 1075config MAX_CPUS 1076 int "Maximum number of CPUs permitted for MPC85xx" 1077 default 12 if ARCH_T4240 1078 default 8 if ARCH_P4080 || \ 1079 ARCH_T4160 1080 default 4 if ARCH_B4860 || \ 1081 ARCH_P2041 || \ 1082 ARCH_P3041 || \ 1083 ARCH_P5040 || \ 1084 ARCH_T1040 || \ 1085 ARCH_T1042 || \ 1086 ARCH_T2080 || \ 1087 ARCH_T2081 1088 default 2 if ARCH_B4420 || \ 1089 ARCH_BSC9132 || \ 1090 ARCH_MPC8572 || \ 1091 ARCH_P1020 || \ 1092 ARCH_P1021 || \ 1093 ARCH_P1022 || \ 1094 ARCH_P1023 || \ 1095 ARCH_P1024 || \ 1096 ARCH_P1025 || \ 1097 ARCH_P2020 || \ 1098 ARCH_P5020 || \ 1099 ARCH_T1023 || \ 1100 ARCH_T1024 1101 default 1 1102 help 1103 Set this number to the maximum number of possible CPUs in the SoC. 1104 SoCs may have multiple clusters with each cluster may have multiple 1105 ports. If some ports are reserved but higher ports are used for 1106 cores, count the reserved ports. This will allocate enough memory 1107 in spin table to properly handle all cores. 1108 1109config SYS_CCSRBAR_DEFAULT 1110 hex "Default CCSRBAR address" 1111 default 0xff700000 if ARCH_BSC9131 || \ 1112 ARCH_BSC9132 || \ 1113 ARCH_C29X || \ 1114 ARCH_MPC8536 || \ 1115 ARCH_MPC8540 || \ 1116 ARCH_MPC8541 || \ 1117 ARCH_MPC8544 || \ 1118 ARCH_MPC8548 || \ 1119 ARCH_MPC8555 || \ 1120 ARCH_MPC8560 || \ 1121 ARCH_MPC8568 || \ 1122 ARCH_MPC8569 || \ 1123 ARCH_MPC8572 || \ 1124 ARCH_P1010 || \ 1125 ARCH_P1011 || \ 1126 ARCH_P1020 || \ 1127 ARCH_P1021 || \ 1128 ARCH_P1022 || \ 1129 ARCH_P1024 || \ 1130 ARCH_P1025 || \ 1131 ARCH_P2020 1132 default 0xff600000 if ARCH_P1023 1133 default 0xfe000000 if ARCH_B4420 || \ 1134 ARCH_B4860 || \ 1135 ARCH_P2041 || \ 1136 ARCH_P3041 || \ 1137 ARCH_P4080 || \ 1138 ARCH_P5020 || \ 1139 ARCH_P5040 || \ 1140 ARCH_T1023 || \ 1141 ARCH_T1024 || \ 1142 ARCH_T1040 || \ 1143 ARCH_T1042 || \ 1144 ARCH_T2080 || \ 1145 ARCH_T2081 || \ 1146 ARCH_T4160 || \ 1147 ARCH_T4240 1148 default 0xe0000000 if ARCH_QEMU_E500 1149 help 1150 Default value of CCSRBAR comes from power-on-reset. It 1151 is fixed on each SoC. Some SoCs can have different value 1152 if changed by pre-boot regime. The value here must match 1153 the current value in SoC. If not sure, do not change. 1154 1155config SYS_FSL_ERRATUM_A004468 1156 bool 1157 1158config SYS_FSL_ERRATUM_A004477 1159 bool 1160 1161config SYS_FSL_ERRATUM_A004508 1162 bool 1163 1164config SYS_FSL_ERRATUM_A004580 1165 bool 1166 1167config SYS_FSL_ERRATUM_A004699 1168 bool 1169 1170config SYS_FSL_ERRATUM_A004849 1171 bool 1172 1173config SYS_FSL_ERRATUM_A004510 1174 bool 1175 1176config SYS_FSL_ERRATUM_A004510_SVR_REV 1177 hex 1178 depends on SYS_FSL_ERRATUM_A004510 1179 default 0x20 if ARCH_P4080 1180 default 0x10 1181 1182config SYS_FSL_ERRATUM_A004510_SVR_REV2 1183 hex 1184 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1185 default 0x11 1186 1187config SYS_FSL_ERRATUM_A005125 1188 bool 1189 1190config SYS_FSL_ERRATUM_A005434 1191 bool 1192 1193config SYS_FSL_ERRATUM_A005812 1194 bool 1195 1196config SYS_FSL_ERRATUM_A005871 1197 bool 1198 1199config SYS_FSL_ERRATUM_A006261 1200 bool 1201 1202config SYS_FSL_ERRATUM_A006379 1203 bool 1204 1205config SYS_FSL_ERRATUM_A006384 1206 bool 1207 1208config SYS_FSL_ERRATUM_A006475 1209 bool 1210 1211config SYS_FSL_ERRATUM_A006593 1212 bool 1213 1214config SYS_FSL_ERRATUM_A007075 1215 bool 1216 1217config SYS_FSL_ERRATUM_A007186 1218 bool 1219 1220config SYS_FSL_ERRATUM_A007212 1221 bool 1222 1223config SYS_FSL_ERRATUM_A007815 1224 bool 1225 1226config SYS_FSL_ERRATUM_A007798 1227 bool 1228 1229config SYS_FSL_ERRATUM_A007907 1230 bool 1231 1232config SYS_FSL_ERRATUM_A008044 1233 bool 1234 1235config SYS_FSL_ERRATUM_CPC_A002 1236 bool 1237 1238config SYS_FSL_ERRATUM_CPC_A003 1239 bool 1240 1241config SYS_FSL_ERRATUM_CPU_A003999 1242 bool 1243 1244config SYS_FSL_ERRATUM_ELBC_A001 1245 bool 1246 1247config SYS_FSL_ERRATUM_I2C_A004447 1248 bool 1249 1250config SYS_FSL_A004447_SVR_REV 1251 hex 1252 depends on SYS_FSL_ERRATUM_I2C_A004447 1253 default 0x00 if ARCH_MPC8548 1254 default 0x10 if ARCH_P1010 1255 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1256 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1257 1258config SYS_FSL_ERRATUM_IFC_A002769 1259 bool 1260 1261config SYS_FSL_ERRATUM_IFC_A003399 1262 bool 1263 1264config SYS_FSL_ERRATUM_NMG_CPU_A011 1265 bool 1266 1267config SYS_FSL_ERRATUM_NMG_ETSEC129 1268 bool 1269 1270config SYS_FSL_ERRATUM_NMG_LBC103 1271 bool 1272 1273config SYS_FSL_ERRATUM_P1010_A003549 1274 bool 1275 1276config SYS_FSL_ERRATUM_SATA_A001 1277 bool 1278 1279config SYS_FSL_ERRATUM_SEC_A003571 1280 bool 1281 1282config SYS_FSL_ERRATUM_SRIO_A004034 1283 bool 1284 1285config SYS_FSL_ERRATUM_USB14 1286 bool 1287 1288config SYS_P4080_ERRATUM_CPU22 1289 bool 1290 1291config SYS_P4080_ERRATUM_PCIE_A003 1292 bool 1293 1294config SYS_P4080_ERRATUM_SERDES8 1295 bool 1296 1297config SYS_P4080_ERRATUM_SERDES9 1298 bool 1299 1300config SYS_P4080_ERRATUM_SERDES_A001 1301 bool 1302 1303config SYS_P4080_ERRATUM_SERDES_A005 1304 bool 1305 1306config SYS_FSL_QORIQ_CHASSIS1 1307 bool 1308 1309config SYS_FSL_QORIQ_CHASSIS2 1310 bool 1311 1312config SYS_FSL_NUM_LAWS 1313 int "Number of local access windows" 1314 depends on FSL_LAW 1315 default 32 if ARCH_B4420 || \ 1316 ARCH_B4860 || \ 1317 ARCH_P2041 || \ 1318 ARCH_P3041 || \ 1319 ARCH_P4080 || \ 1320 ARCH_P5020 || \ 1321 ARCH_P5040 || \ 1322 ARCH_T2080 || \ 1323 ARCH_T2081 || \ 1324 ARCH_T4160 || \ 1325 ARCH_T4240 1326 default 16 if ARCH_T1023 || \ 1327 ARCH_T1024 || \ 1328 ARCH_T1040 || \ 1329 ARCH_T1042 1330 default 12 if ARCH_BSC9131 || \ 1331 ARCH_BSC9132 || \ 1332 ARCH_C29X || \ 1333 ARCH_MPC8536 || \ 1334 ARCH_MPC8572 || \ 1335 ARCH_P1010 || \ 1336 ARCH_P1011 || \ 1337 ARCH_P1020 || \ 1338 ARCH_P1021 || \ 1339 ARCH_P1022 || \ 1340 ARCH_P1023 || \ 1341 ARCH_P1024 || \ 1342 ARCH_P1025 || \ 1343 ARCH_P2020 1344 default 10 if ARCH_MPC8544 || \ 1345 ARCH_MPC8548 || \ 1346 ARCH_MPC8568 || \ 1347 ARCH_MPC8569 1348 default 8 if ARCH_MPC8540 || \ 1349 ARCH_MPC8541 || \ 1350 ARCH_MPC8555 || \ 1351 ARCH_MPC8560 1352 help 1353 Number of local access windows. This is fixed per SoC. 1354 If not sure, do not change. 1355 1356config SYS_FSL_THREADS_PER_CORE 1357 int 1358 default 2 if E6500 1359 default 1 1360 1361config SYS_NUM_TLBCAMS 1362 int "Number of TLB CAM entries" 1363 default 64 if E500MC 1364 default 16 1365 help 1366 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1367 16 for other E500 SoCs. 1368 1369config SYS_PPC64 1370 bool 1371 1372config SYS_PPC_E500_USE_DEBUG_TLB 1373 bool 1374 1375config FSL_IFC 1376 bool 1377 1378config FSL_ELBC 1379 bool 1380 1381config SYS_PPC_E500_DEBUG_TLB 1382 int "Temporary TLB entry for external debugger" 1383 depends on SYS_PPC_E500_USE_DEBUG_TLB 1384 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1385 default 1 if ARCH_MPC8536 1386 default 2 if ARCH_MPC8572 || \ 1387 ARCH_P1011 || \ 1388 ARCH_P1020 || \ 1389 ARCH_P1021 || \ 1390 ARCH_P1022 || \ 1391 ARCH_P1024 || \ 1392 ARCH_P1025 || \ 1393 ARCH_P2020 1394 default 3 if ARCH_P1010 || \ 1395 ARCH_BSC9132 || \ 1396 ARCH_C29X 1397 help 1398 Select a temporary TLB entry to be used during boot to work 1399 around limitations in e500v1 and e500v2 external debugger 1400 support. This reduces the portions of the boot code where 1401 breakpoints and single stepping do not work. The value of this 1402 symbol should be set to the TLB1 entry to be used for this 1403 purpose. If unsure, do not change. 1404 1405config SYS_FSL_IFC_CLK_DIV 1406 int "Divider of platform clock" 1407 depends on FSL_IFC 1408 default 2 if ARCH_B4420 || \ 1409 ARCH_B4860 || \ 1410 ARCH_T1024 || \ 1411 ARCH_T1023 || \ 1412 ARCH_T1040 || \ 1413 ARCH_T1042 || \ 1414 ARCH_T4160 || \ 1415 ARCH_T4240 1416 default 1 1417 help 1418 Defines divider of platform clock(clock input to 1419 IFC controller). 1420 1421config SYS_FSL_LBC_CLK_DIV 1422 int "Divider of platform clock" 1423 depends on FSL_ELBC || ARCH_MPC8540 || \ 1424 ARCH_MPC8548 || ARCH_MPC8541 || \ 1425 ARCH_MPC8555 || ARCH_MPC8560 || \ 1426 ARCH_MPC8568 1427 1428 default 2 if ARCH_P2041 || \ 1429 ARCH_P3041 || \ 1430 ARCH_P4080 || \ 1431 ARCH_P5020 || \ 1432 ARCH_P5040 1433 default 1 1434 1435 help 1436 Defines divider of platform clock(clock input to 1437 eLBC controller). 1438 1439source "board/freescale/b4860qds/Kconfig" 1440source "board/freescale/bsc9131rdb/Kconfig" 1441source "board/freescale/bsc9132qds/Kconfig" 1442source "board/freescale/c29xpcie/Kconfig" 1443source "board/freescale/corenet_ds/Kconfig" 1444source "board/freescale/mpc8536ds/Kconfig" 1445source "board/freescale/mpc8541cds/Kconfig" 1446source "board/freescale/mpc8544ds/Kconfig" 1447source "board/freescale/mpc8548cds/Kconfig" 1448source "board/freescale/mpc8555cds/Kconfig" 1449source "board/freescale/mpc8568mds/Kconfig" 1450source "board/freescale/mpc8569mds/Kconfig" 1451source "board/freescale/mpc8572ds/Kconfig" 1452source "board/freescale/p1010rdb/Kconfig" 1453source "board/freescale/p1022ds/Kconfig" 1454source "board/freescale/p1023rdb/Kconfig" 1455source "board/freescale/p1_p2_rdb_pc/Kconfig" 1456source "board/freescale/p1_twr/Kconfig" 1457source "board/freescale/p2041rdb/Kconfig" 1458source "board/freescale/qemu-ppce500/Kconfig" 1459source "board/freescale/t102xqds/Kconfig" 1460source "board/freescale/t102xrdb/Kconfig" 1461source "board/freescale/t1040qds/Kconfig" 1462source "board/freescale/t104xrdb/Kconfig" 1463source "board/freescale/t208xqds/Kconfig" 1464source "board/freescale/t208xrdb/Kconfig" 1465source "board/freescale/t4qds/Kconfig" 1466source "board/freescale/t4rdb/Kconfig" 1467source "board/gdsys/p1022/Kconfig" 1468source "board/keymile/kmp204x/Kconfig" 1469source "board/sbc8548/Kconfig" 1470source "board/socrates/Kconfig" 1471source "board/varisys/cyrus/Kconfig" 1472source "board/xes/xpedite520x/Kconfig" 1473source "board/xes/xpedite537x/Kconfig" 1474source "board/xes/xpedite550x/Kconfig" 1475source "board/Arcturus/ucp1020/Kconfig" 1476 1477endmenu 1478