1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_SBC8548 12 bool "Support sbc8548" 13 select ARCH_MPC8548 14 15config TARGET_SOCRATES 16 bool "Support socrates" 17 select ARCH_MPC8544 18 19config TARGET_B4420QDS 20 bool "Support B4420QDS" 21 select ARCH_B4420 22 select SUPPORT_SPL 23 select PHYS_64BIT 24 25config TARGET_B4860QDS 26 bool "Support B4860QDS" 27 select ARCH_B4860 28 select BOARD_LATE_INIT if CHAIN_OF_TRUST 29 select SUPPORT_SPL 30 select PHYS_64BIT 31 32config TARGET_BSC9131RDB 33 bool "Support BSC9131RDB" 34 select ARCH_BSC9131 35 select SUPPORT_SPL 36 select BOARD_EARLY_INIT_F 37 38config TARGET_BSC9132QDS 39 bool "Support BSC9132QDS" 40 select ARCH_BSC9132 41 select BOARD_LATE_INIT if CHAIN_OF_TRUST 42 select SUPPORT_SPL 43 select BOARD_EARLY_INIT_F 44 45config TARGET_C29XPCIE 46 bool "Support C29XPCIE" 47 select ARCH_C29X 48 select BOARD_LATE_INIT if CHAIN_OF_TRUST 49 select SUPPORT_SPL 50 select SUPPORT_TPL 51 select PHYS_64BIT 52 53config TARGET_P3041DS 54 bool "Support P3041DS" 55 select PHYS_64BIT 56 select ARCH_P3041 57 select BOARD_LATE_INIT if CHAIN_OF_TRUST 58 59config TARGET_P4080DS 60 bool "Support P4080DS" 61 select PHYS_64BIT 62 select ARCH_P4080 63 select BOARD_LATE_INIT if CHAIN_OF_TRUST 64 65config TARGET_P5020DS 66 bool "Support P5020DS" 67 select PHYS_64BIT 68 select ARCH_P5020 69 select BOARD_LATE_INIT if CHAIN_OF_TRUST 70 71config TARGET_P5040DS 72 bool "Support P5040DS" 73 select PHYS_64BIT 74 select ARCH_P5040 75 select BOARD_LATE_INIT if CHAIN_OF_TRUST 76 77config TARGET_MPC8536DS 78 bool "Support MPC8536DS" 79 select ARCH_MPC8536 80# Use DDR3 controller with DDR2 DIMMs on this board 81 select SYS_FSL_DDRC_GEN3 82 83config TARGET_MPC8540ADS 84 bool "Support MPC8540ADS" 85 select ARCH_MPC8540 86 87config TARGET_MPC8541CDS 88 bool "Support MPC8541CDS" 89 select ARCH_MPC8541 90 91config TARGET_MPC8544DS 92 bool "Support MPC8544DS" 93 select ARCH_MPC8544 94 95config TARGET_MPC8548CDS 96 bool "Support MPC8548CDS" 97 select ARCH_MPC8548 98 99config TARGET_MPC8555CDS 100 bool "Support MPC8555CDS" 101 select ARCH_MPC8555 102 103config TARGET_MPC8560ADS 104 bool "Support MPC8560ADS" 105 select ARCH_MPC8560 106 107config TARGET_MPC8568MDS 108 bool "Support MPC8568MDS" 109 select ARCH_MPC8568 110 111config TARGET_MPC8569MDS 112 bool "Support MPC8569MDS" 113 select ARCH_MPC8569 114 115config TARGET_MPC8572DS 116 bool "Support MPC8572DS" 117 select ARCH_MPC8572 118# Use DDR3 controller with DDR2 DIMMs on this board 119 select SYS_FSL_DDRC_GEN3 120 121config TARGET_P1010RDB_PA 122 bool "Support P1010RDB_PA" 123 select ARCH_P1010 124 select BOARD_LATE_INIT if CHAIN_OF_TRUST 125 select SUPPORT_SPL 126 select SUPPORT_TPL 127 128config TARGET_P1010RDB_PB 129 bool "Support P1010RDB_PB" 130 select ARCH_P1010 131 select BOARD_LATE_INIT if CHAIN_OF_TRUST 132 select SUPPORT_SPL 133 select SUPPORT_TPL 134 135config TARGET_P1022DS 136 bool "Support P1022DS" 137 select ARCH_P1022 138 select SUPPORT_SPL 139 select SUPPORT_TPL 140 141config TARGET_P1023RDB 142 bool "Support P1023RDB" 143 select ARCH_P1023 144 145config TARGET_P1020MBG 146 bool "Support P1020MBG-PC" 147 select SUPPORT_SPL 148 select SUPPORT_TPL 149 select ARCH_P1020 150 151config TARGET_P1020RDB_PC 152 bool "Support P1020RDB-PC" 153 select SUPPORT_SPL 154 select SUPPORT_TPL 155 select ARCH_P1020 156 157config TARGET_P1020RDB_PD 158 bool "Support P1020RDB-PD" 159 select SUPPORT_SPL 160 select SUPPORT_TPL 161 select ARCH_P1020 162 163config TARGET_P1020UTM 164 bool "Support P1020UTM" 165 select SUPPORT_SPL 166 select SUPPORT_TPL 167 select ARCH_P1020 168 169config TARGET_P1021RDB 170 bool "Support P1021RDB" 171 select SUPPORT_SPL 172 select SUPPORT_TPL 173 select ARCH_P1021 174 175config TARGET_P1024RDB 176 bool "Support P1024RDB" 177 select SUPPORT_SPL 178 select SUPPORT_TPL 179 select ARCH_P1024 180 181config TARGET_P1025RDB 182 bool "Support P1025RDB" 183 select SUPPORT_SPL 184 select SUPPORT_TPL 185 select ARCH_P1025 186 187config TARGET_P2020RDB 188 bool "Support P2020RDB-PC" 189 select SUPPORT_SPL 190 select SUPPORT_TPL 191 select ARCH_P2020 192 193config TARGET_P1_TWR 194 bool "Support p1_twr" 195 select ARCH_P1025 196 197config TARGET_P2041RDB 198 bool "Support P2041RDB" 199 select ARCH_P2041 200 select BOARD_LATE_INIT if CHAIN_OF_TRUST 201 select PHYS_64BIT 202 203config TARGET_QEMU_PPCE500 204 bool "Support qemu-ppce500" 205 select ARCH_QEMU_E500 206 select PHYS_64BIT 207 208config TARGET_T1024QDS 209 bool "Support T1024QDS" 210 select ARCH_T1024 211 select BOARD_LATE_INIT if CHAIN_OF_TRUST 212 select SUPPORT_SPL 213 select PHYS_64BIT 214 215config TARGET_T1023RDB 216 bool "Support T1023RDB" 217 select ARCH_T1023 218 select BOARD_LATE_INIT if CHAIN_OF_TRUST 219 select SUPPORT_SPL 220 select PHYS_64BIT 221 222config TARGET_T1024RDB 223 bool "Support T1024RDB" 224 select ARCH_T1024 225 select BOARD_LATE_INIT if CHAIN_OF_TRUST 226 select SUPPORT_SPL 227 select PHYS_64BIT 228 229config TARGET_T1040QDS 230 bool "Support T1040QDS" 231 select ARCH_T1040 232 select BOARD_LATE_INIT if CHAIN_OF_TRUST 233 select PHYS_64BIT 234 235config TARGET_T1040RDB 236 bool "Support T1040RDB" 237 select ARCH_T1040 238 select BOARD_LATE_INIT if CHAIN_OF_TRUST 239 select SUPPORT_SPL 240 select PHYS_64BIT 241 242config TARGET_T1040D4RDB 243 bool "Support T1040D4RDB" 244 select ARCH_T1040 245 select BOARD_LATE_INIT if CHAIN_OF_TRUST 246 select SUPPORT_SPL 247 select PHYS_64BIT 248 249config TARGET_T1042RDB 250 bool "Support T1042RDB" 251 select ARCH_T1042 252 select BOARD_LATE_INIT if CHAIN_OF_TRUST 253 select SUPPORT_SPL 254 select PHYS_64BIT 255 256config TARGET_T1042D4RDB 257 bool "Support T1042D4RDB" 258 select ARCH_T1042 259 select BOARD_LATE_INIT if CHAIN_OF_TRUST 260 select SUPPORT_SPL 261 select PHYS_64BIT 262 263config TARGET_T1042RDB_PI 264 bool "Support T1042RDB_PI" 265 select ARCH_T1042 266 select BOARD_LATE_INIT if CHAIN_OF_TRUST 267 select SUPPORT_SPL 268 select PHYS_64BIT 269 270config TARGET_T2080QDS 271 bool "Support T2080QDS" 272 select ARCH_T2080 273 select BOARD_LATE_INIT if CHAIN_OF_TRUST 274 select SUPPORT_SPL 275 select PHYS_64BIT 276 277config TARGET_T2080RDB 278 bool "Support T2080RDB" 279 select ARCH_T2080 280 select BOARD_LATE_INIT if CHAIN_OF_TRUST 281 select SUPPORT_SPL 282 select PHYS_64BIT 283 284config TARGET_T2081QDS 285 bool "Support T2081QDS" 286 select ARCH_T2081 287 select SUPPORT_SPL 288 select PHYS_64BIT 289 290config TARGET_T4160QDS 291 bool "Support T4160QDS" 292 select ARCH_T4160 293 select BOARD_LATE_INIT if CHAIN_OF_TRUST 294 select SUPPORT_SPL 295 select PHYS_64BIT 296 297config TARGET_T4160RDB 298 bool "Support T4160RDB" 299 select ARCH_T4160 300 select SUPPORT_SPL 301 select PHYS_64BIT 302 303config TARGET_T4240QDS 304 bool "Support T4240QDS" 305 select ARCH_T4240 306 select BOARD_LATE_INIT if CHAIN_OF_TRUST 307 select SUPPORT_SPL 308 select PHYS_64BIT 309 310config TARGET_T4240RDB 311 bool "Support T4240RDB" 312 select ARCH_T4240 313 select SUPPORT_SPL 314 select PHYS_64BIT 315 316config TARGET_CONTROLCENTERD 317 bool "Support controlcenterd" 318 select ARCH_P1022 319 320config TARGET_KMP204X 321 bool "Support kmp204x" 322 select ARCH_P2041 323 select PHYS_64BIT 324 325config TARGET_XPEDITE520X 326 bool "Support xpedite520x" 327 select ARCH_MPC8548 328 329config TARGET_XPEDITE537X 330 bool "Support xpedite537x" 331 select ARCH_MPC8572 332# Use DDR3 controller with DDR2 DIMMs on this board 333 select SYS_FSL_DDRC_GEN3 334 335config TARGET_XPEDITE550X 336 bool "Support xpedite550x" 337 select ARCH_P2020 338 339config TARGET_UCP1020 340 bool "Support uCP1020" 341 select ARCH_P1020 342 343config TARGET_CYRUS_P5020 344 bool "Support Varisys Cyrus P5020" 345 select ARCH_P5020 346 select PHYS_64BIT 347 348config TARGET_CYRUS_P5040 349 bool "Support Varisys Cyrus P5040" 350 select ARCH_P5040 351 select PHYS_64BIT 352 353endchoice 354 355config ARCH_B4420 356 bool 357 select E500MC 358 select E6500 359 select FSL_LAW 360 select SYS_FSL_DDR_VER_47 361 select SYS_FSL_ERRATUM_A004477 362 select SYS_FSL_ERRATUM_A005871 363 select SYS_FSL_ERRATUM_A006379 364 select SYS_FSL_ERRATUM_A006384 365 select SYS_FSL_ERRATUM_A006475 366 select SYS_FSL_ERRATUM_A006593 367 select SYS_FSL_ERRATUM_A007075 368 select SYS_FSL_ERRATUM_A007186 369 select SYS_FSL_ERRATUM_A007212 370 select SYS_FSL_ERRATUM_A009942 371 select SYS_FSL_HAS_DDR3 372 select SYS_FSL_HAS_SEC 373 select SYS_FSL_QORIQ_CHASSIS2 374 select SYS_FSL_SEC_BE 375 select SYS_FSL_SEC_COMPAT_4 376 select SYS_PPC64 377 378config ARCH_B4860 379 bool 380 select E500MC 381 select E6500 382 select FSL_LAW 383 select SYS_FSL_DDR_VER_47 384 select SYS_FSL_ERRATUM_A004477 385 select SYS_FSL_ERRATUM_A005871 386 select SYS_FSL_ERRATUM_A006379 387 select SYS_FSL_ERRATUM_A006384 388 select SYS_FSL_ERRATUM_A006475 389 select SYS_FSL_ERRATUM_A006593 390 select SYS_FSL_ERRATUM_A007075 391 select SYS_FSL_ERRATUM_A007186 392 select SYS_FSL_ERRATUM_A007212 393 select SYS_FSL_ERRATUM_A009942 394 select SYS_FSL_HAS_DDR3 395 select SYS_FSL_HAS_SEC 396 select SYS_FSL_QORIQ_CHASSIS2 397 select SYS_FSL_SEC_BE 398 select SYS_FSL_SEC_COMPAT_4 399 select SYS_PPC64 400 401config ARCH_BSC9131 402 bool 403 select FSL_LAW 404 select SYS_FSL_DDR_VER_44 405 select SYS_FSL_ERRATUM_A004477 406 select SYS_FSL_ERRATUM_A005125 407 select SYS_FSL_ERRATUM_ESDHC111 408 select SYS_FSL_HAS_DDR3 409 select SYS_FSL_HAS_SEC 410 select SYS_FSL_SEC_BE 411 select SYS_FSL_SEC_COMPAT_4 412 413config ARCH_BSC9132 414 bool 415 select FSL_LAW 416 select SYS_FSL_DDR_VER_46 417 select SYS_FSL_ERRATUM_A004477 418 select SYS_FSL_ERRATUM_A005125 419 select SYS_FSL_ERRATUM_A005434 420 select SYS_FSL_ERRATUM_ESDHC111 421 select SYS_FSL_ERRATUM_I2C_A004447 422 select SYS_FSL_ERRATUM_IFC_A002769 423 select SYS_FSL_HAS_DDR3 424 select SYS_FSL_HAS_SEC 425 select SYS_FSL_SEC_BE 426 select SYS_FSL_SEC_COMPAT_4 427 select SYS_PPC_E500_USE_DEBUG_TLB 428 429config ARCH_C29X 430 bool 431 select FSL_LAW 432 select SYS_FSL_DDR_VER_46 433 select SYS_FSL_ERRATUM_A005125 434 select SYS_FSL_ERRATUM_ESDHC111 435 select SYS_FSL_HAS_DDR3 436 select SYS_FSL_HAS_SEC 437 select SYS_FSL_SEC_BE 438 select SYS_FSL_SEC_COMPAT_6 439 select SYS_PPC_E500_USE_DEBUG_TLB 440 441config ARCH_MPC8536 442 bool 443 select FSL_LAW 444 select SYS_FSL_ERRATUM_A004508 445 select SYS_FSL_ERRATUM_A005125 446 select SYS_FSL_HAS_DDR2 447 select SYS_FSL_HAS_DDR3 448 select SYS_FSL_HAS_SEC 449 select SYS_FSL_SEC_BE 450 select SYS_FSL_SEC_COMPAT_2 451 select SYS_PPC_E500_USE_DEBUG_TLB 452 453config ARCH_MPC8540 454 bool 455 select FSL_LAW 456 select SYS_FSL_HAS_DDR1 457 458config ARCH_MPC8541 459 bool 460 select FSL_LAW 461 select SYS_FSL_HAS_DDR1 462 select SYS_FSL_HAS_SEC 463 select SYS_FSL_SEC_BE 464 select SYS_FSL_SEC_COMPAT_2 465 466config ARCH_MPC8544 467 bool 468 select FSL_LAW 469 select SYS_FSL_ERRATUM_A005125 470 select SYS_FSL_HAS_DDR2 471 select SYS_FSL_HAS_SEC 472 select SYS_FSL_SEC_BE 473 select SYS_FSL_SEC_COMPAT_2 474 select SYS_PPC_E500_USE_DEBUG_TLB 475 476config ARCH_MPC8548 477 bool 478 select FSL_LAW 479 select SYS_FSL_ERRATUM_A005125 480 select SYS_FSL_ERRATUM_NMG_DDR120 481 select SYS_FSL_ERRATUM_NMG_LBC103 482 select SYS_FSL_ERRATUM_NMG_ETSEC129 483 select SYS_FSL_ERRATUM_I2C_A004447 484 select SYS_FSL_HAS_DDR2 485 select SYS_FSL_HAS_DDR1 486 select SYS_FSL_HAS_SEC 487 select SYS_FSL_SEC_BE 488 select SYS_FSL_SEC_COMPAT_2 489 select SYS_PPC_E500_USE_DEBUG_TLB 490 491config ARCH_MPC8555 492 bool 493 select FSL_LAW 494 select SYS_FSL_HAS_DDR1 495 select SYS_FSL_HAS_SEC 496 select SYS_FSL_SEC_BE 497 select SYS_FSL_SEC_COMPAT_2 498 499config ARCH_MPC8560 500 bool 501 select FSL_LAW 502 select SYS_FSL_HAS_DDR1 503 504config ARCH_MPC8568 505 bool 506 select FSL_LAW 507 select SYS_FSL_HAS_DDR2 508 select SYS_FSL_HAS_SEC 509 select SYS_FSL_SEC_BE 510 select SYS_FSL_SEC_COMPAT_2 511 512config ARCH_MPC8569 513 bool 514 select FSL_LAW 515 select SYS_FSL_ERRATUM_A004508 516 select SYS_FSL_ERRATUM_A005125 517 select SYS_FSL_HAS_DDR3 518 select SYS_FSL_HAS_SEC 519 select SYS_FSL_SEC_BE 520 select SYS_FSL_SEC_COMPAT_2 521 522config ARCH_MPC8572 523 bool 524 select FSL_LAW 525 select SYS_FSL_ERRATUM_A004508 526 select SYS_FSL_ERRATUM_A005125 527 select SYS_FSL_ERRATUM_DDR_115 528 select SYS_FSL_ERRATUM_DDR111_DDR134 529 select SYS_FSL_HAS_DDR2 530 select SYS_FSL_HAS_DDR3 531 select SYS_FSL_HAS_SEC 532 select SYS_FSL_SEC_BE 533 select SYS_FSL_SEC_COMPAT_2 534 select SYS_PPC_E500_USE_DEBUG_TLB 535 536config ARCH_P1010 537 bool 538 select FSL_LAW 539 select SYS_FSL_ERRATUM_A004477 540 select SYS_FSL_ERRATUM_A004508 541 select SYS_FSL_ERRATUM_A005125 542 select SYS_FSL_ERRATUM_A006261 543 select SYS_FSL_ERRATUM_A007075 544 select SYS_FSL_ERRATUM_ESDHC111 545 select SYS_FSL_ERRATUM_I2C_A004447 546 select SYS_FSL_ERRATUM_IFC_A002769 547 select SYS_FSL_ERRATUM_P1010_A003549 548 select SYS_FSL_ERRATUM_SEC_A003571 549 select SYS_FSL_ERRATUM_IFC_A003399 550 select SYS_FSL_HAS_DDR3 551 select SYS_FSL_HAS_SEC 552 select SYS_FSL_SEC_BE 553 select SYS_FSL_SEC_COMPAT_4 554 select SYS_PPC_E500_USE_DEBUG_TLB 555 556config ARCH_P1011 557 bool 558 select FSL_LAW 559 select SYS_FSL_ERRATUM_A004508 560 select SYS_FSL_ERRATUM_A005125 561 select SYS_FSL_ERRATUM_ELBC_A001 562 select SYS_FSL_ERRATUM_ESDHC111 563 select SYS_FSL_HAS_DDR3 564 select SYS_FSL_HAS_SEC 565 select SYS_FSL_SEC_BE 566 select SYS_FSL_SEC_COMPAT_2 567 select SYS_PPC_E500_USE_DEBUG_TLB 568 569config ARCH_P1020 570 bool 571 select FSL_LAW 572 select SYS_FSL_ERRATUM_A004508 573 select SYS_FSL_ERRATUM_A005125 574 select SYS_FSL_ERRATUM_ELBC_A001 575 select SYS_FSL_ERRATUM_ESDHC111 576 select SYS_FSL_HAS_DDR3 577 select SYS_FSL_HAS_SEC 578 select SYS_FSL_SEC_BE 579 select SYS_FSL_SEC_COMPAT_2 580 select SYS_PPC_E500_USE_DEBUG_TLB 581 582config ARCH_P1021 583 bool 584 select FSL_LAW 585 select SYS_FSL_ERRATUM_A004508 586 select SYS_FSL_ERRATUM_A005125 587 select SYS_FSL_ERRATUM_ELBC_A001 588 select SYS_FSL_ERRATUM_ESDHC111 589 select SYS_FSL_HAS_DDR3 590 select SYS_FSL_HAS_SEC 591 select SYS_FSL_SEC_BE 592 select SYS_FSL_SEC_COMPAT_2 593 select SYS_PPC_E500_USE_DEBUG_TLB 594 595config ARCH_P1022 596 bool 597 select FSL_LAW 598 select SYS_FSL_ERRATUM_A004477 599 select SYS_FSL_ERRATUM_A004508 600 select SYS_FSL_ERRATUM_A005125 601 select SYS_FSL_ERRATUM_ELBC_A001 602 select SYS_FSL_ERRATUM_ESDHC111 603 select SYS_FSL_ERRATUM_SATA_A001 604 select SYS_FSL_HAS_DDR3 605 select SYS_FSL_HAS_SEC 606 select SYS_FSL_SEC_BE 607 select SYS_FSL_SEC_COMPAT_2 608 select SYS_PPC_E500_USE_DEBUG_TLB 609 610config ARCH_P1023 611 bool 612 select FSL_LAW 613 select SYS_FSL_ERRATUM_A004508 614 select SYS_FSL_ERRATUM_A005125 615 select SYS_FSL_ERRATUM_I2C_A004447 616 select SYS_FSL_HAS_DDR3 617 select SYS_FSL_HAS_SEC 618 select SYS_FSL_SEC_BE 619 select SYS_FSL_SEC_COMPAT_4 620 621config ARCH_P1024 622 bool 623 select FSL_LAW 624 select SYS_FSL_ERRATUM_A004508 625 select SYS_FSL_ERRATUM_A005125 626 select SYS_FSL_ERRATUM_ELBC_A001 627 select SYS_FSL_ERRATUM_ESDHC111 628 select SYS_FSL_HAS_DDR3 629 select SYS_FSL_HAS_SEC 630 select SYS_FSL_SEC_BE 631 select SYS_FSL_SEC_COMPAT_2 632 select SYS_PPC_E500_USE_DEBUG_TLB 633 634config ARCH_P1025 635 bool 636 select FSL_LAW 637 select SYS_FSL_ERRATUM_A004508 638 select SYS_FSL_ERRATUM_A005125 639 select SYS_FSL_ERRATUM_ELBC_A001 640 select SYS_FSL_ERRATUM_ESDHC111 641 select SYS_FSL_HAS_DDR3 642 select SYS_FSL_HAS_SEC 643 select SYS_FSL_SEC_BE 644 select SYS_FSL_SEC_COMPAT_2 645 select SYS_PPC_E500_USE_DEBUG_TLB 646 647config ARCH_P2020 648 bool 649 select FSL_LAW 650 select SYS_FSL_ERRATUM_A004477 651 select SYS_FSL_ERRATUM_A004508 652 select SYS_FSL_ERRATUM_A005125 653 select SYS_FSL_ERRATUM_ESDHC111 654 select SYS_FSL_ERRATUM_ESDHC_A001 655 select SYS_FSL_HAS_DDR3 656 select SYS_FSL_HAS_SEC 657 select SYS_FSL_SEC_BE 658 select SYS_FSL_SEC_COMPAT_2 659 select SYS_PPC_E500_USE_DEBUG_TLB 660 661config ARCH_P2041 662 bool 663 select E500MC 664 select FSL_LAW 665 select SYS_FSL_ERRATUM_A004510 666 select SYS_FSL_ERRATUM_A004849 667 select SYS_FSL_ERRATUM_A006261 668 select SYS_FSL_ERRATUM_CPU_A003999 669 select SYS_FSL_ERRATUM_DDR_A003 670 select SYS_FSL_ERRATUM_DDR_A003474 671 select SYS_FSL_ERRATUM_ESDHC111 672 select SYS_FSL_ERRATUM_I2C_A004447 673 select SYS_FSL_ERRATUM_NMG_CPU_A011 674 select SYS_FSL_ERRATUM_SRIO_A004034 675 select SYS_FSL_ERRATUM_USB14 676 select SYS_FSL_HAS_DDR3 677 select SYS_FSL_HAS_SEC 678 select SYS_FSL_QORIQ_CHASSIS1 679 select SYS_FSL_SEC_BE 680 select SYS_FSL_SEC_COMPAT_4 681 682config ARCH_P3041 683 bool 684 select E500MC 685 select FSL_LAW 686 select SYS_FSL_DDR_VER_44 687 select SYS_FSL_ERRATUM_A004510 688 select SYS_FSL_ERRATUM_A004849 689 select SYS_FSL_ERRATUM_A005812 690 select SYS_FSL_ERRATUM_A006261 691 select SYS_FSL_ERRATUM_CPU_A003999 692 select SYS_FSL_ERRATUM_DDR_A003 693 select SYS_FSL_ERRATUM_DDR_A003474 694 select SYS_FSL_ERRATUM_ESDHC111 695 select SYS_FSL_ERRATUM_I2C_A004447 696 select SYS_FSL_ERRATUM_NMG_CPU_A011 697 select SYS_FSL_ERRATUM_SRIO_A004034 698 select SYS_FSL_ERRATUM_USB14 699 select SYS_FSL_HAS_DDR3 700 select SYS_FSL_HAS_SEC 701 select SYS_FSL_QORIQ_CHASSIS1 702 select SYS_FSL_SEC_BE 703 select SYS_FSL_SEC_COMPAT_4 704 705config ARCH_P4080 706 bool 707 select E500MC 708 select FSL_LAW 709 select SYS_FSL_DDR_VER_44 710 select SYS_FSL_ERRATUM_A004510 711 select SYS_FSL_ERRATUM_A004580 712 select SYS_FSL_ERRATUM_A004849 713 select SYS_FSL_ERRATUM_A005812 714 select SYS_FSL_ERRATUM_A007075 715 select SYS_FSL_ERRATUM_CPC_A002 716 select SYS_FSL_ERRATUM_CPC_A003 717 select SYS_FSL_ERRATUM_CPU_A003999 718 select SYS_FSL_ERRATUM_DDR_A003 719 select SYS_FSL_ERRATUM_DDR_A003474 720 select SYS_FSL_ERRATUM_ELBC_A001 721 select SYS_FSL_ERRATUM_ESDHC111 722 select SYS_FSL_ERRATUM_ESDHC13 723 select SYS_FSL_ERRATUM_ESDHC135 724 select SYS_FSL_ERRATUM_I2C_A004447 725 select SYS_FSL_ERRATUM_NMG_CPU_A011 726 select SYS_FSL_ERRATUM_SRIO_A004034 727 select SYS_P4080_ERRATUM_CPU22 728 select SYS_P4080_ERRATUM_PCIE_A003 729 select SYS_P4080_ERRATUM_SERDES8 730 select SYS_P4080_ERRATUM_SERDES9 731 select SYS_P4080_ERRATUM_SERDES_A001 732 select SYS_P4080_ERRATUM_SERDES_A005 733 select SYS_FSL_HAS_DDR3 734 select SYS_FSL_HAS_SEC 735 select SYS_FSL_QORIQ_CHASSIS1 736 select SYS_FSL_SEC_BE 737 select SYS_FSL_SEC_COMPAT_4 738 739config ARCH_P5020 740 bool 741 select E500MC 742 select FSL_LAW 743 select SYS_FSL_DDR_VER_44 744 select SYS_FSL_ERRATUM_A004510 745 select SYS_FSL_ERRATUM_A006261 746 select SYS_FSL_ERRATUM_DDR_A003 747 select SYS_FSL_ERRATUM_DDR_A003474 748 select SYS_FSL_ERRATUM_ESDHC111 749 select SYS_FSL_ERRATUM_I2C_A004447 750 select SYS_FSL_ERRATUM_SRIO_A004034 751 select SYS_FSL_ERRATUM_USB14 752 select SYS_FSL_HAS_DDR3 753 select SYS_FSL_HAS_SEC 754 select SYS_FSL_QORIQ_CHASSIS1 755 select SYS_FSL_SEC_BE 756 select SYS_FSL_SEC_COMPAT_4 757 select SYS_PPC64 758 759config ARCH_P5040 760 bool 761 select E500MC 762 select FSL_LAW 763 select SYS_FSL_DDR_VER_44 764 select SYS_FSL_ERRATUM_A004510 765 select SYS_FSL_ERRATUM_A004699 766 select SYS_FSL_ERRATUM_A005812 767 select SYS_FSL_ERRATUM_A006261 768 select SYS_FSL_ERRATUM_DDR_A003 769 select SYS_FSL_ERRATUM_DDR_A003474 770 select SYS_FSL_ERRATUM_ESDHC111 771 select SYS_FSL_ERRATUM_USB14 772 select SYS_FSL_HAS_DDR3 773 select SYS_FSL_HAS_SEC 774 select SYS_FSL_QORIQ_CHASSIS1 775 select SYS_FSL_SEC_BE 776 select SYS_FSL_SEC_COMPAT_4 777 select SYS_PPC64 778 779config ARCH_QEMU_E500 780 bool 781 782config ARCH_T1023 783 bool 784 select E500MC 785 select FSL_LAW 786 select SYS_FSL_DDR_VER_50 787 select SYS_FSL_ERRATUM_A008378 788 select SYS_FSL_ERRATUM_A009663 789 select SYS_FSL_ERRATUM_A009942 790 select SYS_FSL_ERRATUM_ESDHC111 791 select SYS_FSL_HAS_DDR3 792 select SYS_FSL_HAS_DDR4 793 select SYS_FSL_HAS_SEC 794 select SYS_FSL_QORIQ_CHASSIS2 795 select SYS_FSL_SEC_BE 796 select SYS_FSL_SEC_COMPAT_5 797 798config ARCH_T1024 799 bool 800 select E500MC 801 select FSL_LAW 802 select SYS_FSL_DDR_VER_50 803 select SYS_FSL_ERRATUM_A008378 804 select SYS_FSL_ERRATUM_A009663 805 select SYS_FSL_ERRATUM_A009942 806 select SYS_FSL_ERRATUM_ESDHC111 807 select SYS_FSL_HAS_DDR3 808 select SYS_FSL_HAS_DDR4 809 select SYS_FSL_HAS_SEC 810 select SYS_FSL_QORIQ_CHASSIS2 811 select SYS_FSL_SEC_BE 812 select SYS_FSL_SEC_COMPAT_5 813 814config ARCH_T1040 815 bool 816 select E500MC 817 select FSL_LAW 818 select SYS_FSL_DDR_VER_50 819 select SYS_FSL_ERRATUM_A008044 820 select SYS_FSL_ERRATUM_A008378 821 select SYS_FSL_ERRATUM_A009663 822 select SYS_FSL_ERRATUM_A009942 823 select SYS_FSL_ERRATUM_ESDHC111 824 select SYS_FSL_HAS_DDR3 825 select SYS_FSL_HAS_DDR4 826 select SYS_FSL_HAS_SEC 827 select SYS_FSL_QORIQ_CHASSIS2 828 select SYS_FSL_SEC_BE 829 select SYS_FSL_SEC_COMPAT_5 830 831config ARCH_T1042 832 bool 833 select E500MC 834 select FSL_LAW 835 select SYS_FSL_DDR_VER_50 836 select SYS_FSL_ERRATUM_A008044 837 select SYS_FSL_ERRATUM_A008378 838 select SYS_FSL_ERRATUM_A009663 839 select SYS_FSL_ERRATUM_A009942 840 select SYS_FSL_ERRATUM_ESDHC111 841 select SYS_FSL_HAS_DDR3 842 select SYS_FSL_HAS_DDR4 843 select SYS_FSL_HAS_SEC 844 select SYS_FSL_QORIQ_CHASSIS2 845 select SYS_FSL_SEC_BE 846 select SYS_FSL_SEC_COMPAT_5 847 848config ARCH_T2080 849 bool 850 select E500MC 851 select E6500 852 select FSL_LAW 853 select SYS_FSL_DDR_VER_47 854 select SYS_FSL_ERRATUM_A006379 855 select SYS_FSL_ERRATUM_A006593 856 select SYS_FSL_ERRATUM_A007186 857 select SYS_FSL_ERRATUM_A007212 858 select SYS_FSL_ERRATUM_A009942 859 select SYS_FSL_ERRATUM_ESDHC111 860 select SYS_FSL_HAS_DDR3 861 select SYS_FSL_HAS_SEC 862 select SYS_FSL_QORIQ_CHASSIS2 863 select SYS_FSL_SEC_BE 864 select SYS_FSL_SEC_COMPAT_4 865 select SYS_PPC64 866 867config ARCH_T2081 868 bool 869 select E500MC 870 select E6500 871 select FSL_LAW 872 select SYS_FSL_DDR_VER_47 873 select SYS_FSL_ERRATUM_A006379 874 select SYS_FSL_ERRATUM_A006593 875 select SYS_FSL_ERRATUM_A007186 876 select SYS_FSL_ERRATUM_A007212 877 select SYS_FSL_ERRATUM_A009942 878 select SYS_FSL_ERRATUM_ESDHC111 879 select SYS_FSL_HAS_DDR3 880 select SYS_FSL_HAS_SEC 881 select SYS_FSL_QORIQ_CHASSIS2 882 select SYS_FSL_SEC_BE 883 select SYS_FSL_SEC_COMPAT_4 884 select SYS_PPC64 885 886config ARCH_T4160 887 bool 888 select E500MC 889 select E6500 890 select FSL_LAW 891 select SYS_FSL_DDR_VER_47 892 select SYS_FSL_ERRATUM_A004468 893 select SYS_FSL_ERRATUM_A005871 894 select SYS_FSL_ERRATUM_A006379 895 select SYS_FSL_ERRATUM_A006593 896 select SYS_FSL_ERRATUM_A007186 897 select SYS_FSL_ERRATUM_A007798 898 select SYS_FSL_ERRATUM_A009942 899 select SYS_FSL_HAS_DDR3 900 select SYS_FSL_HAS_SEC 901 select SYS_FSL_QORIQ_CHASSIS2 902 select SYS_FSL_SEC_BE 903 select SYS_FSL_SEC_COMPAT_4 904 select SYS_PPC64 905 906config ARCH_T4240 907 bool 908 select E500MC 909 select E6500 910 select FSL_LAW 911 select SYS_FSL_DDR_VER_47 912 select SYS_FSL_ERRATUM_A004468 913 select SYS_FSL_ERRATUM_A005871 914 select SYS_FSL_ERRATUM_A006261 915 select SYS_FSL_ERRATUM_A006379 916 select SYS_FSL_ERRATUM_A006593 917 select SYS_FSL_ERRATUM_A007186 918 select SYS_FSL_ERRATUM_A007798 919 select SYS_FSL_ERRATUM_A009942 920 select SYS_FSL_HAS_DDR3 921 select SYS_FSL_HAS_SEC 922 select SYS_FSL_QORIQ_CHASSIS2 923 select SYS_FSL_SEC_BE 924 select SYS_FSL_SEC_COMPAT_4 925 select SYS_PPC64 926 927config BOOKE 928 bool 929 default y 930 931config E500 932 bool 933 default y 934 help 935 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 936 937config E500MC 938 bool 939 help 940 Enble PowerPC E500MC core 941 942config E6500 943 bool 944 help 945 Enable PowerPC E6500 core 946 947config FSL_LAW 948 bool 949 help 950 Use Freescale common code for Local Access Window 951 952config SECURE_BOOT 953 bool "Secure Boot" 954 help 955 Enable Freescale Secure Boot feature. Normally selected 956 by defconfig. If unsure, do not change. 957 958config MAX_CPUS 959 int "Maximum number of CPUs permitted for MPC85xx" 960 default 12 if ARCH_T4240 961 default 8 if ARCH_P4080 || \ 962 ARCH_T4160 963 default 4 if ARCH_B4860 || \ 964 ARCH_P2041 || \ 965 ARCH_P3041 || \ 966 ARCH_P5040 || \ 967 ARCH_T1040 || \ 968 ARCH_T1042 || \ 969 ARCH_T2080 || \ 970 ARCH_T2081 971 default 2 if ARCH_B4420 || \ 972 ARCH_BSC9132 || \ 973 ARCH_MPC8572 || \ 974 ARCH_P1020 || \ 975 ARCH_P1021 || \ 976 ARCH_P1022 || \ 977 ARCH_P1023 || \ 978 ARCH_P1024 || \ 979 ARCH_P1025 || \ 980 ARCH_P2020 || \ 981 ARCH_P5020 || \ 982 ARCH_T1023 || \ 983 ARCH_T1024 984 default 1 985 help 986 Set this number to the maximum number of possible CPUs in the SoC. 987 SoCs may have multiple clusters with each cluster may have multiple 988 ports. If some ports are reserved but higher ports are used for 989 cores, count the reserved ports. This will allocate enough memory 990 in spin table to properly handle all cores. 991 992config SYS_CCSRBAR_DEFAULT 993 hex "Default CCSRBAR address" 994 default 0xff700000 if ARCH_BSC9131 || \ 995 ARCH_BSC9132 || \ 996 ARCH_C29X || \ 997 ARCH_MPC8536 || \ 998 ARCH_MPC8540 || \ 999 ARCH_MPC8541 || \ 1000 ARCH_MPC8544 || \ 1001 ARCH_MPC8548 || \ 1002 ARCH_MPC8555 || \ 1003 ARCH_MPC8560 || \ 1004 ARCH_MPC8568 || \ 1005 ARCH_MPC8569 || \ 1006 ARCH_MPC8572 || \ 1007 ARCH_P1010 || \ 1008 ARCH_P1011 || \ 1009 ARCH_P1020 || \ 1010 ARCH_P1021 || \ 1011 ARCH_P1022 || \ 1012 ARCH_P1024 || \ 1013 ARCH_P1025 || \ 1014 ARCH_P2020 1015 default 0xff600000 if ARCH_P1023 1016 default 0xfe000000 if ARCH_B4420 || \ 1017 ARCH_B4860 || \ 1018 ARCH_P2041 || \ 1019 ARCH_P3041 || \ 1020 ARCH_P4080 || \ 1021 ARCH_P5020 || \ 1022 ARCH_P5040 || \ 1023 ARCH_T1023 || \ 1024 ARCH_T1024 || \ 1025 ARCH_T1040 || \ 1026 ARCH_T1042 || \ 1027 ARCH_T2080 || \ 1028 ARCH_T2081 || \ 1029 ARCH_T4160 || \ 1030 ARCH_T4240 1031 default 0xe0000000 if ARCH_QEMU_E500 1032 help 1033 Default value of CCSRBAR comes from power-on-reset. It 1034 is fixed on each SoC. Some SoCs can have different value 1035 if changed by pre-boot regime. The value here must match 1036 the current value in SoC. If not sure, do not change. 1037 1038config SYS_FSL_ERRATUM_A004468 1039 bool 1040 1041config SYS_FSL_ERRATUM_A004477 1042 bool 1043 1044config SYS_FSL_ERRATUM_A004508 1045 bool 1046 1047config SYS_FSL_ERRATUM_A004580 1048 bool 1049 1050config SYS_FSL_ERRATUM_A004699 1051 bool 1052 1053config SYS_FSL_ERRATUM_A004849 1054 bool 1055 1056config SYS_FSL_ERRATUM_A004510 1057 bool 1058 1059config SYS_FSL_ERRATUM_A004510_SVR_REV 1060 hex 1061 depends on SYS_FSL_ERRATUM_A004510 1062 default 0x20 if ARCH_P4080 1063 default 0x10 1064 1065config SYS_FSL_ERRATUM_A004510_SVR_REV2 1066 hex 1067 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1068 default 0x11 1069 1070config SYS_FSL_ERRATUM_A005125 1071 bool 1072 1073config SYS_FSL_ERRATUM_A005434 1074 bool 1075 1076config SYS_FSL_ERRATUM_A005812 1077 bool 1078 1079config SYS_FSL_ERRATUM_A005871 1080 bool 1081 1082config SYS_FSL_ERRATUM_A006261 1083 bool 1084 1085config SYS_FSL_ERRATUM_A006379 1086 bool 1087 1088config SYS_FSL_ERRATUM_A006384 1089 bool 1090 1091config SYS_FSL_ERRATUM_A006475 1092 bool 1093 1094config SYS_FSL_ERRATUM_A006593 1095 bool 1096 1097config SYS_FSL_ERRATUM_A007075 1098 bool 1099 1100config SYS_FSL_ERRATUM_A007186 1101 bool 1102 1103config SYS_FSL_ERRATUM_A007212 1104 bool 1105 1106config SYS_FSL_ERRATUM_A007798 1107 bool 1108 1109config SYS_FSL_ERRATUM_A008044 1110 bool 1111 1112config SYS_FSL_ERRATUM_CPC_A002 1113 bool 1114 1115config SYS_FSL_ERRATUM_CPC_A003 1116 bool 1117 1118config SYS_FSL_ERRATUM_CPU_A003999 1119 bool 1120 1121config SYS_FSL_ERRATUM_ELBC_A001 1122 bool 1123 1124config SYS_FSL_ERRATUM_I2C_A004447 1125 bool 1126 1127config SYS_FSL_A004447_SVR_REV 1128 hex 1129 depends on SYS_FSL_ERRATUM_I2C_A004447 1130 default 0x00 if ARCH_MPC8548 1131 default 0x10 if ARCH_P1010 1132 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1133 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1134 1135config SYS_FSL_ERRATUM_IFC_A002769 1136 bool 1137 1138config SYS_FSL_ERRATUM_IFC_A003399 1139 bool 1140 1141config SYS_FSL_ERRATUM_NMG_CPU_A011 1142 bool 1143 1144config SYS_FSL_ERRATUM_NMG_ETSEC129 1145 bool 1146 1147config SYS_FSL_ERRATUM_NMG_LBC103 1148 bool 1149 1150config SYS_FSL_ERRATUM_P1010_A003549 1151 bool 1152 1153config SYS_FSL_ERRATUM_SATA_A001 1154 bool 1155 1156config SYS_FSL_ERRATUM_SEC_A003571 1157 bool 1158 1159config SYS_FSL_ERRATUM_SRIO_A004034 1160 bool 1161 1162config SYS_FSL_ERRATUM_USB14 1163 bool 1164 1165config SYS_P4080_ERRATUM_CPU22 1166 bool 1167 1168config SYS_P4080_ERRATUM_PCIE_A003 1169 bool 1170 1171config SYS_P4080_ERRATUM_SERDES8 1172 bool 1173 1174config SYS_P4080_ERRATUM_SERDES9 1175 bool 1176 1177config SYS_P4080_ERRATUM_SERDES_A001 1178 bool 1179 1180config SYS_P4080_ERRATUM_SERDES_A005 1181 bool 1182 1183config SYS_FSL_QORIQ_CHASSIS1 1184 bool 1185 1186config SYS_FSL_QORIQ_CHASSIS2 1187 bool 1188 1189config SYS_FSL_NUM_LAWS 1190 int "Number of local access windows" 1191 depends on FSL_LAW 1192 default 32 if ARCH_B4420 || \ 1193 ARCH_B4860 || \ 1194 ARCH_P2041 || \ 1195 ARCH_P3041 || \ 1196 ARCH_P4080 || \ 1197 ARCH_P5020 || \ 1198 ARCH_P5040 || \ 1199 ARCH_T2080 || \ 1200 ARCH_T2081 || \ 1201 ARCH_T4160 || \ 1202 ARCH_T4240 1203 default 16 if ARCH_T1023 || \ 1204 ARCH_T1024 || \ 1205 ARCH_T1040 || \ 1206 ARCH_T1042 1207 default 12 if ARCH_BSC9131 || \ 1208 ARCH_BSC9132 || \ 1209 ARCH_C29X || \ 1210 ARCH_MPC8536 || \ 1211 ARCH_MPC8572 || \ 1212 ARCH_P1010 || \ 1213 ARCH_P1011 || \ 1214 ARCH_P1020 || \ 1215 ARCH_P1021 || \ 1216 ARCH_P1022 || \ 1217 ARCH_P1023 || \ 1218 ARCH_P1024 || \ 1219 ARCH_P1025 || \ 1220 ARCH_P2020 1221 default 10 if ARCH_MPC8544 || \ 1222 ARCH_MPC8548 || \ 1223 ARCH_MPC8568 || \ 1224 ARCH_MPC8569 1225 default 8 if ARCH_MPC8540 || \ 1226 ARCH_MPC8541 || \ 1227 ARCH_MPC8555 || \ 1228 ARCH_MPC8560 1229 help 1230 Number of local access windows. This is fixed per SoC. 1231 If not sure, do not change. 1232 1233config SYS_FSL_THREADS_PER_CORE 1234 int 1235 default 2 if E6500 1236 default 1 1237 1238config SYS_NUM_TLBCAMS 1239 int "Number of TLB CAM entries" 1240 default 64 if E500MC 1241 default 16 1242 help 1243 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1244 16 for other E500 SoCs. 1245 1246config SYS_PPC64 1247 bool 1248 1249config SYS_PPC_E500_USE_DEBUG_TLB 1250 bool 1251 1252config SYS_PPC_E500_DEBUG_TLB 1253 int "Temporary TLB entry for external debugger" 1254 depends on SYS_PPC_E500_USE_DEBUG_TLB 1255 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1256 default 1 if ARCH_MPC8536 1257 default 2 if ARCH_MPC8572 || \ 1258 ARCH_P1011 || \ 1259 ARCH_P1020 || \ 1260 ARCH_P1021 || \ 1261 ARCH_P1022 || \ 1262 ARCH_P1024 || \ 1263 ARCH_P1025 || \ 1264 ARCH_P2020 1265 default 3 if ARCH_P1010 || \ 1266 ARCH_BSC9132 || \ 1267 ARCH_C29X 1268 help 1269 Select a temporary TLB entry to be used during boot to work 1270 around limitations in e500v1 and e500v2 external debugger 1271 support. This reduces the portions of the boot code where 1272 breakpoints and single stepping do not work. The value of this 1273 symbol should be set to the TLB1 entry to be used for this 1274 purpose. If unsure, do not change. 1275 1276source "board/freescale/b4860qds/Kconfig" 1277source "board/freescale/bsc9131rdb/Kconfig" 1278source "board/freescale/bsc9132qds/Kconfig" 1279source "board/freescale/c29xpcie/Kconfig" 1280source "board/freescale/corenet_ds/Kconfig" 1281source "board/freescale/mpc8536ds/Kconfig" 1282source "board/freescale/mpc8540ads/Kconfig" 1283source "board/freescale/mpc8541cds/Kconfig" 1284source "board/freescale/mpc8544ds/Kconfig" 1285source "board/freescale/mpc8548cds/Kconfig" 1286source "board/freescale/mpc8555cds/Kconfig" 1287source "board/freescale/mpc8560ads/Kconfig" 1288source "board/freescale/mpc8568mds/Kconfig" 1289source "board/freescale/mpc8569mds/Kconfig" 1290source "board/freescale/mpc8572ds/Kconfig" 1291source "board/freescale/p1010rdb/Kconfig" 1292source "board/freescale/p1022ds/Kconfig" 1293source "board/freescale/p1023rdb/Kconfig" 1294source "board/freescale/p1_p2_rdb_pc/Kconfig" 1295source "board/freescale/p1_twr/Kconfig" 1296source "board/freescale/p2041rdb/Kconfig" 1297source "board/freescale/qemu-ppce500/Kconfig" 1298source "board/freescale/t102xqds/Kconfig" 1299source "board/freescale/t102xrdb/Kconfig" 1300source "board/freescale/t1040qds/Kconfig" 1301source "board/freescale/t104xrdb/Kconfig" 1302source "board/freescale/t208xqds/Kconfig" 1303source "board/freescale/t208xrdb/Kconfig" 1304source "board/freescale/t4qds/Kconfig" 1305source "board/freescale/t4rdb/Kconfig" 1306source "board/gdsys/p1022/Kconfig" 1307source "board/keymile/kmp204x/Kconfig" 1308source "board/sbc8548/Kconfig" 1309source "board/socrates/Kconfig" 1310source "board/varisys/cyrus/Kconfig" 1311source "board/xes/xpedite520x/Kconfig" 1312source "board/xes/xpedite537x/Kconfig" 1313source "board/xes/xpedite550x/Kconfig" 1314source "board/Arcturus/ucp1020/Kconfig" 1315 1316endmenu 1317