1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_SBC8548 12 bool "Support sbc8548" 13 select ARCH_MPC8548 14 15config TARGET_SOCRATES 16 bool "Support socrates" 17 select ARCH_MPC8544 18 19config TARGET_B4420QDS 20 bool "Support B4420QDS" 21 select ARCH_B4420 22 select SUPPORT_SPL 23 select PHYS_64BIT 24 25config TARGET_B4860QDS 26 bool "Support B4860QDS" 27 select ARCH_B4860 28 select SUPPORT_SPL 29 select PHYS_64BIT 30 31config TARGET_BSC9131RDB 32 bool "Support BSC9131RDB" 33 select ARCH_BSC9131 34 select SUPPORT_SPL 35 36config TARGET_BSC9132QDS 37 bool "Support BSC9132QDS" 38 select ARCH_BSC9132 39 select SUPPORT_SPL 40 41config TARGET_C29XPCIE 42 bool "Support C29XPCIE" 43 select ARCH_C29X 44 select SUPPORT_SPL 45 select SUPPORT_TPL 46 select PHYS_64BIT 47 48config TARGET_P3041DS 49 bool "Support P3041DS" 50 select PHYS_64BIT 51 select ARCH_P3041 52 53config TARGET_P4080DS 54 bool "Support P4080DS" 55 select PHYS_64BIT 56 select ARCH_P4080 57 58config TARGET_P5020DS 59 bool "Support P5020DS" 60 select PHYS_64BIT 61 select ARCH_P5020 62 63config TARGET_P5040DS 64 bool "Support P5040DS" 65 select PHYS_64BIT 66 select ARCH_P5040 67 68config TARGET_MPC8536DS 69 bool "Support MPC8536DS" 70 select ARCH_MPC8536 71# Use DDR3 controller with DDR2 DIMMs on this board 72 select SYS_FSL_DDRC_GEN3 73 74config TARGET_MPC8540ADS 75 bool "Support MPC8540ADS" 76 select ARCH_MPC8540 77 78config TARGET_MPC8541CDS 79 bool "Support MPC8541CDS" 80 select ARCH_MPC8541 81 82config TARGET_MPC8544DS 83 bool "Support MPC8544DS" 84 select ARCH_MPC8544 85 86config TARGET_MPC8548CDS 87 bool "Support MPC8548CDS" 88 select ARCH_MPC8548 89 90config TARGET_MPC8555CDS 91 bool "Support MPC8555CDS" 92 select ARCH_MPC8555 93 94config TARGET_MPC8560ADS 95 bool "Support MPC8560ADS" 96 select ARCH_MPC8560 97 98config TARGET_MPC8568MDS 99 bool "Support MPC8568MDS" 100 select ARCH_MPC8568 101 102config TARGET_MPC8569MDS 103 bool "Support MPC8569MDS" 104 select ARCH_MPC8569 105 106config TARGET_MPC8572DS 107 bool "Support MPC8572DS" 108 select ARCH_MPC8572 109# Use DDR3 controller with DDR2 DIMMs on this board 110 select SYS_FSL_DDRC_GEN3 111 112config TARGET_P1010RDB_PA 113 bool "Support P1010RDB_PA" 114 select ARCH_P1010 115 select SUPPORT_SPL 116 select SUPPORT_TPL 117 118config TARGET_P1010RDB_PB 119 bool "Support P1010RDB_PB" 120 select ARCH_P1010 121 select SUPPORT_SPL 122 select SUPPORT_TPL 123 124config TARGET_P1022DS 125 bool "Support P1022DS" 126 select ARCH_P1022 127 select SUPPORT_SPL 128 select SUPPORT_TPL 129 130config TARGET_P1023RDB 131 bool "Support P1023RDB" 132 select ARCH_P1023 133 134config TARGET_P1020MBG 135 bool "Support P1020MBG-PC" 136 select SUPPORT_SPL 137 select SUPPORT_TPL 138 select ARCH_P1020 139 140config TARGET_P1020RDB_PC 141 bool "Support P1020RDB-PC" 142 select SUPPORT_SPL 143 select SUPPORT_TPL 144 select ARCH_P1020 145 146config TARGET_P1020RDB_PD 147 bool "Support P1020RDB-PD" 148 select SUPPORT_SPL 149 select SUPPORT_TPL 150 select ARCH_P1020 151 152config TARGET_P1020UTM 153 bool "Support P1020UTM" 154 select SUPPORT_SPL 155 select SUPPORT_TPL 156 select ARCH_P1020 157 158config TARGET_P1021RDB 159 bool "Support P1021RDB" 160 select SUPPORT_SPL 161 select SUPPORT_TPL 162 select ARCH_P1021 163 164config TARGET_P1024RDB 165 bool "Support P1024RDB" 166 select SUPPORT_SPL 167 select SUPPORT_TPL 168 select ARCH_P1024 169 170config TARGET_P1025RDB 171 bool "Support P1025RDB" 172 select SUPPORT_SPL 173 select SUPPORT_TPL 174 select ARCH_P1025 175 176config TARGET_P2020RDB 177 bool "Support P2020RDB-PC" 178 select SUPPORT_SPL 179 select SUPPORT_TPL 180 select ARCH_P2020 181 182config TARGET_P1_TWR 183 bool "Support p1_twr" 184 select ARCH_P1025 185 186config TARGET_P2041RDB 187 bool "Support P2041RDB" 188 select ARCH_P2041 189 select PHYS_64BIT 190 191config TARGET_QEMU_PPCE500 192 bool "Support qemu-ppce500" 193 select ARCH_QEMU_E500 194 select PHYS_64BIT 195 196config TARGET_T1024QDS 197 bool "Support T1024QDS" 198 select ARCH_T1024 199 select SUPPORT_SPL 200 select PHYS_64BIT 201 202config TARGET_T1023RDB 203 bool "Support T1023RDB" 204 select ARCH_T1023 205 select SUPPORT_SPL 206 select PHYS_64BIT 207 208config TARGET_T1024RDB 209 bool "Support T1024RDB" 210 select ARCH_T1024 211 select SUPPORT_SPL 212 select PHYS_64BIT 213 214config TARGET_T1040QDS 215 bool "Support T1040QDS" 216 select ARCH_T1040 217 select PHYS_64BIT 218 219config TARGET_T1040RDB 220 bool "Support T1040RDB" 221 select ARCH_T1040 222 select SUPPORT_SPL 223 select PHYS_64BIT 224 225config TARGET_T1040D4RDB 226 bool "Support T1040D4RDB" 227 select ARCH_T1040 228 select SUPPORT_SPL 229 select PHYS_64BIT 230 231config TARGET_T1042RDB 232 bool "Support T1042RDB" 233 select ARCH_T1042 234 select SUPPORT_SPL 235 select PHYS_64BIT 236 237config TARGET_T1042D4RDB 238 bool "Support T1042D4RDB" 239 select ARCH_T1042 240 select SUPPORT_SPL 241 select PHYS_64BIT 242 243config TARGET_T1042RDB_PI 244 bool "Support T1042RDB_PI" 245 select ARCH_T1042 246 select SUPPORT_SPL 247 select PHYS_64BIT 248 249config TARGET_T2080QDS 250 bool "Support T2080QDS" 251 select ARCH_T2080 252 select SUPPORT_SPL 253 select PHYS_64BIT 254 255config TARGET_T2080RDB 256 bool "Support T2080RDB" 257 select ARCH_T2080 258 select SUPPORT_SPL 259 select PHYS_64BIT 260 261config TARGET_T2081QDS 262 bool "Support T2081QDS" 263 select ARCH_T2081 264 select SUPPORT_SPL 265 select PHYS_64BIT 266 267config TARGET_T4160QDS 268 bool "Support T4160QDS" 269 select ARCH_T4160 270 select SUPPORT_SPL 271 select PHYS_64BIT 272 273config TARGET_T4160RDB 274 bool "Support T4160RDB" 275 select ARCH_T4160 276 select SUPPORT_SPL 277 select PHYS_64BIT 278 279config TARGET_T4240QDS 280 bool "Support T4240QDS" 281 select ARCH_T4240 282 select SUPPORT_SPL 283 select PHYS_64BIT 284 285config TARGET_T4240RDB 286 bool "Support T4240RDB" 287 select ARCH_T4240 288 select SUPPORT_SPL 289 select PHYS_64BIT 290 291config TARGET_CONTROLCENTERD 292 bool "Support controlcenterd" 293 select ARCH_P1022 294 295config TARGET_KMP204X 296 bool "Support kmp204x" 297 select ARCH_P2041 298 select PHYS_64BIT 299 300config TARGET_XPEDITE520X 301 bool "Support xpedite520x" 302 select ARCH_MPC8548 303 304config TARGET_XPEDITE537X 305 bool "Support xpedite537x" 306 select ARCH_MPC8572 307# Use DDR3 controller with DDR2 DIMMs on this board 308 select SYS_FSL_DDRC_GEN3 309 310config TARGET_XPEDITE550X 311 bool "Support xpedite550x" 312 select ARCH_P2020 313 314config TARGET_UCP1020 315 bool "Support uCP1020" 316 select ARCH_P1020 317 318config TARGET_CYRUS_P5020 319 bool "Support Varisys Cyrus P5020" 320 select ARCH_P5020 321 select PHYS_64BIT 322 323config TARGET_CYRUS_P5040 324 bool "Support Varisys Cyrus P5040" 325 select ARCH_P5040 326 select PHYS_64BIT 327 328endchoice 329 330config ARCH_B4420 331 bool 332 select E500MC 333 select FSL_LAW 334 select SYS_FSL_HAS_DDR3 335 select SYS_FSL_HAS_SEC 336 select SYS_FSL_SEC_BE 337 select SYS_FSL_SEC_COMPAT_4 338 339config ARCH_B4860 340 bool 341 select E500MC 342 select FSL_LAW 343 select SYS_FSL_HAS_DDR3 344 select SYS_FSL_HAS_SEC 345 select SYS_FSL_SEC_BE 346 select SYS_FSL_SEC_COMPAT_4 347 348config ARCH_BSC9131 349 bool 350 select FSL_LAW 351 select SYS_FSL_ERRATUM_ESDHC111 352 select SYS_FSL_HAS_DDR3 353 select SYS_FSL_HAS_SEC 354 select SYS_FSL_SEC_BE 355 select SYS_FSL_SEC_COMPAT_4 356 357config ARCH_BSC9132 358 bool 359 select FSL_LAW 360 select SYS_FSL_ERRATUM_ESDHC111 361 select SYS_FSL_HAS_DDR3 362 select SYS_FSL_HAS_SEC 363 select SYS_FSL_SEC_BE 364 select SYS_FSL_SEC_COMPAT_4 365 select SYS_PPC_E500_USE_DEBUG_TLB 366 367config ARCH_C29X 368 bool 369 select FSL_LAW 370 select SYS_FSL_ERRATUM_ESDHC111 371 select SYS_FSL_HAS_DDR3 372 select SYS_FSL_HAS_SEC 373 select SYS_FSL_SEC_BE 374 select SYS_FSL_SEC_COMPAT_6 375 select SYS_PPC_E500_USE_DEBUG_TLB 376 377config ARCH_MPC8536 378 bool 379 select FSL_LAW 380 select SYS_FSL_HAS_DDR2 381 select SYS_FSL_HAS_DDR3 382 select SYS_FSL_HAS_SEC 383 select SYS_FSL_SEC_BE 384 select SYS_FSL_SEC_COMPAT_2 385 select SYS_PPC_E500_USE_DEBUG_TLB 386 387config ARCH_MPC8540 388 bool 389 select FSL_LAW 390 select SYS_FSL_HAS_DDR1 391 392config ARCH_MPC8541 393 bool 394 select FSL_LAW 395 select SYS_FSL_HAS_DDR1 396 select SYS_FSL_HAS_SEC 397 select SYS_FSL_SEC_BE 398 select SYS_FSL_SEC_COMPAT_2 399 400config ARCH_MPC8544 401 bool 402 select FSL_LAW 403 select SYS_FSL_HAS_DDR2 404 select SYS_FSL_HAS_SEC 405 select SYS_FSL_SEC_BE 406 select SYS_FSL_SEC_COMPAT_2 407 select SYS_PPC_E500_USE_DEBUG_TLB 408 409config ARCH_MPC8548 410 bool 411 select FSL_LAW 412 select SYS_FSL_HAS_DDR2 413 select SYS_FSL_HAS_DDR1 414 select SYS_FSL_HAS_SEC 415 select SYS_FSL_SEC_BE 416 select SYS_FSL_SEC_COMPAT_2 417 select SYS_PPC_E500_USE_DEBUG_TLB 418 419config ARCH_MPC8555 420 bool 421 select FSL_LAW 422 select SYS_FSL_HAS_DDR1 423 select SYS_FSL_HAS_SEC 424 select SYS_FSL_SEC_BE 425 select SYS_FSL_SEC_COMPAT_2 426 427config ARCH_MPC8560 428 bool 429 select FSL_LAW 430 select SYS_FSL_HAS_DDR1 431 432config ARCH_MPC8568 433 bool 434 select FSL_LAW 435 select SYS_FSL_HAS_DDR2 436 select SYS_FSL_HAS_SEC 437 select SYS_FSL_SEC_BE 438 select SYS_FSL_SEC_COMPAT_2 439 440config ARCH_MPC8569 441 bool 442 select FSL_LAW 443 select SYS_FSL_HAS_DDR3 444 select SYS_FSL_HAS_SEC 445 select SYS_FSL_SEC_BE 446 select SYS_FSL_SEC_COMPAT_2 447 448config ARCH_MPC8572 449 bool 450 select FSL_LAW 451 select SYS_FSL_HAS_DDR2 452 select SYS_FSL_HAS_DDR3 453 select SYS_FSL_HAS_SEC 454 select SYS_FSL_SEC_BE 455 select SYS_FSL_SEC_COMPAT_2 456 select SYS_PPC_E500_USE_DEBUG_TLB 457 458config ARCH_P1010 459 bool 460 select FSL_LAW 461 select SYS_FSL_ERRATUM_ESDHC111 462 select SYS_FSL_HAS_DDR3 463 select SYS_FSL_HAS_SEC 464 select SYS_FSL_SEC_BE 465 select SYS_FSL_SEC_COMPAT_4 466 select SYS_PPC_E500_USE_DEBUG_TLB 467 468config ARCH_P1011 469 bool 470 select FSL_LAW 471 select SYS_FSL_ERRATUM_ESDHC111 472 select SYS_FSL_HAS_DDR3 473 select SYS_FSL_HAS_SEC 474 select SYS_FSL_SEC_BE 475 select SYS_FSL_SEC_COMPAT_2 476 select SYS_PPC_E500_USE_DEBUG_TLB 477 478config ARCH_P1020 479 bool 480 select FSL_LAW 481 select SYS_FSL_ERRATUM_ESDHC111 482 select SYS_FSL_HAS_DDR3 483 select SYS_FSL_HAS_SEC 484 select SYS_FSL_SEC_BE 485 select SYS_FSL_SEC_COMPAT_2 486 select SYS_PPC_E500_USE_DEBUG_TLB 487 488config ARCH_P1021 489 bool 490 select FSL_LAW 491 select SYS_FSL_ERRATUM_ESDHC111 492 select SYS_FSL_HAS_DDR3 493 select SYS_FSL_HAS_SEC 494 select SYS_FSL_SEC_BE 495 select SYS_FSL_SEC_COMPAT_2 496 select SYS_PPC_E500_USE_DEBUG_TLB 497 498config ARCH_P1022 499 bool 500 select FSL_LAW 501 select SYS_FSL_ERRATUM_ESDHC111 502 select SYS_FSL_HAS_DDR3 503 select SYS_FSL_HAS_SEC 504 select SYS_FSL_SEC_BE 505 select SYS_FSL_SEC_COMPAT_2 506 select SYS_PPC_E500_USE_DEBUG_TLB 507 508config ARCH_P1023 509 bool 510 select FSL_LAW 511 select SYS_FSL_HAS_DDR3 512 select SYS_FSL_HAS_SEC 513 select SYS_FSL_SEC_BE 514 select SYS_FSL_SEC_COMPAT_4 515 516config ARCH_P1024 517 bool 518 select FSL_LAW 519 select SYS_FSL_ERRATUM_ESDHC111 520 select SYS_FSL_HAS_DDR3 521 select SYS_FSL_HAS_SEC 522 select SYS_FSL_SEC_BE 523 select SYS_FSL_SEC_COMPAT_2 524 select SYS_PPC_E500_USE_DEBUG_TLB 525 526config ARCH_P1025 527 bool 528 select FSL_LAW 529 select SYS_FSL_ERRATUM_ESDHC111 530 select SYS_FSL_HAS_DDR3 531 select SYS_FSL_HAS_SEC 532 select SYS_FSL_SEC_BE 533 select SYS_FSL_SEC_COMPAT_2 534 select SYS_PPC_E500_USE_DEBUG_TLB 535 536config ARCH_P2020 537 bool 538 select FSL_LAW 539 select SYS_FSL_ERRATUM_ESDHC111 540 select SYS_FSL_ERRATUM_ESDHC_A001 541 select SYS_FSL_HAS_DDR3 542 select SYS_FSL_HAS_SEC 543 select SYS_FSL_SEC_BE 544 select SYS_FSL_SEC_COMPAT_2 545 select SYS_PPC_E500_USE_DEBUG_TLB 546 547config ARCH_P2041 548 bool 549 select E500MC 550 select FSL_LAW 551 select SYS_FSL_ERRATUM_ESDHC111 552 select SYS_FSL_HAS_DDR3 553 select SYS_FSL_HAS_SEC 554 select SYS_FSL_SEC_BE 555 select SYS_FSL_SEC_COMPAT_4 556 557config ARCH_P3041 558 bool 559 select E500MC 560 select FSL_LAW 561 select SYS_FSL_ERRATUM_ESDHC111 562 select SYS_FSL_HAS_DDR3 563 select SYS_FSL_HAS_SEC 564 select SYS_FSL_SEC_BE 565 select SYS_FSL_SEC_COMPAT_4 566 567config ARCH_P4080 568 bool 569 select E500MC 570 select FSL_LAW 571 select SYS_FSL_ERRATUM_ESDHC111 572 select SYS_FSL_ERRATUM_ESDHC13 573 select SYS_FSL_ERRATUM_ESDHC135 574 select SYS_FSL_HAS_DDR3 575 select SYS_FSL_HAS_SEC 576 select SYS_FSL_SEC_BE 577 select SYS_FSL_SEC_COMPAT_4 578 579config ARCH_P5020 580 bool 581 select E500MC 582 select FSL_LAW 583 select SYS_FSL_ERRATUM_ESDHC111 584 select SYS_FSL_HAS_DDR3 585 select SYS_FSL_HAS_SEC 586 select SYS_FSL_SEC_BE 587 select SYS_FSL_SEC_COMPAT_4 588 589config ARCH_P5040 590 bool 591 select E500MC 592 select FSL_LAW 593 select SYS_FSL_ERRATUM_ESDHC111 594 select SYS_FSL_HAS_DDR3 595 select SYS_FSL_HAS_SEC 596 select SYS_FSL_SEC_BE 597 select SYS_FSL_SEC_COMPAT_4 598 599config ARCH_QEMU_E500 600 bool 601 602config ARCH_T1023 603 bool 604 select E500MC 605 select FSL_LAW 606 select SYS_FSL_ERRATUM_ESDHC111 607 select SYS_FSL_HAS_DDR3 608 select SYS_FSL_HAS_DDR4 609 select SYS_FSL_HAS_SEC 610 select SYS_FSL_SEC_BE 611 select SYS_FSL_SEC_COMPAT_5 612 613config ARCH_T1024 614 bool 615 select E500MC 616 select FSL_LAW 617 select SYS_FSL_ERRATUM_ESDHC111 618 select SYS_FSL_HAS_DDR3 619 select SYS_FSL_HAS_DDR4 620 select SYS_FSL_HAS_SEC 621 select SYS_FSL_SEC_BE 622 select SYS_FSL_SEC_COMPAT_5 623 624config ARCH_T1040 625 bool 626 select E500MC 627 select FSL_LAW 628 select SYS_FSL_ERRATUM_ESDHC111 629 select SYS_FSL_HAS_DDR3 630 select SYS_FSL_HAS_DDR4 631 select SYS_FSL_HAS_SEC 632 select SYS_FSL_SEC_BE 633 select SYS_FSL_SEC_COMPAT_5 634 635config ARCH_T1042 636 bool 637 select E500MC 638 select FSL_LAW 639 select SYS_FSL_ERRATUM_ESDHC111 640 select SYS_FSL_HAS_DDR3 641 select SYS_FSL_HAS_DDR4 642 select SYS_FSL_HAS_SEC 643 select SYS_FSL_SEC_BE 644 select SYS_FSL_SEC_COMPAT_5 645 646config ARCH_T2080 647 bool 648 select E500MC 649 select FSL_LAW 650 select SYS_FSL_ERRATUM_ESDHC111 651 select SYS_FSL_HAS_DDR3 652 select SYS_FSL_HAS_SEC 653 select SYS_FSL_SEC_BE 654 select SYS_FSL_SEC_COMPAT_4 655 656config ARCH_T2081 657 bool 658 select E500MC 659 select FSL_LAW 660 select SYS_FSL_ERRATUM_ESDHC111 661 select SYS_FSL_HAS_DDR3 662 select SYS_FSL_HAS_SEC 663 select SYS_FSL_SEC_BE 664 select SYS_FSL_SEC_COMPAT_4 665 666config ARCH_T4160 667 bool 668 select E500MC 669 select FSL_LAW 670 select SYS_FSL_HAS_DDR3 671 select SYS_FSL_HAS_SEC 672 select SYS_FSL_SEC_BE 673 select SYS_FSL_SEC_COMPAT_4 674 675config ARCH_T4240 676 bool 677 select E500MC 678 select FSL_LAW 679 select SYS_FSL_HAS_DDR3 680 select SYS_FSL_HAS_SEC 681 select SYS_FSL_SEC_BE 682 select SYS_FSL_SEC_COMPAT_4 683 684config BOOKE 685 bool 686 default y 687 688config E500 689 bool 690 default y 691 help 692 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 693 694config E500MC 695 bool 696 help 697 Enble PowerPC E500MC core 698 699config FSL_LAW 700 bool 701 help 702 Use Freescale common code for Local Access Window 703 704config SECURE_BOOT 705 bool "Secure Boot" 706 help 707 Enable Freescale Secure Boot feature. Normally selected 708 by defconfig. If unsure, do not change. 709 710config MAX_CPUS 711 int "Maximum number of CPUs permitted for MPC85xx" 712 default 12 if ARCH_T4240 713 default 8 if ARCH_P4080 || \ 714 ARCH_T4160 715 default 4 if ARCH_B4860 || \ 716 ARCH_P2041 || \ 717 ARCH_P3041 || \ 718 ARCH_P5040 || \ 719 ARCH_T1040 || \ 720 ARCH_T1042 || \ 721 ARCH_T2080 || \ 722 ARCH_T2081 723 default 2 if ARCH_B4420 || \ 724 ARCH_BSC9132 || \ 725 ARCH_MPC8572 || \ 726 ARCH_P1020 || \ 727 ARCH_P1021 || \ 728 ARCH_P1022 || \ 729 ARCH_P1023 || \ 730 ARCH_P1024 || \ 731 ARCH_P1025 || \ 732 ARCH_P2020 || \ 733 ARCH_P5020 || \ 734 ARCH_T1023 || \ 735 ARCH_T1024 736 default 1 737 help 738 Set this number to the maximum number of possible CPUs in the SoC. 739 SoCs may have multiple clusters with each cluster may have multiple 740 ports. If some ports are reserved but higher ports are used for 741 cores, count the reserved ports. This will allocate enough memory 742 in spin table to properly handle all cores. 743 744config SYS_CCSRBAR_DEFAULT 745 hex "Default CCSRBAR address" 746 default 0xff700000 if ARCH_BSC9131 || \ 747 ARCH_BSC9132 || \ 748 ARCH_C29X || \ 749 ARCH_MPC8536 || \ 750 ARCH_MPC8540 || \ 751 ARCH_MPC8541 || \ 752 ARCH_MPC8544 || \ 753 ARCH_MPC8548 || \ 754 ARCH_MPC8555 || \ 755 ARCH_MPC8560 || \ 756 ARCH_MPC8568 || \ 757 ARCH_MPC8569 || \ 758 ARCH_MPC8572 || \ 759 ARCH_P1010 || \ 760 ARCH_P1011 || \ 761 ARCH_P1020 || \ 762 ARCH_P1021 || \ 763 ARCH_P1022 || \ 764 ARCH_P1024 || \ 765 ARCH_P1025 || \ 766 ARCH_P2020 767 default 0xff600000 if ARCH_P1023 768 default 0xfe000000 if ARCH_B4420 || \ 769 ARCH_B4860 || \ 770 ARCH_P2041 || \ 771 ARCH_P3041 || \ 772 ARCH_P4080 || \ 773 ARCH_P5020 || \ 774 ARCH_P5040 || \ 775 ARCH_T1023 || \ 776 ARCH_T1024 || \ 777 ARCH_T1040 || \ 778 ARCH_T1042 || \ 779 ARCH_T2080 || \ 780 ARCH_T2081 || \ 781 ARCH_T4160 || \ 782 ARCH_T4240 783 default 0xe0000000 if ARCH_QEMU_E500 784 help 785 Default value of CCSRBAR comes from power-on-reset. It 786 is fixed on each SoC. Some SoCs can have different value 787 if changed by pre-boot regime. The value here must match 788 the current value in SoC. If not sure, do not change. 789 790config SYS_FSL_NUM_LAWS 791 int "Number of local access windows" 792 depends on FSL_LAW 793 default 32 if ARCH_B4420 || \ 794 ARCH_B4860 || \ 795 ARCH_P2041 || \ 796 ARCH_P3041 || \ 797 ARCH_P4080 || \ 798 ARCH_P5020 || \ 799 ARCH_P5040 || \ 800 ARCH_T2080 || \ 801 ARCH_T2081 || \ 802 ARCH_T4160 || \ 803 ARCH_T4240 804 default 16 if ARCH_T1023 || \ 805 ARCH_T1024 || \ 806 ARCH_T1040 || \ 807 ARCH_T1042 808 default 12 if ARCH_BSC9131 || \ 809 ARCH_BSC9132 || \ 810 ARCH_C29X || \ 811 ARCH_MPC8536 || \ 812 ARCH_MPC8572 || \ 813 ARCH_P1010 || \ 814 ARCH_P1011 || \ 815 ARCH_P1020 || \ 816 ARCH_P1021 || \ 817 ARCH_P1022 || \ 818 ARCH_P1023 || \ 819 ARCH_P1024 || \ 820 ARCH_P1025 || \ 821 ARCH_P2020 822 default 10 if ARCH_MPC8544 || \ 823 ARCH_MPC8548 || \ 824 ARCH_MPC8568 || \ 825 ARCH_MPC8569 826 default 8 if ARCH_MPC8540 || \ 827 ARCH_MPC8541 || \ 828 ARCH_MPC8555 || \ 829 ARCH_MPC8560 830 help 831 Number of local access windows. This is fixed per SoC. 832 If not sure, do not change. 833 834config SYS_NUM_TLBCAMS 835 int "Number of TLB CAM entries" 836 default 64 if E500MC 837 default 16 838 help 839 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 840 16 for other E500 SoCs. 841 842config SYS_PPC_E500_USE_DEBUG_TLB 843 bool 844 845config SYS_PPC_E500_DEBUG_TLB 846 int "Temporary TLB entry for external debugger" 847 depends on SYS_PPC_E500_USE_DEBUG_TLB 848 default 0 if ARCH_MPC8544 || ARCH_MPC8548 849 default 1 if ARCH_MPC8536 850 default 2 if ARCH_MPC8572 || \ 851 ARCH_P1011 || \ 852 ARCH_P1020 || \ 853 ARCH_P1021 || \ 854 ARCH_P1022 || \ 855 ARCH_P1024 || \ 856 ARCH_P1025 || \ 857 ARCH_P2020 858 default 3 if ARCH_P1010 || \ 859 ARCH_BSC9132 || \ 860 ARCH_C29X 861 help 862 Select a temporary TLB entry to be used during boot to work 863 around limitations in e500v1 and e500v2 external debugger 864 support. This reduces the portions of the boot code where 865 breakpoints and single stepping do not work. The value of this 866 symbol should be set to the TLB1 entry to be used for this 867 purpose. If unsure, do not change. 868 869source "board/freescale/b4860qds/Kconfig" 870source "board/freescale/bsc9131rdb/Kconfig" 871source "board/freescale/bsc9132qds/Kconfig" 872source "board/freescale/c29xpcie/Kconfig" 873source "board/freescale/corenet_ds/Kconfig" 874source "board/freescale/mpc8536ds/Kconfig" 875source "board/freescale/mpc8540ads/Kconfig" 876source "board/freescale/mpc8541cds/Kconfig" 877source "board/freescale/mpc8544ds/Kconfig" 878source "board/freescale/mpc8548cds/Kconfig" 879source "board/freescale/mpc8555cds/Kconfig" 880source "board/freescale/mpc8560ads/Kconfig" 881source "board/freescale/mpc8568mds/Kconfig" 882source "board/freescale/mpc8569mds/Kconfig" 883source "board/freescale/mpc8572ds/Kconfig" 884source "board/freescale/p1010rdb/Kconfig" 885source "board/freescale/p1022ds/Kconfig" 886source "board/freescale/p1023rdb/Kconfig" 887source "board/freescale/p1_p2_rdb_pc/Kconfig" 888source "board/freescale/p1_twr/Kconfig" 889source "board/freescale/p2041rdb/Kconfig" 890source "board/freescale/qemu-ppce500/Kconfig" 891source "board/freescale/t102xqds/Kconfig" 892source "board/freescale/t102xrdb/Kconfig" 893source "board/freescale/t1040qds/Kconfig" 894source "board/freescale/t104xrdb/Kconfig" 895source "board/freescale/t208xqds/Kconfig" 896source "board/freescale/t208xrdb/Kconfig" 897source "board/freescale/t4qds/Kconfig" 898source "board/freescale/t4rdb/Kconfig" 899source "board/gdsys/p1022/Kconfig" 900source "board/keymile/kmp204x/Kconfig" 901source "board/sbc8548/Kconfig" 902source "board/socrates/Kconfig" 903source "board/varisys/cyrus/Kconfig" 904source "board/xes/xpedite520x/Kconfig" 905source "board/xes/xpedite537x/Kconfig" 906source "board/xes/xpedite550x/Kconfig" 907source "board/Arcturus/ucp1020/Kconfig" 908 909endmenu 910