1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 23config TARGET_SOCRATES 24 bool "Support socrates" 25 select ARCH_MPC8544 26 27config TARGET_B4420QDS 28 bool "Support B4420QDS" 29 select ARCH_B4420 30 select SUPPORT_SPL 31 select PHYS_64BIT 32 33config TARGET_B4860QDS 34 bool "Support B4860QDS" 35 select ARCH_B4860 36 select BOARD_LATE_INIT if CHAIN_OF_TRUST 37 select SUPPORT_SPL 38 select PHYS_64BIT 39 40config TARGET_BSC9131RDB 41 bool "Support BSC9131RDB" 42 select ARCH_BSC9131 43 select SUPPORT_SPL 44 select BOARD_EARLY_INIT_F 45 46config TARGET_BSC9132QDS 47 bool "Support BSC9132QDS" 48 select ARCH_BSC9132 49 select BOARD_LATE_INIT if CHAIN_OF_TRUST 50 select SUPPORT_SPL 51 select BOARD_EARLY_INIT_F 52 53config TARGET_C29XPCIE 54 bool "Support C29XPCIE" 55 select ARCH_C29X 56 select BOARD_LATE_INIT if CHAIN_OF_TRUST 57 select SUPPORT_SPL 58 select SUPPORT_TPL 59 select PHYS_64BIT 60 61config TARGET_P3041DS 62 bool "Support P3041DS" 63 select PHYS_64BIT 64 select ARCH_P3041 65 select BOARD_LATE_INIT if CHAIN_OF_TRUST 66 imply CMD_SATA 67 68config TARGET_P4080DS 69 bool "Support P4080DS" 70 select PHYS_64BIT 71 select ARCH_P4080 72 select BOARD_LATE_INIT if CHAIN_OF_TRUST 73 imply CMD_SATA 74 75config TARGET_P5020DS 76 bool "Support P5020DS" 77 select PHYS_64BIT 78 select ARCH_P5020 79 select BOARD_LATE_INIT if CHAIN_OF_TRUST 80 imply CMD_SATA 81 82config TARGET_P5040DS 83 bool "Support P5040DS" 84 select PHYS_64BIT 85 select ARCH_P5040 86 select BOARD_LATE_INIT if CHAIN_OF_TRUST 87 imply CMD_SATA 88 89config TARGET_MPC8536DS 90 bool "Support MPC8536DS" 91 select ARCH_MPC8536 92# Use DDR3 controller with DDR2 DIMMs on this board 93 select SYS_FSL_DDRC_GEN3 94 imply CMD_SATA 95 imply FSL_SATA 96 97config TARGET_MPC8541CDS 98 bool "Support MPC8541CDS" 99 select ARCH_MPC8541 100 101config TARGET_MPC8544DS 102 bool "Support MPC8544DS" 103 select ARCH_MPC8544 104 105config TARGET_MPC8548CDS 106 bool "Support MPC8548CDS" 107 select ARCH_MPC8548 108 109config TARGET_MPC8555CDS 110 bool "Support MPC8555CDS" 111 select ARCH_MPC8555 112 113config TARGET_MPC8568MDS 114 bool "Support MPC8568MDS" 115 select ARCH_MPC8568 116 117config TARGET_MPC8569MDS 118 bool "Support MPC8569MDS" 119 select ARCH_MPC8569 120 121config TARGET_MPC8572DS 122 bool "Support MPC8572DS" 123 select ARCH_MPC8572 124# Use DDR3 controller with DDR2 DIMMs on this board 125 select SYS_FSL_DDRC_GEN3 126 imply SCSI 127 128config TARGET_P1010RDB_PA 129 bool "Support P1010RDB_PA" 130 select ARCH_P1010 131 select BOARD_LATE_INIT if CHAIN_OF_TRUST 132 select SUPPORT_SPL 133 select SUPPORT_TPL 134 imply CMD_EEPROM 135 imply CMD_SATA 136 137config TARGET_P1010RDB_PB 138 bool "Support P1010RDB_PB" 139 select ARCH_P1010 140 select BOARD_LATE_INIT if CHAIN_OF_TRUST 141 select SUPPORT_SPL 142 select SUPPORT_TPL 143 imply CMD_EEPROM 144 imply CMD_SATA 145 146config TARGET_P1022DS 147 bool "Support P1022DS" 148 select ARCH_P1022 149 select SUPPORT_SPL 150 select SUPPORT_TPL 151 imply CMD_SATA 152 imply FSL_SATA 153 154config TARGET_P1023RDB 155 bool "Support P1023RDB" 156 select ARCH_P1023 157 imply CMD_EEPROM 158 159config TARGET_P1020MBG 160 bool "Support P1020MBG-PC" 161 select SUPPORT_SPL 162 select SUPPORT_TPL 163 select ARCH_P1020 164 imply CMD_EEPROM 165 imply CMD_SATA 166 167config TARGET_P1020RDB_PC 168 bool "Support P1020RDB-PC" 169 select SUPPORT_SPL 170 select SUPPORT_TPL 171 select ARCH_P1020 172 imply CMD_EEPROM 173 imply CMD_SATA 174 175config TARGET_P1020RDB_PD 176 bool "Support P1020RDB-PD" 177 select SUPPORT_SPL 178 select SUPPORT_TPL 179 select ARCH_P1020 180 imply CMD_EEPROM 181 imply CMD_SATA 182 183config TARGET_P1020UTM 184 bool "Support P1020UTM" 185 select SUPPORT_SPL 186 select SUPPORT_TPL 187 select ARCH_P1020 188 imply CMD_EEPROM 189 imply CMD_SATA 190 191config TARGET_P1021RDB 192 bool "Support P1021RDB" 193 select SUPPORT_SPL 194 select SUPPORT_TPL 195 select ARCH_P1021 196 imply CMD_EEPROM 197 imply CMD_SATA 198 199config TARGET_P1024RDB 200 bool "Support P1024RDB" 201 select SUPPORT_SPL 202 select SUPPORT_TPL 203 select ARCH_P1024 204 imply CMD_EEPROM 205 imply CMD_SATA 206 207config TARGET_P1025RDB 208 bool "Support P1025RDB" 209 select SUPPORT_SPL 210 select SUPPORT_TPL 211 select ARCH_P1025 212 imply CMD_EEPROM 213 imply CMD_SATA 214 imply SATA_SIL 215 216config TARGET_P2020RDB 217 bool "Support P2020RDB-PC" 218 select SUPPORT_SPL 219 select SUPPORT_TPL 220 select ARCH_P2020 221 imply CMD_EEPROM 222 imply CMD_SATA 223 imply SATA_SIL 224 225config TARGET_P1_TWR 226 bool "Support p1_twr" 227 select ARCH_P1025 228 229config TARGET_P2041RDB 230 bool "Support P2041RDB" 231 select ARCH_P2041 232 select BOARD_LATE_INIT if CHAIN_OF_TRUST 233 select PHYS_64BIT 234 imply CMD_SATA 235 imply FSL_SATA 236 237config TARGET_QEMU_PPCE500 238 bool "Support qemu-ppce500" 239 select ARCH_QEMU_E500 240 select PHYS_64BIT 241 242config TARGET_T1024QDS 243 bool "Support T1024QDS" 244 select ARCH_T1024 245 select BOARD_LATE_INIT if CHAIN_OF_TRUST 246 select SUPPORT_SPL 247 select PHYS_64BIT 248 imply CMD_EEPROM 249 imply CMD_SATA 250 imply FSL_SATA 251 252config TARGET_T1023RDB 253 bool "Support T1023RDB" 254 select ARCH_T1023 255 select BOARD_LATE_INIT if CHAIN_OF_TRUST 256 select SUPPORT_SPL 257 select PHYS_64BIT 258 imply CMD_EEPROM 259 260config TARGET_T1024RDB 261 bool "Support T1024RDB" 262 select ARCH_T1024 263 select BOARD_LATE_INIT if CHAIN_OF_TRUST 264 select SUPPORT_SPL 265 select PHYS_64BIT 266 imply CMD_EEPROM 267 268config TARGET_T1040QDS 269 bool "Support T1040QDS" 270 select ARCH_T1040 271 select BOARD_LATE_INIT if CHAIN_OF_TRUST 272 select PHYS_64BIT 273 imply CMD_EEPROM 274 imply CMD_SATA 275 276config TARGET_T1040RDB 277 bool "Support T1040RDB" 278 select ARCH_T1040 279 select BOARD_LATE_INIT if CHAIN_OF_TRUST 280 select SUPPORT_SPL 281 select PHYS_64BIT 282 imply CMD_SATA 283 284config TARGET_T1040D4RDB 285 bool "Support T1040D4RDB" 286 select ARCH_T1040 287 select BOARD_LATE_INIT if CHAIN_OF_TRUST 288 select SUPPORT_SPL 289 select PHYS_64BIT 290 imply CMD_SATA 291 292config TARGET_T1042RDB 293 bool "Support T1042RDB" 294 select ARCH_T1042 295 select BOARD_LATE_INIT if CHAIN_OF_TRUST 296 select SUPPORT_SPL 297 select PHYS_64BIT 298 imply CMD_SATA 299 300config TARGET_T1042D4RDB 301 bool "Support T1042D4RDB" 302 select ARCH_T1042 303 select BOARD_LATE_INIT if CHAIN_OF_TRUST 304 select SUPPORT_SPL 305 select PHYS_64BIT 306 imply CMD_SATA 307 308config TARGET_T1042RDB_PI 309 bool "Support T1042RDB_PI" 310 select ARCH_T1042 311 select BOARD_LATE_INIT if CHAIN_OF_TRUST 312 select SUPPORT_SPL 313 select PHYS_64BIT 314 imply CMD_SATA 315 316config TARGET_T2080QDS 317 bool "Support T2080QDS" 318 select ARCH_T2080 319 select BOARD_LATE_INIT if CHAIN_OF_TRUST 320 select SUPPORT_SPL 321 select PHYS_64BIT 322 imply CMD_SATA 323 324config TARGET_T2080RDB 325 bool "Support T2080RDB" 326 select ARCH_T2080 327 select BOARD_LATE_INIT if CHAIN_OF_TRUST 328 select SUPPORT_SPL 329 select PHYS_64BIT 330 imply CMD_SATA 331 332config TARGET_T2081QDS 333 bool "Support T2081QDS" 334 select ARCH_T2081 335 select SUPPORT_SPL 336 select PHYS_64BIT 337 338config TARGET_T4160QDS 339 bool "Support T4160QDS" 340 select ARCH_T4160 341 select BOARD_LATE_INIT if CHAIN_OF_TRUST 342 select SUPPORT_SPL 343 select PHYS_64BIT 344 imply CMD_SATA 345 346config TARGET_T4160RDB 347 bool "Support T4160RDB" 348 select ARCH_T4160 349 select SUPPORT_SPL 350 select PHYS_64BIT 351 352config TARGET_T4240QDS 353 bool "Support T4240QDS" 354 select ARCH_T4240 355 select BOARD_LATE_INIT if CHAIN_OF_TRUST 356 select SUPPORT_SPL 357 select PHYS_64BIT 358 imply CMD_SATA 359 360config TARGET_T4240RDB 361 bool "Support T4240RDB" 362 select ARCH_T4240 363 select SUPPORT_SPL 364 select PHYS_64BIT 365 imply CMD_SATA 366 367config TARGET_CONTROLCENTERD 368 bool "Support controlcenterd" 369 select ARCH_P1022 370 371config TARGET_KMP204X 372 bool "Support kmp204x" 373 select ARCH_P2041 374 select PHYS_64BIT 375 imply CMD_CRAMFS 376 imply FS_CRAMFS 377 378config TARGET_XPEDITE520X 379 bool "Support xpedite520x" 380 select ARCH_MPC8548 381 382config TARGET_XPEDITE537X 383 bool "Support xpedite537x" 384 select ARCH_MPC8572 385# Use DDR3 controller with DDR2 DIMMs on this board 386 select SYS_FSL_DDRC_GEN3 387 388config TARGET_XPEDITE550X 389 bool "Support xpedite550x" 390 select ARCH_P2020 391 392config TARGET_UCP1020 393 bool "Support uCP1020" 394 select ARCH_P1020 395 imply CMD_SATA 396 397config TARGET_CYRUS_P5020 398 bool "Support Varisys Cyrus P5020" 399 select ARCH_P5020 400 select PHYS_64BIT 401 402config TARGET_CYRUS_P5040 403 bool "Support Varisys Cyrus P5040" 404 select ARCH_P5040 405 select PHYS_64BIT 406 407endchoice 408 409config ARCH_B4420 410 bool 411 select E500MC 412 select E6500 413 select FSL_LAW 414 select SYS_FSL_DDR_VER_47 415 select SYS_FSL_ERRATUM_A004477 416 select SYS_FSL_ERRATUM_A005871 417 select SYS_FSL_ERRATUM_A006379 418 select SYS_FSL_ERRATUM_A006384 419 select SYS_FSL_ERRATUM_A006475 420 select SYS_FSL_ERRATUM_A006593 421 select SYS_FSL_ERRATUM_A007075 422 select SYS_FSL_ERRATUM_A007186 423 select SYS_FSL_ERRATUM_A007212 424 select SYS_FSL_ERRATUM_A009942 425 select SYS_FSL_HAS_DDR3 426 select SYS_FSL_HAS_SEC 427 select SYS_FSL_QORIQ_CHASSIS2 428 select SYS_FSL_SEC_BE 429 select SYS_FSL_SEC_COMPAT_4 430 select SYS_PPC64 431 select FSL_IFC 432 imply CMD_EEPROM 433 imply CMD_NAND 434 imply CMD_REGINFO 435 436config ARCH_B4860 437 bool 438 select E500MC 439 select E6500 440 select FSL_LAW 441 select SYS_FSL_DDR_VER_47 442 select SYS_FSL_ERRATUM_A004477 443 select SYS_FSL_ERRATUM_A005871 444 select SYS_FSL_ERRATUM_A006379 445 select SYS_FSL_ERRATUM_A006384 446 select SYS_FSL_ERRATUM_A006475 447 select SYS_FSL_ERRATUM_A006593 448 select SYS_FSL_ERRATUM_A007075 449 select SYS_FSL_ERRATUM_A007186 450 select SYS_FSL_ERRATUM_A007212 451 select SYS_FSL_ERRATUM_A007907 452 select SYS_FSL_ERRATUM_A009942 453 select SYS_FSL_HAS_DDR3 454 select SYS_FSL_HAS_SEC 455 select SYS_FSL_QORIQ_CHASSIS2 456 select SYS_FSL_SEC_BE 457 select SYS_FSL_SEC_COMPAT_4 458 select SYS_PPC64 459 select FSL_IFC 460 imply CMD_EEPROM 461 imply CMD_NAND 462 imply CMD_REGINFO 463 464config ARCH_BSC9131 465 bool 466 select FSL_LAW 467 select SYS_FSL_DDR_VER_44 468 select SYS_FSL_ERRATUM_A004477 469 select SYS_FSL_ERRATUM_A005125 470 select SYS_FSL_ERRATUM_ESDHC111 471 select SYS_FSL_HAS_DDR3 472 select SYS_FSL_HAS_SEC 473 select SYS_FSL_SEC_BE 474 select SYS_FSL_SEC_COMPAT_4 475 select FSL_IFC 476 imply CMD_EEPROM 477 imply CMD_NAND 478 imply CMD_REGINFO 479 480config ARCH_BSC9132 481 bool 482 select FSL_LAW 483 select SYS_FSL_DDR_VER_46 484 select SYS_FSL_ERRATUM_A004477 485 select SYS_FSL_ERRATUM_A005125 486 select SYS_FSL_ERRATUM_A005434 487 select SYS_FSL_ERRATUM_ESDHC111 488 select SYS_FSL_ERRATUM_I2C_A004447 489 select SYS_FSL_ERRATUM_IFC_A002769 490 select SYS_FSL_HAS_DDR3 491 select SYS_FSL_HAS_SEC 492 select SYS_FSL_SEC_BE 493 select SYS_FSL_SEC_COMPAT_4 494 select SYS_PPC_E500_USE_DEBUG_TLB 495 select FSL_IFC 496 imply CMD_EEPROM 497 imply CMD_MTDPARTS 498 imply CMD_NAND 499 imply CMD_PCI 500 imply CMD_REGINFO 501 502config ARCH_C29X 503 bool 504 select FSL_LAW 505 select SYS_FSL_DDR_VER_46 506 select SYS_FSL_ERRATUM_A005125 507 select SYS_FSL_ERRATUM_ESDHC111 508 select SYS_FSL_HAS_DDR3 509 select SYS_FSL_HAS_SEC 510 select SYS_FSL_SEC_BE 511 select SYS_FSL_SEC_COMPAT_6 512 select SYS_PPC_E500_USE_DEBUG_TLB 513 select FSL_IFC 514 imply CMD_NAND 515 imply CMD_PCI 516 imply CMD_REGINFO 517 518config ARCH_MPC8536 519 bool 520 select FSL_LAW 521 select SYS_FSL_ERRATUM_A004508 522 select SYS_FSL_ERRATUM_A005125 523 select SYS_FSL_HAS_DDR2 524 select SYS_FSL_HAS_DDR3 525 select SYS_FSL_HAS_SEC 526 select SYS_FSL_SEC_BE 527 select SYS_FSL_SEC_COMPAT_2 528 select SYS_PPC_E500_USE_DEBUG_TLB 529 select FSL_ELBC 530 imply CMD_NAND 531 imply CMD_SATA 532 imply CMD_REGINFO 533 534config ARCH_MPC8540 535 bool 536 select FSL_LAW 537 select SYS_FSL_HAS_DDR1 538 539config ARCH_MPC8541 540 bool 541 select FSL_LAW 542 select SYS_FSL_HAS_DDR1 543 select SYS_FSL_HAS_SEC 544 select SYS_FSL_SEC_BE 545 select SYS_FSL_SEC_COMPAT_2 546 547config ARCH_MPC8544 548 bool 549 select FSL_LAW 550 select SYS_FSL_ERRATUM_A005125 551 select SYS_FSL_HAS_DDR2 552 select SYS_FSL_HAS_SEC 553 select SYS_FSL_SEC_BE 554 select SYS_FSL_SEC_COMPAT_2 555 select SYS_PPC_E500_USE_DEBUG_TLB 556 select FSL_ELBC 557 558config ARCH_MPC8548 559 bool 560 select FSL_LAW 561 select SYS_FSL_ERRATUM_A005125 562 select SYS_FSL_ERRATUM_NMG_DDR120 563 select SYS_FSL_ERRATUM_NMG_LBC103 564 select SYS_FSL_ERRATUM_NMG_ETSEC129 565 select SYS_FSL_ERRATUM_I2C_A004447 566 select SYS_FSL_HAS_DDR2 567 select SYS_FSL_HAS_DDR1 568 select SYS_FSL_HAS_SEC 569 select SYS_FSL_SEC_BE 570 select SYS_FSL_SEC_COMPAT_2 571 select SYS_PPC_E500_USE_DEBUG_TLB 572 imply CMD_REGINFO 573 574config ARCH_MPC8555 575 bool 576 select FSL_LAW 577 select SYS_FSL_HAS_DDR1 578 select SYS_FSL_HAS_SEC 579 select SYS_FSL_SEC_BE 580 select SYS_FSL_SEC_COMPAT_2 581 582config ARCH_MPC8560 583 bool 584 select FSL_LAW 585 select SYS_FSL_HAS_DDR1 586 587config ARCH_MPC8568 588 bool 589 select FSL_LAW 590 select SYS_FSL_HAS_DDR2 591 select SYS_FSL_HAS_SEC 592 select SYS_FSL_SEC_BE 593 select SYS_FSL_SEC_COMPAT_2 594 595config ARCH_MPC8569 596 bool 597 select FSL_LAW 598 select SYS_FSL_ERRATUM_A004508 599 select SYS_FSL_ERRATUM_A005125 600 select SYS_FSL_HAS_DDR3 601 select SYS_FSL_HAS_SEC 602 select SYS_FSL_SEC_BE 603 select SYS_FSL_SEC_COMPAT_2 604 select FSL_ELBC 605 imply CMD_NAND 606 607config ARCH_MPC8572 608 bool 609 select FSL_LAW 610 select SYS_FSL_ERRATUM_A004508 611 select SYS_FSL_ERRATUM_A005125 612 select SYS_FSL_ERRATUM_DDR_115 613 select SYS_FSL_ERRATUM_DDR111_DDR134 614 select SYS_FSL_HAS_DDR2 615 select SYS_FSL_HAS_DDR3 616 select SYS_FSL_HAS_SEC 617 select SYS_FSL_SEC_BE 618 select SYS_FSL_SEC_COMPAT_2 619 select SYS_PPC_E500_USE_DEBUG_TLB 620 select FSL_ELBC 621 imply CMD_NAND 622 623config ARCH_P1010 624 bool 625 select FSL_LAW 626 select SYS_FSL_ERRATUM_A004477 627 select SYS_FSL_ERRATUM_A004508 628 select SYS_FSL_ERRATUM_A005125 629 select SYS_FSL_ERRATUM_A006261 630 select SYS_FSL_ERRATUM_A007075 631 select SYS_FSL_ERRATUM_ESDHC111 632 select SYS_FSL_ERRATUM_I2C_A004447 633 select SYS_FSL_ERRATUM_IFC_A002769 634 select SYS_FSL_ERRATUM_P1010_A003549 635 select SYS_FSL_ERRATUM_SEC_A003571 636 select SYS_FSL_ERRATUM_IFC_A003399 637 select SYS_FSL_HAS_DDR3 638 select SYS_FSL_HAS_SEC 639 select SYS_FSL_SEC_BE 640 select SYS_FSL_SEC_COMPAT_4 641 select SYS_PPC_E500_USE_DEBUG_TLB 642 select FSL_IFC 643 imply CMD_EEPROM 644 imply CMD_MTDPARTS 645 imply CMD_NAND 646 imply CMD_SATA 647 imply CMD_PCI 648 imply CMD_REGINFO 649 imply FSL_SATA 650 651config ARCH_P1011 652 bool 653 select FSL_LAW 654 select SYS_FSL_ERRATUM_A004508 655 select SYS_FSL_ERRATUM_A005125 656 select SYS_FSL_ERRATUM_ELBC_A001 657 select SYS_FSL_ERRATUM_ESDHC111 658 select SYS_FSL_HAS_DDR3 659 select SYS_FSL_HAS_SEC 660 select SYS_FSL_SEC_BE 661 select SYS_FSL_SEC_COMPAT_2 662 select SYS_PPC_E500_USE_DEBUG_TLB 663 select FSL_ELBC 664 665config ARCH_P1020 666 bool 667 select FSL_LAW 668 select SYS_FSL_ERRATUM_A004508 669 select SYS_FSL_ERRATUM_A005125 670 select SYS_FSL_ERRATUM_ELBC_A001 671 select SYS_FSL_ERRATUM_ESDHC111 672 select SYS_FSL_HAS_DDR3 673 select SYS_FSL_HAS_SEC 674 select SYS_FSL_SEC_BE 675 select SYS_FSL_SEC_COMPAT_2 676 select SYS_PPC_E500_USE_DEBUG_TLB 677 select FSL_ELBC 678 imply CMD_NAND 679 imply CMD_SATA 680 imply CMD_PCI 681 imply CMD_REGINFO 682 imply SATA_SIL 683 684config ARCH_P1021 685 bool 686 select FSL_LAW 687 select SYS_FSL_ERRATUM_A004508 688 select SYS_FSL_ERRATUM_A005125 689 select SYS_FSL_ERRATUM_ELBC_A001 690 select SYS_FSL_ERRATUM_ESDHC111 691 select SYS_FSL_HAS_DDR3 692 select SYS_FSL_HAS_SEC 693 select SYS_FSL_SEC_BE 694 select SYS_FSL_SEC_COMPAT_2 695 select SYS_PPC_E500_USE_DEBUG_TLB 696 select FSL_ELBC 697 imply CMD_REGINFO 698 imply CMD_NAND 699 imply CMD_SATA 700 imply CMD_REGINFO 701 imply SATA_SIL 702 703config ARCH_P1022 704 bool 705 select FSL_LAW 706 select SYS_FSL_ERRATUM_A004477 707 select SYS_FSL_ERRATUM_A004508 708 select SYS_FSL_ERRATUM_A005125 709 select SYS_FSL_ERRATUM_ELBC_A001 710 select SYS_FSL_ERRATUM_ESDHC111 711 select SYS_FSL_ERRATUM_SATA_A001 712 select SYS_FSL_HAS_DDR3 713 select SYS_FSL_HAS_SEC 714 select SYS_FSL_SEC_BE 715 select SYS_FSL_SEC_COMPAT_2 716 select SYS_PPC_E500_USE_DEBUG_TLB 717 select FSL_ELBC 718 719config ARCH_P1023 720 bool 721 select FSL_LAW 722 select SYS_FSL_ERRATUM_A004508 723 select SYS_FSL_ERRATUM_A005125 724 select SYS_FSL_ERRATUM_I2C_A004447 725 select SYS_FSL_HAS_DDR3 726 select SYS_FSL_HAS_SEC 727 select SYS_FSL_SEC_BE 728 select SYS_FSL_SEC_COMPAT_4 729 select FSL_ELBC 730 731config ARCH_P1024 732 bool 733 select FSL_LAW 734 select SYS_FSL_ERRATUM_A004508 735 select SYS_FSL_ERRATUM_A005125 736 select SYS_FSL_ERRATUM_ELBC_A001 737 select SYS_FSL_ERRATUM_ESDHC111 738 select SYS_FSL_HAS_DDR3 739 select SYS_FSL_HAS_SEC 740 select SYS_FSL_SEC_BE 741 select SYS_FSL_SEC_COMPAT_2 742 select SYS_PPC_E500_USE_DEBUG_TLB 743 select FSL_ELBC 744 imply CMD_EEPROM 745 imply CMD_NAND 746 imply CMD_SATA 747 imply CMD_PCI 748 imply CMD_REGINFO 749 imply SATA_SIL 750 751config ARCH_P1025 752 bool 753 select FSL_LAW 754 select SYS_FSL_ERRATUM_A004508 755 select SYS_FSL_ERRATUM_A005125 756 select SYS_FSL_ERRATUM_ELBC_A001 757 select SYS_FSL_ERRATUM_ESDHC111 758 select SYS_FSL_HAS_DDR3 759 select SYS_FSL_HAS_SEC 760 select SYS_FSL_SEC_BE 761 select SYS_FSL_SEC_COMPAT_2 762 select SYS_PPC_E500_USE_DEBUG_TLB 763 select FSL_ELBC 764 imply CMD_SATA 765 imply CMD_REGINFO 766 767config ARCH_P2020 768 bool 769 select FSL_LAW 770 select SYS_FSL_ERRATUM_A004477 771 select SYS_FSL_ERRATUM_A004508 772 select SYS_FSL_ERRATUM_A005125 773 select SYS_FSL_ERRATUM_ESDHC111 774 select SYS_FSL_ERRATUM_ESDHC_A001 775 select SYS_FSL_HAS_DDR3 776 select SYS_FSL_HAS_SEC 777 select SYS_FSL_SEC_BE 778 select SYS_FSL_SEC_COMPAT_2 779 select SYS_PPC_E500_USE_DEBUG_TLB 780 select FSL_ELBC 781 imply CMD_EEPROM 782 imply CMD_NAND 783 imply CMD_REGINFO 784 785config ARCH_P2041 786 bool 787 select E500MC 788 select FSL_LAW 789 select SYS_FSL_ERRATUM_A004510 790 select SYS_FSL_ERRATUM_A004849 791 select SYS_FSL_ERRATUM_A006261 792 select SYS_FSL_ERRATUM_CPU_A003999 793 select SYS_FSL_ERRATUM_DDR_A003 794 select SYS_FSL_ERRATUM_DDR_A003474 795 select SYS_FSL_ERRATUM_ESDHC111 796 select SYS_FSL_ERRATUM_I2C_A004447 797 select SYS_FSL_ERRATUM_NMG_CPU_A011 798 select SYS_FSL_ERRATUM_SRIO_A004034 799 select SYS_FSL_ERRATUM_USB14 800 select SYS_FSL_HAS_DDR3 801 select SYS_FSL_HAS_SEC 802 select SYS_FSL_QORIQ_CHASSIS1 803 select SYS_FSL_SEC_BE 804 select SYS_FSL_SEC_COMPAT_4 805 select FSL_ELBC 806 imply CMD_NAND 807 808config ARCH_P3041 809 bool 810 select E500MC 811 select FSL_LAW 812 select SYS_FSL_DDR_VER_44 813 select SYS_FSL_ERRATUM_A004510 814 select SYS_FSL_ERRATUM_A004849 815 select SYS_FSL_ERRATUM_A005812 816 select SYS_FSL_ERRATUM_A006261 817 select SYS_FSL_ERRATUM_CPU_A003999 818 select SYS_FSL_ERRATUM_DDR_A003 819 select SYS_FSL_ERRATUM_DDR_A003474 820 select SYS_FSL_ERRATUM_ESDHC111 821 select SYS_FSL_ERRATUM_I2C_A004447 822 select SYS_FSL_ERRATUM_NMG_CPU_A011 823 select SYS_FSL_ERRATUM_SRIO_A004034 824 select SYS_FSL_ERRATUM_USB14 825 select SYS_FSL_HAS_DDR3 826 select SYS_FSL_HAS_SEC 827 select SYS_FSL_QORIQ_CHASSIS1 828 select SYS_FSL_SEC_BE 829 select SYS_FSL_SEC_COMPAT_4 830 select FSL_ELBC 831 imply CMD_NAND 832 imply CMD_SATA 833 imply CMD_REGINFO 834 imply FSL_SATA 835 836config ARCH_P4080 837 bool 838 select E500MC 839 select FSL_LAW 840 select SYS_FSL_DDR_VER_44 841 select SYS_FSL_ERRATUM_A004510 842 select SYS_FSL_ERRATUM_A004580 843 select SYS_FSL_ERRATUM_A004849 844 select SYS_FSL_ERRATUM_A005812 845 select SYS_FSL_ERRATUM_A007075 846 select SYS_FSL_ERRATUM_CPC_A002 847 select SYS_FSL_ERRATUM_CPC_A003 848 select SYS_FSL_ERRATUM_CPU_A003999 849 select SYS_FSL_ERRATUM_DDR_A003 850 select SYS_FSL_ERRATUM_DDR_A003474 851 select SYS_FSL_ERRATUM_ELBC_A001 852 select SYS_FSL_ERRATUM_ESDHC111 853 select SYS_FSL_ERRATUM_ESDHC13 854 select SYS_FSL_ERRATUM_ESDHC135 855 select SYS_FSL_ERRATUM_I2C_A004447 856 select SYS_FSL_ERRATUM_NMG_CPU_A011 857 select SYS_FSL_ERRATUM_SRIO_A004034 858 select SYS_P4080_ERRATUM_CPU22 859 select SYS_P4080_ERRATUM_PCIE_A003 860 select SYS_P4080_ERRATUM_SERDES8 861 select SYS_P4080_ERRATUM_SERDES9 862 select SYS_P4080_ERRATUM_SERDES_A001 863 select SYS_P4080_ERRATUM_SERDES_A005 864 select SYS_FSL_HAS_DDR3 865 select SYS_FSL_HAS_SEC 866 select SYS_FSL_QORIQ_CHASSIS1 867 select SYS_FSL_SEC_BE 868 select SYS_FSL_SEC_COMPAT_4 869 select FSL_ELBC 870 imply CMD_SATA 871 imply CMD_REGINFO 872 imply SATA_SIL 873 874config ARCH_P5020 875 bool 876 select E500MC 877 select FSL_LAW 878 select SYS_FSL_DDR_VER_44 879 select SYS_FSL_ERRATUM_A004510 880 select SYS_FSL_ERRATUM_A006261 881 select SYS_FSL_ERRATUM_DDR_A003 882 select SYS_FSL_ERRATUM_DDR_A003474 883 select SYS_FSL_ERRATUM_ESDHC111 884 select SYS_FSL_ERRATUM_I2C_A004447 885 select SYS_FSL_ERRATUM_SRIO_A004034 886 select SYS_FSL_ERRATUM_USB14 887 select SYS_FSL_HAS_DDR3 888 select SYS_FSL_HAS_SEC 889 select SYS_FSL_QORIQ_CHASSIS1 890 select SYS_FSL_SEC_BE 891 select SYS_FSL_SEC_COMPAT_4 892 select SYS_PPC64 893 select FSL_ELBC 894 imply CMD_SATA 895 imply CMD_REGINFO 896 imply FSL_SATA 897 898config ARCH_P5040 899 bool 900 select E500MC 901 select FSL_LAW 902 select SYS_FSL_DDR_VER_44 903 select SYS_FSL_ERRATUM_A004510 904 select SYS_FSL_ERRATUM_A004699 905 select SYS_FSL_ERRATUM_A005812 906 select SYS_FSL_ERRATUM_A006261 907 select SYS_FSL_ERRATUM_DDR_A003 908 select SYS_FSL_ERRATUM_DDR_A003474 909 select SYS_FSL_ERRATUM_ESDHC111 910 select SYS_FSL_ERRATUM_USB14 911 select SYS_FSL_HAS_DDR3 912 select SYS_FSL_HAS_SEC 913 select SYS_FSL_QORIQ_CHASSIS1 914 select SYS_FSL_SEC_BE 915 select SYS_FSL_SEC_COMPAT_4 916 select SYS_PPC64 917 select FSL_ELBC 918 imply CMD_SATA 919 imply CMD_REGINFO 920 imply FSL_SATA 921 922config ARCH_QEMU_E500 923 bool 924 925config ARCH_T1023 926 bool 927 select E500MC 928 select FSL_LAW 929 select SYS_FSL_DDR_VER_50 930 select SYS_FSL_ERRATUM_A008378 931 select SYS_FSL_ERRATUM_A009663 932 select SYS_FSL_ERRATUM_A009942 933 select SYS_FSL_ERRATUM_ESDHC111 934 select SYS_FSL_HAS_DDR3 935 select SYS_FSL_HAS_DDR4 936 select SYS_FSL_HAS_SEC 937 select SYS_FSL_QORIQ_CHASSIS2 938 select SYS_FSL_SEC_BE 939 select SYS_FSL_SEC_COMPAT_5 940 select FSL_IFC 941 imply CMD_EEPROM 942 imply CMD_NAND 943 imply CMD_REGINFO 944 945config ARCH_T1024 946 bool 947 select E500MC 948 select FSL_LAW 949 select SYS_FSL_DDR_VER_50 950 select SYS_FSL_ERRATUM_A008378 951 select SYS_FSL_ERRATUM_A009663 952 select SYS_FSL_ERRATUM_A009942 953 select SYS_FSL_ERRATUM_ESDHC111 954 select SYS_FSL_HAS_DDR3 955 select SYS_FSL_HAS_DDR4 956 select SYS_FSL_HAS_SEC 957 select SYS_FSL_QORIQ_CHASSIS2 958 select SYS_FSL_SEC_BE 959 select SYS_FSL_SEC_COMPAT_5 960 select FSL_IFC 961 imply CMD_EEPROM 962 imply CMD_NAND 963 imply CMD_MTDPARTS 964 imply CMD_REGINFO 965 966config ARCH_T1040 967 bool 968 select E500MC 969 select FSL_LAW 970 select SYS_FSL_DDR_VER_50 971 select SYS_FSL_ERRATUM_A008044 972 select SYS_FSL_ERRATUM_A008378 973 select SYS_FSL_ERRATUM_A009663 974 select SYS_FSL_ERRATUM_A009942 975 select SYS_FSL_ERRATUM_ESDHC111 976 select SYS_FSL_HAS_DDR3 977 select SYS_FSL_HAS_DDR4 978 select SYS_FSL_HAS_SEC 979 select SYS_FSL_QORIQ_CHASSIS2 980 select SYS_FSL_SEC_BE 981 select SYS_FSL_SEC_COMPAT_5 982 select FSL_IFC 983 imply CMD_MTDPARTS 984 imply CMD_NAND 985 imply CMD_SATA 986 imply CMD_REGINFO 987 imply FSL_SATA 988 989config ARCH_T1042 990 bool 991 select E500MC 992 select FSL_LAW 993 select SYS_FSL_DDR_VER_50 994 select SYS_FSL_ERRATUM_A008044 995 select SYS_FSL_ERRATUM_A008378 996 select SYS_FSL_ERRATUM_A009663 997 select SYS_FSL_ERRATUM_A009942 998 select SYS_FSL_ERRATUM_ESDHC111 999 select SYS_FSL_HAS_DDR3 1000 select SYS_FSL_HAS_DDR4 1001 select SYS_FSL_HAS_SEC 1002 select SYS_FSL_QORIQ_CHASSIS2 1003 select SYS_FSL_SEC_BE 1004 select SYS_FSL_SEC_COMPAT_5 1005 select FSL_IFC 1006 imply CMD_MTDPARTS 1007 imply CMD_NAND 1008 imply CMD_SATA 1009 imply CMD_REGINFO 1010 imply FSL_SATA 1011 1012config ARCH_T2080 1013 bool 1014 select E500MC 1015 select E6500 1016 select FSL_LAW 1017 select SYS_FSL_DDR_VER_47 1018 select SYS_FSL_ERRATUM_A006379 1019 select SYS_FSL_ERRATUM_A006593 1020 select SYS_FSL_ERRATUM_A007186 1021 select SYS_FSL_ERRATUM_A007212 1022 select SYS_FSL_ERRATUM_A007815 1023 select SYS_FSL_ERRATUM_A007907 1024 select SYS_FSL_ERRATUM_A009942 1025 select SYS_FSL_ERRATUM_ESDHC111 1026 select SYS_FSL_HAS_DDR3 1027 select SYS_FSL_HAS_SEC 1028 select SYS_FSL_QORIQ_CHASSIS2 1029 select SYS_FSL_SEC_BE 1030 select SYS_FSL_SEC_COMPAT_4 1031 select SYS_PPC64 1032 select FSL_IFC 1033 imply CMD_SATA 1034 imply CMD_NAND 1035 imply CMD_REGINFO 1036 imply FSL_SATA 1037 1038config ARCH_T2081 1039 bool 1040 select E500MC 1041 select E6500 1042 select FSL_LAW 1043 select SYS_FSL_DDR_VER_47 1044 select SYS_FSL_ERRATUM_A006379 1045 select SYS_FSL_ERRATUM_A006593 1046 select SYS_FSL_ERRATUM_A007186 1047 select SYS_FSL_ERRATUM_A007212 1048 select SYS_FSL_ERRATUM_A009942 1049 select SYS_FSL_ERRATUM_ESDHC111 1050 select SYS_FSL_HAS_DDR3 1051 select SYS_FSL_HAS_SEC 1052 select SYS_FSL_QORIQ_CHASSIS2 1053 select SYS_FSL_SEC_BE 1054 select SYS_FSL_SEC_COMPAT_4 1055 select SYS_PPC64 1056 select FSL_IFC 1057 imply CMD_NAND 1058 imply CMD_REGINFO 1059 1060config ARCH_T4160 1061 bool 1062 select E500MC 1063 select E6500 1064 select FSL_LAW 1065 select SYS_FSL_DDR_VER_47 1066 select SYS_FSL_ERRATUM_A004468 1067 select SYS_FSL_ERRATUM_A005871 1068 select SYS_FSL_ERRATUM_A006379 1069 select SYS_FSL_ERRATUM_A006593 1070 select SYS_FSL_ERRATUM_A007186 1071 select SYS_FSL_ERRATUM_A007798 1072 select SYS_FSL_ERRATUM_A009942 1073 select SYS_FSL_HAS_DDR3 1074 select SYS_FSL_HAS_SEC 1075 select SYS_FSL_QORIQ_CHASSIS2 1076 select SYS_FSL_SEC_BE 1077 select SYS_FSL_SEC_COMPAT_4 1078 select SYS_PPC64 1079 select FSL_IFC 1080 imply CMD_SATA 1081 imply CMD_NAND 1082 imply CMD_REGINFO 1083 imply FSL_SATA 1084 1085config ARCH_T4240 1086 bool 1087 select E500MC 1088 select E6500 1089 select FSL_LAW 1090 select SYS_FSL_DDR_VER_47 1091 select SYS_FSL_ERRATUM_A004468 1092 select SYS_FSL_ERRATUM_A005871 1093 select SYS_FSL_ERRATUM_A006261 1094 select SYS_FSL_ERRATUM_A006379 1095 select SYS_FSL_ERRATUM_A006593 1096 select SYS_FSL_ERRATUM_A007186 1097 select SYS_FSL_ERRATUM_A007798 1098 select SYS_FSL_ERRATUM_A007815 1099 select SYS_FSL_ERRATUM_A007907 1100 select SYS_FSL_ERRATUM_A009942 1101 select SYS_FSL_HAS_DDR3 1102 select SYS_FSL_HAS_SEC 1103 select SYS_FSL_QORIQ_CHASSIS2 1104 select SYS_FSL_SEC_BE 1105 select SYS_FSL_SEC_COMPAT_4 1106 select SYS_PPC64 1107 select FSL_IFC 1108 imply CMD_SATA 1109 imply CMD_NAND 1110 imply CMD_REGINFO 1111 imply FSL_SATA 1112 1113config BOOKE 1114 bool 1115 default y 1116 1117config E500 1118 bool 1119 default y 1120 help 1121 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 1122 1123config E500MC 1124 bool 1125 imply CMD_PCI 1126 help 1127 Enble PowerPC E500MC core 1128 1129config E6500 1130 bool 1131 help 1132 Enable PowerPC E6500 core 1133 1134config FSL_LAW 1135 bool 1136 help 1137 Use Freescale common code for Local Access Window 1138 1139config SECURE_BOOT 1140 bool "Secure Boot" 1141 help 1142 Enable Freescale Secure Boot feature. Normally selected 1143 by defconfig. If unsure, do not change. 1144 1145config MAX_CPUS 1146 int "Maximum number of CPUs permitted for MPC85xx" 1147 default 12 if ARCH_T4240 1148 default 8 if ARCH_P4080 || \ 1149 ARCH_T4160 1150 default 4 if ARCH_B4860 || \ 1151 ARCH_P2041 || \ 1152 ARCH_P3041 || \ 1153 ARCH_P5040 || \ 1154 ARCH_T1040 || \ 1155 ARCH_T1042 || \ 1156 ARCH_T2080 || \ 1157 ARCH_T2081 1158 default 2 if ARCH_B4420 || \ 1159 ARCH_BSC9132 || \ 1160 ARCH_MPC8572 || \ 1161 ARCH_P1020 || \ 1162 ARCH_P1021 || \ 1163 ARCH_P1022 || \ 1164 ARCH_P1023 || \ 1165 ARCH_P1024 || \ 1166 ARCH_P1025 || \ 1167 ARCH_P2020 || \ 1168 ARCH_P5020 || \ 1169 ARCH_T1023 || \ 1170 ARCH_T1024 1171 default 1 1172 help 1173 Set this number to the maximum number of possible CPUs in the SoC. 1174 SoCs may have multiple clusters with each cluster may have multiple 1175 ports. If some ports are reserved but higher ports are used for 1176 cores, count the reserved ports. This will allocate enough memory 1177 in spin table to properly handle all cores. 1178 1179config SYS_CCSRBAR_DEFAULT 1180 hex "Default CCSRBAR address" 1181 default 0xff700000 if ARCH_BSC9131 || \ 1182 ARCH_BSC9132 || \ 1183 ARCH_C29X || \ 1184 ARCH_MPC8536 || \ 1185 ARCH_MPC8540 || \ 1186 ARCH_MPC8541 || \ 1187 ARCH_MPC8544 || \ 1188 ARCH_MPC8548 || \ 1189 ARCH_MPC8555 || \ 1190 ARCH_MPC8560 || \ 1191 ARCH_MPC8568 || \ 1192 ARCH_MPC8569 || \ 1193 ARCH_MPC8572 || \ 1194 ARCH_P1010 || \ 1195 ARCH_P1011 || \ 1196 ARCH_P1020 || \ 1197 ARCH_P1021 || \ 1198 ARCH_P1022 || \ 1199 ARCH_P1024 || \ 1200 ARCH_P1025 || \ 1201 ARCH_P2020 1202 default 0xff600000 if ARCH_P1023 1203 default 0xfe000000 if ARCH_B4420 || \ 1204 ARCH_B4860 || \ 1205 ARCH_P2041 || \ 1206 ARCH_P3041 || \ 1207 ARCH_P4080 || \ 1208 ARCH_P5020 || \ 1209 ARCH_P5040 || \ 1210 ARCH_T1023 || \ 1211 ARCH_T1024 || \ 1212 ARCH_T1040 || \ 1213 ARCH_T1042 || \ 1214 ARCH_T2080 || \ 1215 ARCH_T2081 || \ 1216 ARCH_T4160 || \ 1217 ARCH_T4240 1218 default 0xe0000000 if ARCH_QEMU_E500 1219 help 1220 Default value of CCSRBAR comes from power-on-reset. It 1221 is fixed on each SoC. Some SoCs can have different value 1222 if changed by pre-boot regime. The value here must match 1223 the current value in SoC. If not sure, do not change. 1224 1225config SYS_FSL_ERRATUM_A004468 1226 bool 1227 1228config SYS_FSL_ERRATUM_A004477 1229 bool 1230 1231config SYS_FSL_ERRATUM_A004508 1232 bool 1233 1234config SYS_FSL_ERRATUM_A004580 1235 bool 1236 1237config SYS_FSL_ERRATUM_A004699 1238 bool 1239 1240config SYS_FSL_ERRATUM_A004849 1241 bool 1242 1243config SYS_FSL_ERRATUM_A004510 1244 bool 1245 1246config SYS_FSL_ERRATUM_A004510_SVR_REV 1247 hex 1248 depends on SYS_FSL_ERRATUM_A004510 1249 default 0x20 if ARCH_P4080 1250 default 0x10 1251 1252config SYS_FSL_ERRATUM_A004510_SVR_REV2 1253 hex 1254 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1255 default 0x11 1256 1257config SYS_FSL_ERRATUM_A005125 1258 bool 1259 1260config SYS_FSL_ERRATUM_A005434 1261 bool 1262 1263config SYS_FSL_ERRATUM_A005812 1264 bool 1265 1266config SYS_FSL_ERRATUM_A005871 1267 bool 1268 1269config SYS_FSL_ERRATUM_A006261 1270 bool 1271 1272config SYS_FSL_ERRATUM_A006379 1273 bool 1274 1275config SYS_FSL_ERRATUM_A006384 1276 bool 1277 1278config SYS_FSL_ERRATUM_A006475 1279 bool 1280 1281config SYS_FSL_ERRATUM_A006593 1282 bool 1283 1284config SYS_FSL_ERRATUM_A007075 1285 bool 1286 1287config SYS_FSL_ERRATUM_A007186 1288 bool 1289 1290config SYS_FSL_ERRATUM_A007212 1291 bool 1292 1293config SYS_FSL_ERRATUM_A007815 1294 bool 1295 1296config SYS_FSL_ERRATUM_A007798 1297 bool 1298 1299config SYS_FSL_ERRATUM_A007907 1300 bool 1301 1302config SYS_FSL_ERRATUM_A008044 1303 bool 1304 1305config SYS_FSL_ERRATUM_CPC_A002 1306 bool 1307 1308config SYS_FSL_ERRATUM_CPC_A003 1309 bool 1310 1311config SYS_FSL_ERRATUM_CPU_A003999 1312 bool 1313 1314config SYS_FSL_ERRATUM_ELBC_A001 1315 bool 1316 1317config SYS_FSL_ERRATUM_I2C_A004447 1318 bool 1319 1320config SYS_FSL_A004447_SVR_REV 1321 hex 1322 depends on SYS_FSL_ERRATUM_I2C_A004447 1323 default 0x00 if ARCH_MPC8548 1324 default 0x10 if ARCH_P1010 1325 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1326 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1327 1328config SYS_FSL_ERRATUM_IFC_A002769 1329 bool 1330 1331config SYS_FSL_ERRATUM_IFC_A003399 1332 bool 1333 1334config SYS_FSL_ERRATUM_NMG_CPU_A011 1335 bool 1336 1337config SYS_FSL_ERRATUM_NMG_ETSEC129 1338 bool 1339 1340config SYS_FSL_ERRATUM_NMG_LBC103 1341 bool 1342 1343config SYS_FSL_ERRATUM_P1010_A003549 1344 bool 1345 1346config SYS_FSL_ERRATUM_SATA_A001 1347 bool 1348 1349config SYS_FSL_ERRATUM_SEC_A003571 1350 bool 1351 1352config SYS_FSL_ERRATUM_SRIO_A004034 1353 bool 1354 1355config SYS_FSL_ERRATUM_USB14 1356 bool 1357 1358config SYS_P4080_ERRATUM_CPU22 1359 bool 1360 1361config SYS_P4080_ERRATUM_PCIE_A003 1362 bool 1363 1364config SYS_P4080_ERRATUM_SERDES8 1365 bool 1366 1367config SYS_P4080_ERRATUM_SERDES9 1368 bool 1369 1370config SYS_P4080_ERRATUM_SERDES_A001 1371 bool 1372 1373config SYS_P4080_ERRATUM_SERDES_A005 1374 bool 1375 1376config SYS_FSL_QORIQ_CHASSIS1 1377 bool 1378 1379config SYS_FSL_QORIQ_CHASSIS2 1380 bool 1381 1382config SYS_FSL_NUM_LAWS 1383 int "Number of local access windows" 1384 depends on FSL_LAW 1385 default 32 if ARCH_B4420 || \ 1386 ARCH_B4860 || \ 1387 ARCH_P2041 || \ 1388 ARCH_P3041 || \ 1389 ARCH_P4080 || \ 1390 ARCH_P5020 || \ 1391 ARCH_P5040 || \ 1392 ARCH_T2080 || \ 1393 ARCH_T2081 || \ 1394 ARCH_T4160 || \ 1395 ARCH_T4240 1396 default 16 if ARCH_T1023 || \ 1397 ARCH_T1024 || \ 1398 ARCH_T1040 || \ 1399 ARCH_T1042 1400 default 12 if ARCH_BSC9131 || \ 1401 ARCH_BSC9132 || \ 1402 ARCH_C29X || \ 1403 ARCH_MPC8536 || \ 1404 ARCH_MPC8572 || \ 1405 ARCH_P1010 || \ 1406 ARCH_P1011 || \ 1407 ARCH_P1020 || \ 1408 ARCH_P1021 || \ 1409 ARCH_P1022 || \ 1410 ARCH_P1023 || \ 1411 ARCH_P1024 || \ 1412 ARCH_P1025 || \ 1413 ARCH_P2020 1414 default 10 if ARCH_MPC8544 || \ 1415 ARCH_MPC8548 || \ 1416 ARCH_MPC8568 || \ 1417 ARCH_MPC8569 1418 default 8 if ARCH_MPC8540 || \ 1419 ARCH_MPC8541 || \ 1420 ARCH_MPC8555 || \ 1421 ARCH_MPC8560 1422 help 1423 Number of local access windows. This is fixed per SoC. 1424 If not sure, do not change. 1425 1426config SYS_FSL_THREADS_PER_CORE 1427 int 1428 default 2 if E6500 1429 default 1 1430 1431config SYS_NUM_TLBCAMS 1432 int "Number of TLB CAM entries" 1433 default 64 if E500MC 1434 default 16 1435 help 1436 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1437 16 for other E500 SoCs. 1438 1439config SYS_PPC64 1440 bool 1441 1442config SYS_PPC_E500_USE_DEBUG_TLB 1443 bool 1444 1445config FSL_IFC 1446 bool 1447 1448config FSL_ELBC 1449 bool 1450 1451config SYS_PPC_E500_DEBUG_TLB 1452 int "Temporary TLB entry for external debugger" 1453 depends on SYS_PPC_E500_USE_DEBUG_TLB 1454 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1455 default 1 if ARCH_MPC8536 1456 default 2 if ARCH_MPC8572 || \ 1457 ARCH_P1011 || \ 1458 ARCH_P1020 || \ 1459 ARCH_P1021 || \ 1460 ARCH_P1022 || \ 1461 ARCH_P1024 || \ 1462 ARCH_P1025 || \ 1463 ARCH_P2020 1464 default 3 if ARCH_P1010 || \ 1465 ARCH_BSC9132 || \ 1466 ARCH_C29X 1467 help 1468 Select a temporary TLB entry to be used during boot to work 1469 around limitations in e500v1 and e500v2 external debugger 1470 support. This reduces the portions of the boot code where 1471 breakpoints and single stepping do not work. The value of this 1472 symbol should be set to the TLB1 entry to be used for this 1473 purpose. If unsure, do not change. 1474 1475config SYS_FSL_IFC_CLK_DIV 1476 int "Divider of platform clock" 1477 depends on FSL_IFC 1478 default 2 if ARCH_B4420 || \ 1479 ARCH_B4860 || \ 1480 ARCH_T1024 || \ 1481 ARCH_T1023 || \ 1482 ARCH_T1040 || \ 1483 ARCH_T1042 || \ 1484 ARCH_T4160 || \ 1485 ARCH_T4240 1486 default 1 1487 help 1488 Defines divider of platform clock(clock input to 1489 IFC controller). 1490 1491config SYS_FSL_LBC_CLK_DIV 1492 int "Divider of platform clock" 1493 depends on FSL_ELBC || ARCH_MPC8540 || \ 1494 ARCH_MPC8548 || ARCH_MPC8541 || \ 1495 ARCH_MPC8555 || ARCH_MPC8560 || \ 1496 ARCH_MPC8568 1497 1498 default 2 if ARCH_P2041 || \ 1499 ARCH_P3041 || \ 1500 ARCH_P4080 || \ 1501 ARCH_P5020 || \ 1502 ARCH_P5040 1503 default 1 1504 1505 help 1506 Defines divider of platform clock(clock input to 1507 eLBC controller). 1508 1509source "board/freescale/b4860qds/Kconfig" 1510source "board/freescale/bsc9131rdb/Kconfig" 1511source "board/freescale/bsc9132qds/Kconfig" 1512source "board/freescale/c29xpcie/Kconfig" 1513source "board/freescale/corenet_ds/Kconfig" 1514source "board/freescale/mpc8536ds/Kconfig" 1515source "board/freescale/mpc8541cds/Kconfig" 1516source "board/freescale/mpc8544ds/Kconfig" 1517source "board/freescale/mpc8548cds/Kconfig" 1518source "board/freescale/mpc8555cds/Kconfig" 1519source "board/freescale/mpc8568mds/Kconfig" 1520source "board/freescale/mpc8569mds/Kconfig" 1521source "board/freescale/mpc8572ds/Kconfig" 1522source "board/freescale/p1010rdb/Kconfig" 1523source "board/freescale/p1022ds/Kconfig" 1524source "board/freescale/p1023rdb/Kconfig" 1525source "board/freescale/p1_p2_rdb_pc/Kconfig" 1526source "board/freescale/p1_twr/Kconfig" 1527source "board/freescale/p2041rdb/Kconfig" 1528source "board/freescale/qemu-ppce500/Kconfig" 1529source "board/freescale/t102xqds/Kconfig" 1530source "board/freescale/t102xrdb/Kconfig" 1531source "board/freescale/t1040qds/Kconfig" 1532source "board/freescale/t104xrdb/Kconfig" 1533source "board/freescale/t208xqds/Kconfig" 1534source "board/freescale/t208xrdb/Kconfig" 1535source "board/freescale/t4qds/Kconfig" 1536source "board/freescale/t4rdb/Kconfig" 1537source "board/gdsys/p1022/Kconfig" 1538source "board/keymile/kmp204x/Kconfig" 1539source "board/sbc8548/Kconfig" 1540source "board/socrates/Kconfig" 1541source "board/varisys/cyrus/Kconfig" 1542source "board/xes/xpedite520x/Kconfig" 1543source "board/xes/xpedite537x/Kconfig" 1544source "board/xes/xpedite550x/Kconfig" 1545source "board/Arcturus/ucp1020/Kconfig" 1546 1547endmenu 1548