1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 imply ENV_IS_IN_FLASH 23 24config TARGET_SOCRATES 25 bool "Support socrates" 26 select ARCH_MPC8544 27 28config TARGET_B4420QDS 29 bool "Support B4420QDS" 30 select ARCH_B4420 31 select SUPPORT_SPL 32 select PHYS_64BIT 33 34config TARGET_B4860QDS 35 bool "Support B4860QDS" 36 select ARCH_B4860 37 select BOARD_LATE_INIT if CHAIN_OF_TRUST 38 select SUPPORT_SPL 39 select PHYS_64BIT 40 41config TARGET_BSC9131RDB 42 bool "Support BSC9131RDB" 43 select ARCH_BSC9131 44 select SUPPORT_SPL 45 select BOARD_EARLY_INIT_F 46 47config TARGET_BSC9132QDS 48 bool "Support BSC9132QDS" 49 select ARCH_BSC9132 50 select BOARD_LATE_INIT if CHAIN_OF_TRUST 51 select SUPPORT_SPL 52 select BOARD_EARLY_INIT_F 53 54config TARGET_C29XPCIE 55 bool "Support C29XPCIE" 56 select ARCH_C29X 57 select BOARD_LATE_INIT if CHAIN_OF_TRUST 58 select SUPPORT_SPL 59 select SUPPORT_TPL 60 select PHYS_64BIT 61 62config TARGET_P3041DS 63 bool "Support P3041DS" 64 select PHYS_64BIT 65 select ARCH_P3041 66 select BOARD_LATE_INIT if CHAIN_OF_TRUST 67 imply CMD_SATA 68 69config TARGET_P4080DS 70 bool "Support P4080DS" 71 select PHYS_64BIT 72 select ARCH_P4080 73 select BOARD_LATE_INIT if CHAIN_OF_TRUST 74 imply CMD_SATA 75 76config TARGET_P5020DS 77 bool "Support P5020DS" 78 select PHYS_64BIT 79 select ARCH_P5020 80 select BOARD_LATE_INIT if CHAIN_OF_TRUST 81 imply CMD_SATA 82 83config TARGET_P5040DS 84 bool "Support P5040DS" 85 select PHYS_64BIT 86 select ARCH_P5040 87 select BOARD_LATE_INIT if CHAIN_OF_TRUST 88 imply CMD_SATA 89 90config TARGET_MPC8536DS 91 bool "Support MPC8536DS" 92 select ARCH_MPC8536 93# Use DDR3 controller with DDR2 DIMMs on this board 94 select SYS_FSL_DDRC_GEN3 95 imply CMD_SATA 96 97config TARGET_MPC8541CDS 98 bool "Support MPC8541CDS" 99 select ARCH_MPC8541 100 101config TARGET_MPC8544DS 102 bool "Support MPC8544DS" 103 select ARCH_MPC8544 104 105config TARGET_MPC8548CDS 106 bool "Support MPC8548CDS" 107 select ARCH_MPC8548 108 imply ENV_IS_IN_FLASH 109 110config TARGET_MPC8555CDS 111 bool "Support MPC8555CDS" 112 select ARCH_MPC8555 113 114config TARGET_MPC8568MDS 115 bool "Support MPC8568MDS" 116 select ARCH_MPC8568 117 118config TARGET_MPC8569MDS 119 bool "Support MPC8569MDS" 120 select ARCH_MPC8569 121 122config TARGET_MPC8572DS 123 bool "Support MPC8572DS" 124 select ARCH_MPC8572 125# Use DDR3 controller with DDR2 DIMMs on this board 126 select SYS_FSL_DDRC_GEN3 127 imply SCSI 128 129config TARGET_P1010RDB_PA 130 bool "Support P1010RDB_PA" 131 select ARCH_P1010 132 select BOARD_LATE_INIT if CHAIN_OF_TRUST 133 select SUPPORT_SPL 134 select SUPPORT_TPL 135 imply CMD_EEPROM 136 imply CMD_SATA 137 138config TARGET_P1010RDB_PB 139 bool "Support P1010RDB_PB" 140 select ARCH_P1010 141 select BOARD_LATE_INIT if CHAIN_OF_TRUST 142 select SUPPORT_SPL 143 select SUPPORT_TPL 144 imply CMD_EEPROM 145 imply CMD_SATA 146 147config TARGET_P1022DS 148 bool "Support P1022DS" 149 select ARCH_P1022 150 select SUPPORT_SPL 151 select SUPPORT_TPL 152 imply CMD_SATA 153 154config TARGET_P1023RDB 155 bool "Support P1023RDB" 156 select ARCH_P1023 157 imply CMD_EEPROM 158 159config TARGET_P1020MBG 160 bool "Support P1020MBG-PC" 161 select SUPPORT_SPL 162 select SUPPORT_TPL 163 select ARCH_P1020 164 imply CMD_EEPROM 165 imply CMD_SATA 166 167config TARGET_P1020RDB_PC 168 bool "Support P1020RDB-PC" 169 select SUPPORT_SPL 170 select SUPPORT_TPL 171 select ARCH_P1020 172 imply CMD_EEPROM 173 imply CMD_SATA 174 175config TARGET_P1020RDB_PD 176 bool "Support P1020RDB-PD" 177 select SUPPORT_SPL 178 select SUPPORT_TPL 179 select ARCH_P1020 180 imply CMD_EEPROM 181 imply CMD_SATA 182 183config TARGET_P1020UTM 184 bool "Support P1020UTM" 185 select SUPPORT_SPL 186 select SUPPORT_TPL 187 select ARCH_P1020 188 imply CMD_EEPROM 189 imply CMD_SATA 190 191config TARGET_P1021RDB 192 bool "Support P1021RDB" 193 select SUPPORT_SPL 194 select SUPPORT_TPL 195 select ARCH_P1021 196 imply CMD_EEPROM 197 imply CMD_SATA 198 199config TARGET_P1024RDB 200 bool "Support P1024RDB" 201 select SUPPORT_SPL 202 select SUPPORT_TPL 203 select ARCH_P1024 204 imply CMD_EEPROM 205 imply CMD_SATA 206 207config TARGET_P1025RDB 208 bool "Support P1025RDB" 209 select SUPPORT_SPL 210 select SUPPORT_TPL 211 select ARCH_P1025 212 imply CMD_EEPROM 213 imply CMD_SATA 214 215config TARGET_P2020RDB 216 bool "Support P2020RDB-PC" 217 select SUPPORT_SPL 218 select SUPPORT_TPL 219 select ARCH_P2020 220 imply CMD_EEPROM 221 imply CMD_SATA 222 223config TARGET_P1_TWR 224 bool "Support p1_twr" 225 select ARCH_P1025 226 227config TARGET_P2041RDB 228 bool "Support P2041RDB" 229 select ARCH_P2041 230 select BOARD_LATE_INIT if CHAIN_OF_TRUST 231 select PHYS_64BIT 232 imply CMD_SATA 233 234config TARGET_QEMU_PPCE500 235 bool "Support qemu-ppce500" 236 select ARCH_QEMU_E500 237 select PHYS_64BIT 238 239config TARGET_T1024QDS 240 bool "Support T1024QDS" 241 select ARCH_T1024 242 select BOARD_LATE_INIT if CHAIN_OF_TRUST 243 select SUPPORT_SPL 244 select PHYS_64BIT 245 imply CMD_EEPROM 246 imply CMD_SATA 247 248config TARGET_T1023RDB 249 bool "Support T1023RDB" 250 select ARCH_T1023 251 select BOARD_LATE_INIT if CHAIN_OF_TRUST 252 select SUPPORT_SPL 253 select PHYS_64BIT 254 imply CMD_EEPROM 255 256config TARGET_T1024RDB 257 bool "Support T1024RDB" 258 select ARCH_T1024 259 select BOARD_LATE_INIT if CHAIN_OF_TRUST 260 select SUPPORT_SPL 261 select PHYS_64BIT 262 imply CMD_EEPROM 263 264config TARGET_T1040QDS 265 bool "Support T1040QDS" 266 select ARCH_T1040 267 select BOARD_LATE_INIT if CHAIN_OF_TRUST 268 select PHYS_64BIT 269 imply CMD_EEPROM 270 imply CMD_SATA 271 272config TARGET_T1040RDB 273 bool "Support T1040RDB" 274 select ARCH_T1040 275 select BOARD_LATE_INIT if CHAIN_OF_TRUST 276 select SUPPORT_SPL 277 select PHYS_64BIT 278 imply CMD_SATA 279 280config TARGET_T1040D4RDB 281 bool "Support T1040D4RDB" 282 select ARCH_T1040 283 select BOARD_LATE_INIT if CHAIN_OF_TRUST 284 select SUPPORT_SPL 285 select PHYS_64BIT 286 imply CMD_SATA 287 288config TARGET_T1042RDB 289 bool "Support T1042RDB" 290 select ARCH_T1042 291 select BOARD_LATE_INIT if CHAIN_OF_TRUST 292 select SUPPORT_SPL 293 select PHYS_64BIT 294 imply CMD_SATA 295 296config TARGET_T1042D4RDB 297 bool "Support T1042D4RDB" 298 select ARCH_T1042 299 select BOARD_LATE_INIT if CHAIN_OF_TRUST 300 select SUPPORT_SPL 301 select PHYS_64BIT 302 imply CMD_SATA 303 304config TARGET_T1042RDB_PI 305 bool "Support T1042RDB_PI" 306 select ARCH_T1042 307 select BOARD_LATE_INIT if CHAIN_OF_TRUST 308 select SUPPORT_SPL 309 select PHYS_64BIT 310 imply CMD_SATA 311 312config TARGET_T2080QDS 313 bool "Support T2080QDS" 314 select ARCH_T2080 315 select BOARD_LATE_INIT if CHAIN_OF_TRUST 316 select SUPPORT_SPL 317 select PHYS_64BIT 318 imply CMD_SATA 319 320config TARGET_T2080RDB 321 bool "Support T2080RDB" 322 select ARCH_T2080 323 select BOARD_LATE_INIT if CHAIN_OF_TRUST 324 select SUPPORT_SPL 325 select PHYS_64BIT 326 imply CMD_SATA 327 328config TARGET_T2081QDS 329 bool "Support T2081QDS" 330 select ARCH_T2081 331 select SUPPORT_SPL 332 select PHYS_64BIT 333 334config TARGET_T4160QDS 335 bool "Support T4160QDS" 336 select ARCH_T4160 337 select BOARD_LATE_INIT if CHAIN_OF_TRUST 338 select SUPPORT_SPL 339 select PHYS_64BIT 340 imply CMD_SATA 341 342config TARGET_T4160RDB 343 bool "Support T4160RDB" 344 select ARCH_T4160 345 select SUPPORT_SPL 346 select PHYS_64BIT 347 348config TARGET_T4240QDS 349 bool "Support T4240QDS" 350 select ARCH_T4240 351 select BOARD_LATE_INIT if CHAIN_OF_TRUST 352 select SUPPORT_SPL 353 select PHYS_64BIT 354 imply CMD_SATA 355 356config TARGET_T4240RDB 357 bool "Support T4240RDB" 358 select ARCH_T4240 359 select SUPPORT_SPL 360 select PHYS_64BIT 361 imply CMD_SATA 362 363config TARGET_CONTROLCENTERD 364 bool "Support controlcenterd" 365 select ARCH_P1022 366 367config TARGET_KMP204X 368 bool "Support kmp204x" 369 select ARCH_P2041 370 select PHYS_64BIT 371 imply CMD_CRAMFS 372 imply FS_CRAMFS 373 374config TARGET_XPEDITE520X 375 bool "Support xpedite520x" 376 select ARCH_MPC8548 377 378config TARGET_XPEDITE537X 379 bool "Support xpedite537x" 380 select ARCH_MPC8572 381# Use DDR3 controller with DDR2 DIMMs on this board 382 select SYS_FSL_DDRC_GEN3 383 384config TARGET_XPEDITE550X 385 bool "Support xpedite550x" 386 select ARCH_P2020 387 388config TARGET_UCP1020 389 bool "Support uCP1020" 390 select ARCH_P1020 391 imply CMD_SATA 392 393config TARGET_CYRUS_P5020 394 bool "Support Varisys Cyrus P5020" 395 select ARCH_P5020 396 select PHYS_64BIT 397 398config TARGET_CYRUS_P5040 399 bool "Support Varisys Cyrus P5040" 400 select ARCH_P5040 401 select PHYS_64BIT 402 403endchoice 404 405config ARCH_B4420 406 bool 407 select E500MC 408 select E6500 409 select FSL_LAW 410 select SYS_FSL_DDR_VER_47 411 select SYS_FSL_ERRATUM_A004477 412 select SYS_FSL_ERRATUM_A005871 413 select SYS_FSL_ERRATUM_A006379 414 select SYS_FSL_ERRATUM_A006384 415 select SYS_FSL_ERRATUM_A006475 416 select SYS_FSL_ERRATUM_A006593 417 select SYS_FSL_ERRATUM_A007075 418 select SYS_FSL_ERRATUM_A007186 419 select SYS_FSL_ERRATUM_A007212 420 select SYS_FSL_ERRATUM_A009942 421 select SYS_FSL_HAS_DDR3 422 select SYS_FSL_HAS_SEC 423 select SYS_FSL_QORIQ_CHASSIS2 424 select SYS_FSL_SEC_BE 425 select SYS_FSL_SEC_COMPAT_4 426 select SYS_PPC64 427 select FSL_IFC 428 imply CMD_EEPROM 429 imply CMD_NAND 430 431config ARCH_B4860 432 bool 433 select E500MC 434 select E6500 435 select FSL_LAW 436 select SYS_FSL_DDR_VER_47 437 select SYS_FSL_ERRATUM_A004477 438 select SYS_FSL_ERRATUM_A005871 439 select SYS_FSL_ERRATUM_A006379 440 select SYS_FSL_ERRATUM_A006384 441 select SYS_FSL_ERRATUM_A006475 442 select SYS_FSL_ERRATUM_A006593 443 select SYS_FSL_ERRATUM_A007075 444 select SYS_FSL_ERRATUM_A007186 445 select SYS_FSL_ERRATUM_A007212 446 select SYS_FSL_ERRATUM_A007907 447 select SYS_FSL_ERRATUM_A009942 448 select SYS_FSL_HAS_DDR3 449 select SYS_FSL_HAS_SEC 450 select SYS_FSL_QORIQ_CHASSIS2 451 select SYS_FSL_SEC_BE 452 select SYS_FSL_SEC_COMPAT_4 453 select SYS_PPC64 454 select FSL_IFC 455 imply CMD_EEPROM 456 imply CMD_NAND 457 458config ARCH_BSC9131 459 bool 460 select FSL_LAW 461 select SYS_FSL_DDR_VER_44 462 select SYS_FSL_ERRATUM_A004477 463 select SYS_FSL_ERRATUM_A005125 464 select SYS_FSL_ERRATUM_ESDHC111 465 select SYS_FSL_HAS_DDR3 466 select SYS_FSL_HAS_SEC 467 select SYS_FSL_SEC_BE 468 select SYS_FSL_SEC_COMPAT_4 469 select FSL_IFC 470 imply CMD_EEPROM 471 imply CMD_NAND 472 473config ARCH_BSC9132 474 bool 475 select FSL_LAW 476 select SYS_FSL_DDR_VER_46 477 select SYS_FSL_ERRATUM_A004477 478 select SYS_FSL_ERRATUM_A005125 479 select SYS_FSL_ERRATUM_A005434 480 select SYS_FSL_ERRATUM_ESDHC111 481 select SYS_FSL_ERRATUM_I2C_A004447 482 select SYS_FSL_ERRATUM_IFC_A002769 483 select SYS_FSL_HAS_DDR3 484 select SYS_FSL_HAS_SEC 485 select SYS_FSL_SEC_BE 486 select SYS_FSL_SEC_COMPAT_4 487 select SYS_PPC_E500_USE_DEBUG_TLB 488 select FSL_IFC 489 imply CMD_EEPROM 490 imply CMD_MTDPARTS 491 imply CMD_NAND 492 493config ARCH_C29X 494 bool 495 select FSL_LAW 496 select SYS_FSL_DDR_VER_46 497 select SYS_FSL_ERRATUM_A005125 498 select SYS_FSL_ERRATUM_ESDHC111 499 select SYS_FSL_HAS_DDR3 500 select SYS_FSL_HAS_SEC 501 select SYS_FSL_SEC_BE 502 select SYS_FSL_SEC_COMPAT_6 503 select SYS_PPC_E500_USE_DEBUG_TLB 504 select FSL_IFC 505 imply CMD_NAND 506 507config ARCH_MPC8536 508 bool 509 select FSL_LAW 510 select SYS_FSL_ERRATUM_A004508 511 select SYS_FSL_ERRATUM_A005125 512 select SYS_FSL_HAS_DDR2 513 select SYS_FSL_HAS_DDR3 514 select SYS_FSL_HAS_SEC 515 select SYS_FSL_SEC_BE 516 select SYS_FSL_SEC_COMPAT_2 517 select SYS_PPC_E500_USE_DEBUG_TLB 518 select FSL_ELBC 519 imply CMD_NAND 520 imply CMD_SATA 521 522config ARCH_MPC8540 523 bool 524 select FSL_LAW 525 select SYS_FSL_HAS_DDR1 526 527config ARCH_MPC8541 528 bool 529 select FSL_LAW 530 select SYS_FSL_HAS_DDR1 531 select SYS_FSL_HAS_SEC 532 select SYS_FSL_SEC_BE 533 select SYS_FSL_SEC_COMPAT_2 534 535config ARCH_MPC8544 536 bool 537 select FSL_LAW 538 select SYS_FSL_ERRATUM_A005125 539 select SYS_FSL_HAS_DDR2 540 select SYS_FSL_HAS_SEC 541 select SYS_FSL_SEC_BE 542 select SYS_FSL_SEC_COMPAT_2 543 select SYS_PPC_E500_USE_DEBUG_TLB 544 select FSL_ELBC 545 546config ARCH_MPC8548 547 bool 548 select FSL_LAW 549 select SYS_FSL_ERRATUM_A005125 550 select SYS_FSL_ERRATUM_NMG_DDR120 551 select SYS_FSL_ERRATUM_NMG_LBC103 552 select SYS_FSL_ERRATUM_NMG_ETSEC129 553 select SYS_FSL_ERRATUM_I2C_A004447 554 select SYS_FSL_HAS_DDR2 555 select SYS_FSL_HAS_DDR1 556 select SYS_FSL_HAS_SEC 557 select SYS_FSL_SEC_BE 558 select SYS_FSL_SEC_COMPAT_2 559 select SYS_PPC_E500_USE_DEBUG_TLB 560 imply ENV_IS_IN_FLASH 561 562config ARCH_MPC8555 563 bool 564 select FSL_LAW 565 select SYS_FSL_HAS_DDR1 566 select SYS_FSL_HAS_SEC 567 select SYS_FSL_SEC_BE 568 select SYS_FSL_SEC_COMPAT_2 569 570config ARCH_MPC8560 571 bool 572 select FSL_LAW 573 select SYS_FSL_HAS_DDR1 574 575config ARCH_MPC8568 576 bool 577 select FSL_LAW 578 select SYS_FSL_HAS_DDR2 579 select SYS_FSL_HAS_SEC 580 select SYS_FSL_SEC_BE 581 select SYS_FSL_SEC_COMPAT_2 582 583config ARCH_MPC8569 584 bool 585 select FSL_LAW 586 select SYS_FSL_ERRATUM_A004508 587 select SYS_FSL_ERRATUM_A005125 588 select SYS_FSL_HAS_DDR3 589 select SYS_FSL_HAS_SEC 590 select SYS_FSL_SEC_BE 591 select SYS_FSL_SEC_COMPAT_2 592 select FSL_ELBC 593 imply CMD_NAND 594 595config ARCH_MPC8572 596 bool 597 select FSL_LAW 598 select SYS_FSL_ERRATUM_A004508 599 select SYS_FSL_ERRATUM_A005125 600 select SYS_FSL_ERRATUM_DDR_115 601 select SYS_FSL_ERRATUM_DDR111_DDR134 602 select SYS_FSL_HAS_DDR2 603 select SYS_FSL_HAS_DDR3 604 select SYS_FSL_HAS_SEC 605 select SYS_FSL_SEC_BE 606 select SYS_FSL_SEC_COMPAT_2 607 select SYS_PPC_E500_USE_DEBUG_TLB 608 select FSL_ELBC 609 imply CMD_NAND 610 imply ENV_IS_IN_FLASH 611 612config ARCH_P1010 613 bool 614 select FSL_LAW 615 select SYS_FSL_ERRATUM_A004477 616 select SYS_FSL_ERRATUM_A004508 617 select SYS_FSL_ERRATUM_A005125 618 select SYS_FSL_ERRATUM_A006261 619 select SYS_FSL_ERRATUM_A007075 620 select SYS_FSL_ERRATUM_ESDHC111 621 select SYS_FSL_ERRATUM_I2C_A004447 622 select SYS_FSL_ERRATUM_IFC_A002769 623 select SYS_FSL_ERRATUM_P1010_A003549 624 select SYS_FSL_ERRATUM_SEC_A003571 625 select SYS_FSL_ERRATUM_IFC_A003399 626 select SYS_FSL_HAS_DDR3 627 select SYS_FSL_HAS_SEC 628 select SYS_FSL_SEC_BE 629 select SYS_FSL_SEC_COMPAT_4 630 select SYS_PPC_E500_USE_DEBUG_TLB 631 select FSL_IFC 632 imply CMD_EEPROM 633 imply CMD_MTDPARTS 634 imply CMD_NAND 635 imply CMD_SATA 636 637config ARCH_P1011 638 bool 639 select FSL_LAW 640 select SYS_FSL_ERRATUM_A004508 641 select SYS_FSL_ERRATUM_A005125 642 select SYS_FSL_ERRATUM_ELBC_A001 643 select SYS_FSL_ERRATUM_ESDHC111 644 select SYS_FSL_HAS_DDR3 645 select SYS_FSL_HAS_SEC 646 select SYS_FSL_SEC_BE 647 select SYS_FSL_SEC_COMPAT_2 648 select SYS_PPC_E500_USE_DEBUG_TLB 649 select FSL_ELBC 650 651config ARCH_P1020 652 bool 653 select FSL_LAW 654 select SYS_FSL_ERRATUM_A004508 655 select SYS_FSL_ERRATUM_A005125 656 select SYS_FSL_ERRATUM_ELBC_A001 657 select SYS_FSL_ERRATUM_ESDHC111 658 select SYS_FSL_HAS_DDR3 659 select SYS_FSL_HAS_SEC 660 select SYS_FSL_SEC_BE 661 select SYS_FSL_SEC_COMPAT_2 662 select SYS_PPC_E500_USE_DEBUG_TLB 663 select FSL_ELBC 664 imply CMD_NAND 665 imply CMD_SATA 666 667config ARCH_P1021 668 bool 669 select FSL_LAW 670 select SYS_FSL_ERRATUM_A004508 671 select SYS_FSL_ERRATUM_A005125 672 select SYS_FSL_ERRATUM_ELBC_A001 673 select SYS_FSL_ERRATUM_ESDHC111 674 select SYS_FSL_HAS_DDR3 675 select SYS_FSL_HAS_SEC 676 select SYS_FSL_SEC_BE 677 select SYS_FSL_SEC_COMPAT_2 678 select SYS_PPC_E500_USE_DEBUG_TLB 679 select FSL_ELBC 680 imply CMD_NAND 681 imply CMD_SATA 682 683config ARCH_P1022 684 bool 685 select FSL_LAW 686 select SYS_FSL_ERRATUM_A004477 687 select SYS_FSL_ERRATUM_A004508 688 select SYS_FSL_ERRATUM_A005125 689 select SYS_FSL_ERRATUM_ELBC_A001 690 select SYS_FSL_ERRATUM_ESDHC111 691 select SYS_FSL_ERRATUM_SATA_A001 692 select SYS_FSL_HAS_DDR3 693 select SYS_FSL_HAS_SEC 694 select SYS_FSL_SEC_BE 695 select SYS_FSL_SEC_COMPAT_2 696 select SYS_PPC_E500_USE_DEBUG_TLB 697 select FSL_ELBC 698 699config ARCH_P1023 700 bool 701 select FSL_LAW 702 select SYS_FSL_ERRATUM_A004508 703 select SYS_FSL_ERRATUM_A005125 704 select SYS_FSL_ERRATUM_I2C_A004447 705 select SYS_FSL_HAS_DDR3 706 select SYS_FSL_HAS_SEC 707 select SYS_FSL_SEC_BE 708 select SYS_FSL_SEC_COMPAT_4 709 select FSL_ELBC 710 711config ARCH_P1024 712 bool 713 select FSL_LAW 714 select SYS_FSL_ERRATUM_A004508 715 select SYS_FSL_ERRATUM_A005125 716 select SYS_FSL_ERRATUM_ELBC_A001 717 select SYS_FSL_ERRATUM_ESDHC111 718 select SYS_FSL_HAS_DDR3 719 select SYS_FSL_HAS_SEC 720 select SYS_FSL_SEC_BE 721 select SYS_FSL_SEC_COMPAT_2 722 select SYS_PPC_E500_USE_DEBUG_TLB 723 select FSL_ELBC 724 imply CMD_EEPROM 725 imply CMD_NAND 726 imply CMD_SATA 727 728config ARCH_P1025 729 bool 730 select FSL_LAW 731 select SYS_FSL_ERRATUM_A004508 732 select SYS_FSL_ERRATUM_A005125 733 select SYS_FSL_ERRATUM_ELBC_A001 734 select SYS_FSL_ERRATUM_ESDHC111 735 select SYS_FSL_HAS_DDR3 736 select SYS_FSL_HAS_SEC 737 select SYS_FSL_SEC_BE 738 select SYS_FSL_SEC_COMPAT_2 739 select SYS_PPC_E500_USE_DEBUG_TLB 740 select FSL_ELBC 741 imply CMD_SATA 742 743config ARCH_P2020 744 bool 745 select FSL_LAW 746 select SYS_FSL_ERRATUM_A004477 747 select SYS_FSL_ERRATUM_A004508 748 select SYS_FSL_ERRATUM_A005125 749 select SYS_FSL_ERRATUM_ESDHC111 750 select SYS_FSL_ERRATUM_ESDHC_A001 751 select SYS_FSL_HAS_DDR3 752 select SYS_FSL_HAS_SEC 753 select SYS_FSL_SEC_BE 754 select SYS_FSL_SEC_COMPAT_2 755 select SYS_PPC_E500_USE_DEBUG_TLB 756 select FSL_ELBC 757 imply CMD_EEPROM 758 imply CMD_NAND 759 760config ARCH_P2041 761 bool 762 select E500MC 763 select FSL_LAW 764 select SYS_FSL_ERRATUM_A004510 765 select SYS_FSL_ERRATUM_A004849 766 select SYS_FSL_ERRATUM_A006261 767 select SYS_FSL_ERRATUM_CPU_A003999 768 select SYS_FSL_ERRATUM_DDR_A003 769 select SYS_FSL_ERRATUM_DDR_A003474 770 select SYS_FSL_ERRATUM_ESDHC111 771 select SYS_FSL_ERRATUM_I2C_A004447 772 select SYS_FSL_ERRATUM_NMG_CPU_A011 773 select SYS_FSL_ERRATUM_SRIO_A004034 774 select SYS_FSL_ERRATUM_USB14 775 select SYS_FSL_HAS_DDR3 776 select SYS_FSL_HAS_SEC 777 select SYS_FSL_QORIQ_CHASSIS1 778 select SYS_FSL_SEC_BE 779 select SYS_FSL_SEC_COMPAT_4 780 select FSL_ELBC 781 imply CMD_NAND 782 783config ARCH_P3041 784 bool 785 select E500MC 786 select FSL_LAW 787 select SYS_FSL_DDR_VER_44 788 select SYS_FSL_ERRATUM_A004510 789 select SYS_FSL_ERRATUM_A004849 790 select SYS_FSL_ERRATUM_A005812 791 select SYS_FSL_ERRATUM_A006261 792 select SYS_FSL_ERRATUM_CPU_A003999 793 select SYS_FSL_ERRATUM_DDR_A003 794 select SYS_FSL_ERRATUM_DDR_A003474 795 select SYS_FSL_ERRATUM_ESDHC111 796 select SYS_FSL_ERRATUM_I2C_A004447 797 select SYS_FSL_ERRATUM_NMG_CPU_A011 798 select SYS_FSL_ERRATUM_SRIO_A004034 799 select SYS_FSL_ERRATUM_USB14 800 select SYS_FSL_HAS_DDR3 801 select SYS_FSL_HAS_SEC 802 select SYS_FSL_QORIQ_CHASSIS1 803 select SYS_FSL_SEC_BE 804 select SYS_FSL_SEC_COMPAT_4 805 select FSL_ELBC 806 imply CMD_NAND 807 imply CMD_SATA 808 809config ARCH_P4080 810 bool 811 select E500MC 812 select FSL_LAW 813 select SYS_FSL_DDR_VER_44 814 select SYS_FSL_ERRATUM_A004510 815 select SYS_FSL_ERRATUM_A004580 816 select SYS_FSL_ERRATUM_A004849 817 select SYS_FSL_ERRATUM_A005812 818 select SYS_FSL_ERRATUM_A007075 819 select SYS_FSL_ERRATUM_CPC_A002 820 select SYS_FSL_ERRATUM_CPC_A003 821 select SYS_FSL_ERRATUM_CPU_A003999 822 select SYS_FSL_ERRATUM_DDR_A003 823 select SYS_FSL_ERRATUM_DDR_A003474 824 select SYS_FSL_ERRATUM_ELBC_A001 825 select SYS_FSL_ERRATUM_ESDHC111 826 select SYS_FSL_ERRATUM_ESDHC13 827 select SYS_FSL_ERRATUM_ESDHC135 828 select SYS_FSL_ERRATUM_I2C_A004447 829 select SYS_FSL_ERRATUM_NMG_CPU_A011 830 select SYS_FSL_ERRATUM_SRIO_A004034 831 select SYS_P4080_ERRATUM_CPU22 832 select SYS_P4080_ERRATUM_PCIE_A003 833 select SYS_P4080_ERRATUM_SERDES8 834 select SYS_P4080_ERRATUM_SERDES9 835 select SYS_P4080_ERRATUM_SERDES_A001 836 select SYS_P4080_ERRATUM_SERDES_A005 837 select SYS_FSL_HAS_DDR3 838 select SYS_FSL_HAS_SEC 839 select SYS_FSL_QORIQ_CHASSIS1 840 select SYS_FSL_SEC_BE 841 select SYS_FSL_SEC_COMPAT_4 842 select FSL_ELBC 843 imply CMD_SATA 844 845config ARCH_P5020 846 bool 847 select E500MC 848 select FSL_LAW 849 select SYS_FSL_DDR_VER_44 850 select SYS_FSL_ERRATUM_A004510 851 select SYS_FSL_ERRATUM_A006261 852 select SYS_FSL_ERRATUM_DDR_A003 853 select SYS_FSL_ERRATUM_DDR_A003474 854 select SYS_FSL_ERRATUM_ESDHC111 855 select SYS_FSL_ERRATUM_I2C_A004447 856 select SYS_FSL_ERRATUM_SRIO_A004034 857 select SYS_FSL_ERRATUM_USB14 858 select SYS_FSL_HAS_DDR3 859 select SYS_FSL_HAS_SEC 860 select SYS_FSL_QORIQ_CHASSIS1 861 select SYS_FSL_SEC_BE 862 select SYS_FSL_SEC_COMPAT_4 863 select SYS_PPC64 864 select FSL_ELBC 865 imply CMD_SATA 866 867config ARCH_P5040 868 bool 869 select E500MC 870 select FSL_LAW 871 select SYS_FSL_DDR_VER_44 872 select SYS_FSL_ERRATUM_A004510 873 select SYS_FSL_ERRATUM_A004699 874 select SYS_FSL_ERRATUM_A005812 875 select SYS_FSL_ERRATUM_A006261 876 select SYS_FSL_ERRATUM_DDR_A003 877 select SYS_FSL_ERRATUM_DDR_A003474 878 select SYS_FSL_ERRATUM_ESDHC111 879 select SYS_FSL_ERRATUM_USB14 880 select SYS_FSL_HAS_DDR3 881 select SYS_FSL_HAS_SEC 882 select SYS_FSL_QORIQ_CHASSIS1 883 select SYS_FSL_SEC_BE 884 select SYS_FSL_SEC_COMPAT_4 885 select SYS_PPC64 886 select FSL_ELBC 887 imply CMD_SATA 888 889config ARCH_QEMU_E500 890 bool 891 892config ARCH_T1023 893 bool 894 select E500MC 895 select FSL_LAW 896 select SYS_FSL_DDR_VER_50 897 select SYS_FSL_ERRATUM_A008378 898 select SYS_FSL_ERRATUM_A009663 899 select SYS_FSL_ERRATUM_A009942 900 select SYS_FSL_ERRATUM_ESDHC111 901 select SYS_FSL_HAS_DDR3 902 select SYS_FSL_HAS_DDR4 903 select SYS_FSL_HAS_SEC 904 select SYS_FSL_QORIQ_CHASSIS2 905 select SYS_FSL_SEC_BE 906 select SYS_FSL_SEC_COMPAT_5 907 select FSL_IFC 908 imply CMD_EEPROM 909 imply CMD_NAND 910 911config ARCH_T1024 912 bool 913 select E500MC 914 select FSL_LAW 915 select SYS_FSL_DDR_VER_50 916 select SYS_FSL_ERRATUM_A008378 917 select SYS_FSL_ERRATUM_A009663 918 select SYS_FSL_ERRATUM_A009942 919 select SYS_FSL_ERRATUM_ESDHC111 920 select SYS_FSL_HAS_DDR3 921 select SYS_FSL_HAS_DDR4 922 select SYS_FSL_HAS_SEC 923 select SYS_FSL_QORIQ_CHASSIS2 924 select SYS_FSL_SEC_BE 925 select SYS_FSL_SEC_COMPAT_5 926 select FSL_IFC 927 imply CMD_EEPROM 928 imply CMD_NAND 929 imply CMD_MTDPARTS 930 931config ARCH_T1040 932 bool 933 select E500MC 934 select FSL_LAW 935 select SYS_FSL_DDR_VER_50 936 select SYS_FSL_ERRATUM_A008044 937 select SYS_FSL_ERRATUM_A008378 938 select SYS_FSL_ERRATUM_A009663 939 select SYS_FSL_ERRATUM_A009942 940 select SYS_FSL_ERRATUM_ESDHC111 941 select SYS_FSL_HAS_DDR3 942 select SYS_FSL_HAS_DDR4 943 select SYS_FSL_HAS_SEC 944 select SYS_FSL_QORIQ_CHASSIS2 945 select SYS_FSL_SEC_BE 946 select SYS_FSL_SEC_COMPAT_5 947 select FSL_IFC 948 imply CMD_MTDPARTS 949 imply CMD_NAND 950 imply CMD_SATA 951 952config ARCH_T1042 953 bool 954 select E500MC 955 select FSL_LAW 956 select SYS_FSL_DDR_VER_50 957 select SYS_FSL_ERRATUM_A008044 958 select SYS_FSL_ERRATUM_A008378 959 select SYS_FSL_ERRATUM_A009663 960 select SYS_FSL_ERRATUM_A009942 961 select SYS_FSL_ERRATUM_ESDHC111 962 select SYS_FSL_HAS_DDR3 963 select SYS_FSL_HAS_DDR4 964 select SYS_FSL_HAS_SEC 965 select SYS_FSL_QORIQ_CHASSIS2 966 select SYS_FSL_SEC_BE 967 select SYS_FSL_SEC_COMPAT_5 968 select FSL_IFC 969 imply CMD_MTDPARTS 970 imply CMD_NAND 971 imply CMD_SATA 972 973config ARCH_T2080 974 bool 975 select E500MC 976 select E6500 977 select FSL_LAW 978 select SYS_FSL_DDR_VER_47 979 select SYS_FSL_ERRATUM_A006379 980 select SYS_FSL_ERRATUM_A006593 981 select SYS_FSL_ERRATUM_A007186 982 select SYS_FSL_ERRATUM_A007212 983 select SYS_FSL_ERRATUM_A007815 984 select SYS_FSL_ERRATUM_A007907 985 select SYS_FSL_ERRATUM_A009942 986 select SYS_FSL_ERRATUM_ESDHC111 987 select SYS_FSL_HAS_DDR3 988 select SYS_FSL_HAS_SEC 989 select SYS_FSL_QORIQ_CHASSIS2 990 select SYS_FSL_SEC_BE 991 select SYS_FSL_SEC_COMPAT_4 992 select SYS_PPC64 993 select FSL_IFC 994 imply CMD_SATA 995 imply CMD_NAND 996 997config ARCH_T2081 998 bool 999 select E500MC 1000 select E6500 1001 select FSL_LAW 1002 select SYS_FSL_DDR_VER_47 1003 select SYS_FSL_ERRATUM_A006379 1004 select SYS_FSL_ERRATUM_A006593 1005 select SYS_FSL_ERRATUM_A007186 1006 select SYS_FSL_ERRATUM_A007212 1007 select SYS_FSL_ERRATUM_A009942 1008 select SYS_FSL_ERRATUM_ESDHC111 1009 select SYS_FSL_HAS_DDR3 1010 select SYS_FSL_HAS_SEC 1011 select SYS_FSL_QORIQ_CHASSIS2 1012 select SYS_FSL_SEC_BE 1013 select SYS_FSL_SEC_COMPAT_4 1014 select SYS_PPC64 1015 select FSL_IFC 1016 imply CMD_NAND 1017 1018config ARCH_T4160 1019 bool 1020 select E500MC 1021 select E6500 1022 select FSL_LAW 1023 select SYS_FSL_DDR_VER_47 1024 select SYS_FSL_ERRATUM_A004468 1025 select SYS_FSL_ERRATUM_A005871 1026 select SYS_FSL_ERRATUM_A006379 1027 select SYS_FSL_ERRATUM_A006593 1028 select SYS_FSL_ERRATUM_A007186 1029 select SYS_FSL_ERRATUM_A007798 1030 select SYS_FSL_ERRATUM_A009942 1031 select SYS_FSL_HAS_DDR3 1032 select SYS_FSL_HAS_SEC 1033 select SYS_FSL_QORIQ_CHASSIS2 1034 select SYS_FSL_SEC_BE 1035 select SYS_FSL_SEC_COMPAT_4 1036 select SYS_PPC64 1037 select FSL_IFC 1038 imply CMD_SATA 1039 imply CMD_NAND 1040 1041config ARCH_T4240 1042 bool 1043 select E500MC 1044 select E6500 1045 select FSL_LAW 1046 select SYS_FSL_DDR_VER_47 1047 select SYS_FSL_ERRATUM_A004468 1048 select SYS_FSL_ERRATUM_A005871 1049 select SYS_FSL_ERRATUM_A006261 1050 select SYS_FSL_ERRATUM_A006379 1051 select SYS_FSL_ERRATUM_A006593 1052 select SYS_FSL_ERRATUM_A007186 1053 select SYS_FSL_ERRATUM_A007798 1054 select SYS_FSL_ERRATUM_A007815 1055 select SYS_FSL_ERRATUM_A007907 1056 select SYS_FSL_ERRATUM_A009942 1057 select SYS_FSL_HAS_DDR3 1058 select SYS_FSL_HAS_SEC 1059 select SYS_FSL_QORIQ_CHASSIS2 1060 select SYS_FSL_SEC_BE 1061 select SYS_FSL_SEC_COMPAT_4 1062 select SYS_PPC64 1063 select FSL_IFC 1064 imply CMD_SATA 1065 imply CMD_NAND 1066 1067config BOOKE 1068 bool 1069 default y 1070 1071config E500 1072 bool 1073 default y 1074 help 1075 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 1076 1077config E500MC 1078 bool 1079 help 1080 Enble PowerPC E500MC core 1081 1082config E6500 1083 bool 1084 help 1085 Enable PowerPC E6500 core 1086 1087config FSL_LAW 1088 bool 1089 help 1090 Use Freescale common code for Local Access Window 1091 1092config SECURE_BOOT 1093 bool "Secure Boot" 1094 help 1095 Enable Freescale Secure Boot feature. Normally selected 1096 by defconfig. If unsure, do not change. 1097 1098config MAX_CPUS 1099 int "Maximum number of CPUs permitted for MPC85xx" 1100 default 12 if ARCH_T4240 1101 default 8 if ARCH_P4080 || \ 1102 ARCH_T4160 1103 default 4 if ARCH_B4860 || \ 1104 ARCH_P2041 || \ 1105 ARCH_P3041 || \ 1106 ARCH_P5040 || \ 1107 ARCH_T1040 || \ 1108 ARCH_T1042 || \ 1109 ARCH_T2080 || \ 1110 ARCH_T2081 1111 default 2 if ARCH_B4420 || \ 1112 ARCH_BSC9132 || \ 1113 ARCH_MPC8572 || \ 1114 ARCH_P1020 || \ 1115 ARCH_P1021 || \ 1116 ARCH_P1022 || \ 1117 ARCH_P1023 || \ 1118 ARCH_P1024 || \ 1119 ARCH_P1025 || \ 1120 ARCH_P2020 || \ 1121 ARCH_P5020 || \ 1122 ARCH_T1023 || \ 1123 ARCH_T1024 1124 default 1 1125 help 1126 Set this number to the maximum number of possible CPUs in the SoC. 1127 SoCs may have multiple clusters with each cluster may have multiple 1128 ports. If some ports are reserved but higher ports are used for 1129 cores, count the reserved ports. This will allocate enough memory 1130 in spin table to properly handle all cores. 1131 1132config SYS_CCSRBAR_DEFAULT 1133 hex "Default CCSRBAR address" 1134 default 0xff700000 if ARCH_BSC9131 || \ 1135 ARCH_BSC9132 || \ 1136 ARCH_C29X || \ 1137 ARCH_MPC8536 || \ 1138 ARCH_MPC8540 || \ 1139 ARCH_MPC8541 || \ 1140 ARCH_MPC8544 || \ 1141 ARCH_MPC8548 || \ 1142 ARCH_MPC8555 || \ 1143 ARCH_MPC8560 || \ 1144 ARCH_MPC8568 || \ 1145 ARCH_MPC8569 || \ 1146 ARCH_MPC8572 || \ 1147 ARCH_P1010 || \ 1148 ARCH_P1011 || \ 1149 ARCH_P1020 || \ 1150 ARCH_P1021 || \ 1151 ARCH_P1022 || \ 1152 ARCH_P1024 || \ 1153 ARCH_P1025 || \ 1154 ARCH_P2020 1155 default 0xff600000 if ARCH_P1023 1156 default 0xfe000000 if ARCH_B4420 || \ 1157 ARCH_B4860 || \ 1158 ARCH_P2041 || \ 1159 ARCH_P3041 || \ 1160 ARCH_P4080 || \ 1161 ARCH_P5020 || \ 1162 ARCH_P5040 || \ 1163 ARCH_T1023 || \ 1164 ARCH_T1024 || \ 1165 ARCH_T1040 || \ 1166 ARCH_T1042 || \ 1167 ARCH_T2080 || \ 1168 ARCH_T2081 || \ 1169 ARCH_T4160 || \ 1170 ARCH_T4240 1171 default 0xe0000000 if ARCH_QEMU_E500 1172 help 1173 Default value of CCSRBAR comes from power-on-reset. It 1174 is fixed on each SoC. Some SoCs can have different value 1175 if changed by pre-boot regime. The value here must match 1176 the current value in SoC. If not sure, do not change. 1177 1178config SYS_FSL_ERRATUM_A004468 1179 bool 1180 1181config SYS_FSL_ERRATUM_A004477 1182 bool 1183 1184config SYS_FSL_ERRATUM_A004508 1185 bool 1186 1187config SYS_FSL_ERRATUM_A004580 1188 bool 1189 1190config SYS_FSL_ERRATUM_A004699 1191 bool 1192 1193config SYS_FSL_ERRATUM_A004849 1194 bool 1195 1196config SYS_FSL_ERRATUM_A004510 1197 bool 1198 1199config SYS_FSL_ERRATUM_A004510_SVR_REV 1200 hex 1201 depends on SYS_FSL_ERRATUM_A004510 1202 default 0x20 if ARCH_P4080 1203 default 0x10 1204 1205config SYS_FSL_ERRATUM_A004510_SVR_REV2 1206 hex 1207 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1208 default 0x11 1209 1210config SYS_FSL_ERRATUM_A005125 1211 bool 1212 1213config SYS_FSL_ERRATUM_A005434 1214 bool 1215 1216config SYS_FSL_ERRATUM_A005812 1217 bool 1218 1219config SYS_FSL_ERRATUM_A005871 1220 bool 1221 1222config SYS_FSL_ERRATUM_A006261 1223 bool 1224 1225config SYS_FSL_ERRATUM_A006379 1226 bool 1227 1228config SYS_FSL_ERRATUM_A006384 1229 bool 1230 1231config SYS_FSL_ERRATUM_A006475 1232 bool 1233 1234config SYS_FSL_ERRATUM_A006593 1235 bool 1236 1237config SYS_FSL_ERRATUM_A007075 1238 bool 1239 1240config SYS_FSL_ERRATUM_A007186 1241 bool 1242 1243config SYS_FSL_ERRATUM_A007212 1244 bool 1245 1246config SYS_FSL_ERRATUM_A007815 1247 bool 1248 1249config SYS_FSL_ERRATUM_A007798 1250 bool 1251 1252config SYS_FSL_ERRATUM_A007907 1253 bool 1254 1255config SYS_FSL_ERRATUM_A008044 1256 bool 1257 1258config SYS_FSL_ERRATUM_CPC_A002 1259 bool 1260 1261config SYS_FSL_ERRATUM_CPC_A003 1262 bool 1263 1264config SYS_FSL_ERRATUM_CPU_A003999 1265 bool 1266 1267config SYS_FSL_ERRATUM_ELBC_A001 1268 bool 1269 1270config SYS_FSL_ERRATUM_I2C_A004447 1271 bool 1272 1273config SYS_FSL_A004447_SVR_REV 1274 hex 1275 depends on SYS_FSL_ERRATUM_I2C_A004447 1276 default 0x00 if ARCH_MPC8548 1277 default 0x10 if ARCH_P1010 1278 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1279 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1280 1281config SYS_FSL_ERRATUM_IFC_A002769 1282 bool 1283 1284config SYS_FSL_ERRATUM_IFC_A003399 1285 bool 1286 1287config SYS_FSL_ERRATUM_NMG_CPU_A011 1288 bool 1289 1290config SYS_FSL_ERRATUM_NMG_ETSEC129 1291 bool 1292 1293config SYS_FSL_ERRATUM_NMG_LBC103 1294 bool 1295 1296config SYS_FSL_ERRATUM_P1010_A003549 1297 bool 1298 1299config SYS_FSL_ERRATUM_SATA_A001 1300 bool 1301 1302config SYS_FSL_ERRATUM_SEC_A003571 1303 bool 1304 1305config SYS_FSL_ERRATUM_SRIO_A004034 1306 bool 1307 1308config SYS_FSL_ERRATUM_USB14 1309 bool 1310 1311config SYS_P4080_ERRATUM_CPU22 1312 bool 1313 1314config SYS_P4080_ERRATUM_PCIE_A003 1315 bool 1316 1317config SYS_P4080_ERRATUM_SERDES8 1318 bool 1319 1320config SYS_P4080_ERRATUM_SERDES9 1321 bool 1322 1323config SYS_P4080_ERRATUM_SERDES_A001 1324 bool 1325 1326config SYS_P4080_ERRATUM_SERDES_A005 1327 bool 1328 1329config SYS_FSL_QORIQ_CHASSIS1 1330 bool 1331 1332config SYS_FSL_QORIQ_CHASSIS2 1333 bool 1334 1335config SYS_FSL_NUM_LAWS 1336 int "Number of local access windows" 1337 depends on FSL_LAW 1338 default 32 if ARCH_B4420 || \ 1339 ARCH_B4860 || \ 1340 ARCH_P2041 || \ 1341 ARCH_P3041 || \ 1342 ARCH_P4080 || \ 1343 ARCH_P5020 || \ 1344 ARCH_P5040 || \ 1345 ARCH_T2080 || \ 1346 ARCH_T2081 || \ 1347 ARCH_T4160 || \ 1348 ARCH_T4240 1349 default 16 if ARCH_T1023 || \ 1350 ARCH_T1024 || \ 1351 ARCH_T1040 || \ 1352 ARCH_T1042 1353 default 12 if ARCH_BSC9131 || \ 1354 ARCH_BSC9132 || \ 1355 ARCH_C29X || \ 1356 ARCH_MPC8536 || \ 1357 ARCH_MPC8572 || \ 1358 ARCH_P1010 || \ 1359 ARCH_P1011 || \ 1360 ARCH_P1020 || \ 1361 ARCH_P1021 || \ 1362 ARCH_P1022 || \ 1363 ARCH_P1023 || \ 1364 ARCH_P1024 || \ 1365 ARCH_P1025 || \ 1366 ARCH_P2020 1367 default 10 if ARCH_MPC8544 || \ 1368 ARCH_MPC8548 || \ 1369 ARCH_MPC8568 || \ 1370 ARCH_MPC8569 1371 default 8 if ARCH_MPC8540 || \ 1372 ARCH_MPC8541 || \ 1373 ARCH_MPC8555 || \ 1374 ARCH_MPC8560 1375 help 1376 Number of local access windows. This is fixed per SoC. 1377 If not sure, do not change. 1378 1379config SYS_FSL_THREADS_PER_CORE 1380 int 1381 default 2 if E6500 1382 default 1 1383 1384config SYS_NUM_TLBCAMS 1385 int "Number of TLB CAM entries" 1386 default 64 if E500MC 1387 default 16 1388 help 1389 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1390 16 for other E500 SoCs. 1391 1392config SYS_PPC64 1393 bool 1394 1395config SYS_PPC_E500_USE_DEBUG_TLB 1396 bool 1397 1398config FSL_IFC 1399 bool 1400 1401config FSL_ELBC 1402 bool 1403 1404config SYS_PPC_E500_DEBUG_TLB 1405 int "Temporary TLB entry for external debugger" 1406 depends on SYS_PPC_E500_USE_DEBUG_TLB 1407 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1408 default 1 if ARCH_MPC8536 1409 default 2 if ARCH_MPC8572 || \ 1410 ARCH_P1011 || \ 1411 ARCH_P1020 || \ 1412 ARCH_P1021 || \ 1413 ARCH_P1022 || \ 1414 ARCH_P1024 || \ 1415 ARCH_P1025 || \ 1416 ARCH_P2020 1417 default 3 if ARCH_P1010 || \ 1418 ARCH_BSC9132 || \ 1419 ARCH_C29X 1420 help 1421 Select a temporary TLB entry to be used during boot to work 1422 around limitations in e500v1 and e500v2 external debugger 1423 support. This reduces the portions of the boot code where 1424 breakpoints and single stepping do not work. The value of this 1425 symbol should be set to the TLB1 entry to be used for this 1426 purpose. If unsure, do not change. 1427 1428config SYS_FSL_IFC_CLK_DIV 1429 int "Divider of platform clock" 1430 depends on FSL_IFC 1431 default 2 if ARCH_B4420 || \ 1432 ARCH_B4860 || \ 1433 ARCH_T1024 || \ 1434 ARCH_T1023 || \ 1435 ARCH_T1040 || \ 1436 ARCH_T1042 || \ 1437 ARCH_T4160 || \ 1438 ARCH_T4240 1439 default 1 1440 help 1441 Defines divider of platform clock(clock input to 1442 IFC controller). 1443 1444config SYS_FSL_LBC_CLK_DIV 1445 int "Divider of platform clock" 1446 depends on FSL_ELBC || ARCH_MPC8540 || \ 1447 ARCH_MPC8548 || ARCH_MPC8541 || \ 1448 ARCH_MPC8555 || ARCH_MPC8560 || \ 1449 ARCH_MPC8568 1450 1451 default 2 if ARCH_P2041 || \ 1452 ARCH_P3041 || \ 1453 ARCH_P4080 || \ 1454 ARCH_P5020 || \ 1455 ARCH_P5040 1456 default 1 1457 1458 help 1459 Defines divider of platform clock(clock input to 1460 eLBC controller). 1461 1462source "board/freescale/b4860qds/Kconfig" 1463source "board/freescale/bsc9131rdb/Kconfig" 1464source "board/freescale/bsc9132qds/Kconfig" 1465source "board/freescale/c29xpcie/Kconfig" 1466source "board/freescale/corenet_ds/Kconfig" 1467source "board/freescale/mpc8536ds/Kconfig" 1468source "board/freescale/mpc8541cds/Kconfig" 1469source "board/freescale/mpc8544ds/Kconfig" 1470source "board/freescale/mpc8548cds/Kconfig" 1471source "board/freescale/mpc8555cds/Kconfig" 1472source "board/freescale/mpc8568mds/Kconfig" 1473source "board/freescale/mpc8569mds/Kconfig" 1474source "board/freescale/mpc8572ds/Kconfig" 1475source "board/freescale/p1010rdb/Kconfig" 1476source "board/freescale/p1022ds/Kconfig" 1477source "board/freescale/p1023rdb/Kconfig" 1478source "board/freescale/p1_p2_rdb_pc/Kconfig" 1479source "board/freescale/p1_twr/Kconfig" 1480source "board/freescale/p2041rdb/Kconfig" 1481source "board/freescale/qemu-ppce500/Kconfig" 1482source "board/freescale/t102xqds/Kconfig" 1483source "board/freescale/t102xrdb/Kconfig" 1484source "board/freescale/t1040qds/Kconfig" 1485source "board/freescale/t104xrdb/Kconfig" 1486source "board/freescale/t208xqds/Kconfig" 1487source "board/freescale/t208xrdb/Kconfig" 1488source "board/freescale/t4qds/Kconfig" 1489source "board/freescale/t4rdb/Kconfig" 1490source "board/gdsys/p1022/Kconfig" 1491source "board/keymile/kmp204x/Kconfig" 1492source "board/sbc8548/Kconfig" 1493source "board/socrates/Kconfig" 1494source "board/varisys/cyrus/Kconfig" 1495source "board/xes/xpedite520x/Kconfig" 1496source "board/xes/xpedite537x/Kconfig" 1497source "board/xes/xpedite550x/Kconfig" 1498source "board/Arcturus/ucp1020/Kconfig" 1499 1500endmenu 1501