1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_SBC8548 12 bool "Support sbc8548" 13 select ARCH_MPC8548 14 15config TARGET_SOCRATES 16 bool "Support socrates" 17 select ARCH_MPC8544 18 19config TARGET_B4420QDS 20 bool "Support B4420QDS" 21 select ARCH_B4420 22 select SUPPORT_SPL 23 select PHYS_64BIT 24 25config TARGET_B4860QDS 26 bool "Support B4860QDS" 27 select ARCH_B4860 28 select SUPPORT_SPL 29 select PHYS_64BIT 30 31config TARGET_BSC9131RDB 32 bool "Support BSC9131RDB" 33 select ARCH_BSC9131 34 select SUPPORT_SPL 35 36config TARGET_BSC9132QDS 37 bool "Support BSC9132QDS" 38 select ARCH_BSC9132 39 select SUPPORT_SPL 40 41config TARGET_C29XPCIE 42 bool "Support C29XPCIE" 43 select ARCH_C29X 44 select SUPPORT_SPL 45 select SUPPORT_TPL 46 select PHYS_64BIT 47 48config TARGET_P3041DS 49 bool "Support P3041DS" 50 select PHYS_64BIT 51 select ARCH_P3041 52 53config TARGET_P4080DS 54 bool "Support P4080DS" 55 select PHYS_64BIT 56 select ARCH_P4080 57 58config TARGET_P5020DS 59 bool "Support P5020DS" 60 select PHYS_64BIT 61 select ARCH_P5020 62 63config TARGET_P5040DS 64 bool "Support P5040DS" 65 select PHYS_64BIT 66 select ARCH_P5040 67 68config TARGET_MPC8536DS 69 bool "Support MPC8536DS" 70 select ARCH_MPC8536 71# Use DDR3 controller with DDR2 DIMMs on this board 72 select SYS_FSL_DDRC_GEN3 73 74config TARGET_MPC8540ADS 75 bool "Support MPC8540ADS" 76 select ARCH_MPC8540 77 78config TARGET_MPC8541CDS 79 bool "Support MPC8541CDS" 80 select ARCH_MPC8541 81 82config TARGET_MPC8544DS 83 bool "Support MPC8544DS" 84 select ARCH_MPC8544 85 86config TARGET_MPC8548CDS 87 bool "Support MPC8548CDS" 88 select ARCH_MPC8548 89 90config TARGET_MPC8555CDS 91 bool "Support MPC8555CDS" 92 select ARCH_MPC8555 93 94config TARGET_MPC8560ADS 95 bool "Support MPC8560ADS" 96 select ARCH_MPC8560 97 98config TARGET_MPC8568MDS 99 bool "Support MPC8568MDS" 100 select ARCH_MPC8568 101 102config TARGET_MPC8569MDS 103 bool "Support MPC8569MDS" 104 select ARCH_MPC8569 105 106config TARGET_MPC8572DS 107 bool "Support MPC8572DS" 108 select ARCH_MPC8572 109# Use DDR3 controller with DDR2 DIMMs on this board 110 select SYS_FSL_DDRC_GEN3 111 112config TARGET_P1010RDB_PA 113 bool "Support P1010RDB_PA" 114 select ARCH_P1010 115 select SUPPORT_SPL 116 select SUPPORT_TPL 117 118config TARGET_P1010RDB_PB 119 bool "Support P1010RDB_PB" 120 select ARCH_P1010 121 select SUPPORT_SPL 122 select SUPPORT_TPL 123 124config TARGET_P1022DS 125 bool "Support P1022DS" 126 select ARCH_P1022 127 select SUPPORT_SPL 128 select SUPPORT_TPL 129 130config TARGET_P1023RDB 131 bool "Support P1023RDB" 132 select ARCH_P1023 133 134config TARGET_P1020MBG 135 bool "Support P1020MBG-PC" 136 select SUPPORT_SPL 137 select SUPPORT_TPL 138 select ARCH_P1020 139 140config TARGET_P1020RDB_PC 141 bool "Support P1020RDB-PC" 142 select SUPPORT_SPL 143 select SUPPORT_TPL 144 select ARCH_P1020 145 146config TARGET_P1020RDB_PD 147 bool "Support P1020RDB-PD" 148 select SUPPORT_SPL 149 select SUPPORT_TPL 150 select ARCH_P1020 151 152config TARGET_P1020UTM 153 bool "Support P1020UTM" 154 select SUPPORT_SPL 155 select SUPPORT_TPL 156 select ARCH_P1020 157 158config TARGET_P1021RDB 159 bool "Support P1021RDB" 160 select SUPPORT_SPL 161 select SUPPORT_TPL 162 select ARCH_P1021 163 164config TARGET_P1024RDB 165 bool "Support P1024RDB" 166 select SUPPORT_SPL 167 select SUPPORT_TPL 168 select ARCH_P1024 169 170config TARGET_P1025RDB 171 bool "Support P1025RDB" 172 select SUPPORT_SPL 173 select SUPPORT_TPL 174 select ARCH_P1025 175 176config TARGET_P2020RDB 177 bool "Support P2020RDB-PC" 178 select SUPPORT_SPL 179 select SUPPORT_TPL 180 select ARCH_P2020 181 182config TARGET_P1_TWR 183 bool "Support p1_twr" 184 select ARCH_P1025 185 186config TARGET_P2041RDB 187 bool "Support P2041RDB" 188 select ARCH_P2041 189 select PHYS_64BIT 190 191config TARGET_QEMU_PPCE500 192 bool "Support qemu-ppce500" 193 select ARCH_QEMU_E500 194 select PHYS_64BIT 195 196config TARGET_T1024QDS 197 bool "Support T1024QDS" 198 select ARCH_T1024 199 select SUPPORT_SPL 200 select PHYS_64BIT 201 202config TARGET_T1023RDB 203 bool "Support T1023RDB" 204 select ARCH_T1023 205 select SUPPORT_SPL 206 select PHYS_64BIT 207 208config TARGET_T1024RDB 209 bool "Support T1024RDB" 210 select ARCH_T1024 211 select SUPPORT_SPL 212 select PHYS_64BIT 213 214config TARGET_T1040QDS 215 bool "Support T1040QDS" 216 select ARCH_T1040 217 select PHYS_64BIT 218 219config TARGET_T1040RDB 220 bool "Support T1040RDB" 221 select ARCH_T1040 222 select SUPPORT_SPL 223 select PHYS_64BIT 224 225config TARGET_T1040D4RDB 226 bool "Support T1040D4RDB" 227 select ARCH_T1040 228 select SUPPORT_SPL 229 select PHYS_64BIT 230 231config TARGET_T1042RDB 232 bool "Support T1042RDB" 233 select ARCH_T1042 234 select SUPPORT_SPL 235 select PHYS_64BIT 236 237config TARGET_T1042D4RDB 238 bool "Support T1042D4RDB" 239 select ARCH_T1042 240 select SUPPORT_SPL 241 select PHYS_64BIT 242 243config TARGET_T1042RDB_PI 244 bool "Support T1042RDB_PI" 245 select ARCH_T1042 246 select SUPPORT_SPL 247 select PHYS_64BIT 248 249config TARGET_T2080QDS 250 bool "Support T2080QDS" 251 select ARCH_T2080 252 select SUPPORT_SPL 253 select PHYS_64BIT 254 255config TARGET_T2080RDB 256 bool "Support T2080RDB" 257 select ARCH_T2080 258 select SUPPORT_SPL 259 select PHYS_64BIT 260 261config TARGET_T2081QDS 262 bool "Support T2081QDS" 263 select ARCH_T2081 264 select SUPPORT_SPL 265 select PHYS_64BIT 266 267config TARGET_T4160QDS 268 bool "Support T4160QDS" 269 select ARCH_T4160 270 select SUPPORT_SPL 271 select PHYS_64BIT 272 273config TARGET_T4160RDB 274 bool "Support T4160RDB" 275 select ARCH_T4160 276 select SUPPORT_SPL 277 select PHYS_64BIT 278 279config TARGET_T4240QDS 280 bool "Support T4240QDS" 281 select ARCH_T4240 282 select SUPPORT_SPL 283 select PHYS_64BIT 284 285config TARGET_T4240RDB 286 bool "Support T4240RDB" 287 select ARCH_T4240 288 select SUPPORT_SPL 289 select PHYS_64BIT 290 291config TARGET_CONTROLCENTERD 292 bool "Support controlcenterd" 293 select ARCH_P1022 294 295config TARGET_KMP204X 296 bool "Support kmp204x" 297 select ARCH_P2041 298 select PHYS_64BIT 299 300config TARGET_XPEDITE520X 301 bool "Support xpedite520x" 302 select ARCH_MPC8548 303 304config TARGET_XPEDITE537X 305 bool "Support xpedite537x" 306 select ARCH_MPC8572 307# Use DDR3 controller with DDR2 DIMMs on this board 308 select SYS_FSL_DDRC_GEN3 309 310config TARGET_XPEDITE550X 311 bool "Support xpedite550x" 312 select ARCH_P2020 313 314config TARGET_UCP1020 315 bool "Support uCP1020" 316 select ARCH_P1020 317 318config TARGET_CYRUS_P5020 319 bool "Support Varisys Cyrus P5020" 320 select ARCH_P5020 321 select PHYS_64BIT 322 323config TARGET_CYRUS_P5040 324 bool "Support Varisys Cyrus P5040" 325 select ARCH_P5040 326 select PHYS_64BIT 327 328endchoice 329 330config ARCH_B4420 331 bool 332 select E500MC 333 select E6500 334 select FSL_LAW 335 select SYS_FSL_DDR_VER_47 336 select SYS_FSL_ERRATUM_A004477 337 select SYS_FSL_ERRATUM_A005871 338 select SYS_FSL_ERRATUM_A006379 339 select SYS_FSL_ERRATUM_A006384 340 select SYS_FSL_ERRATUM_A006475 341 select SYS_FSL_ERRATUM_A006593 342 select SYS_FSL_ERRATUM_A007075 343 select SYS_FSL_ERRATUM_A007186 344 select SYS_FSL_ERRATUM_A007212 345 select SYS_FSL_ERRATUM_A009942 346 select SYS_FSL_HAS_DDR3 347 select SYS_FSL_HAS_SEC 348 select SYS_FSL_SEC_BE 349 select SYS_FSL_SEC_COMPAT_4 350 351config ARCH_B4860 352 bool 353 select E500MC 354 select E6500 355 select FSL_LAW 356 select SYS_FSL_DDR_VER_47 357 select SYS_FSL_ERRATUM_A004477 358 select SYS_FSL_ERRATUM_A005871 359 select SYS_FSL_ERRATUM_A006379 360 select SYS_FSL_ERRATUM_A006384 361 select SYS_FSL_ERRATUM_A006475 362 select SYS_FSL_ERRATUM_A006593 363 select SYS_FSL_ERRATUM_A007075 364 select SYS_FSL_ERRATUM_A007186 365 select SYS_FSL_ERRATUM_A007212 366 select SYS_FSL_ERRATUM_A009942 367 select SYS_FSL_HAS_DDR3 368 select SYS_FSL_HAS_SEC 369 select SYS_FSL_SEC_BE 370 select SYS_FSL_SEC_COMPAT_4 371 372config ARCH_BSC9131 373 bool 374 select FSL_LAW 375 select SYS_FSL_DDR_VER_44 376 select SYS_FSL_ERRATUM_A004477 377 select SYS_FSL_ERRATUM_A005125 378 select SYS_FSL_ERRATUM_ESDHC111 379 select SYS_FSL_HAS_DDR3 380 select SYS_FSL_HAS_SEC 381 select SYS_FSL_SEC_BE 382 select SYS_FSL_SEC_COMPAT_4 383 384config ARCH_BSC9132 385 bool 386 select FSL_LAW 387 select SYS_FSL_DDR_VER_46 388 select SYS_FSL_ERRATUM_A004477 389 select SYS_FSL_ERRATUM_A005125 390 select SYS_FSL_ERRATUM_A005434 391 select SYS_FSL_ERRATUM_ESDHC111 392 select SYS_FSL_ERRATUM_I2C_A004447 393 select SYS_FSL_ERRATUM_IFC_A002769 394 select SYS_FSL_HAS_DDR3 395 select SYS_FSL_HAS_SEC 396 select SYS_FSL_SEC_BE 397 select SYS_FSL_SEC_COMPAT_4 398 select SYS_PPC_E500_USE_DEBUG_TLB 399 400config ARCH_C29X 401 bool 402 select FSL_LAW 403 select SYS_FSL_DDR_VER_46 404 select SYS_FSL_ERRATUM_A005125 405 select SYS_FSL_ERRATUM_ESDHC111 406 select SYS_FSL_HAS_DDR3 407 select SYS_FSL_HAS_SEC 408 select SYS_FSL_SEC_BE 409 select SYS_FSL_SEC_COMPAT_6 410 select SYS_PPC_E500_USE_DEBUG_TLB 411 412config ARCH_MPC8536 413 bool 414 select FSL_LAW 415 select SYS_FSL_ERRATUM_A004508 416 select SYS_FSL_ERRATUM_A005125 417 select SYS_FSL_HAS_DDR2 418 select SYS_FSL_HAS_DDR3 419 select SYS_FSL_HAS_SEC 420 select SYS_FSL_SEC_BE 421 select SYS_FSL_SEC_COMPAT_2 422 select SYS_PPC_E500_USE_DEBUG_TLB 423 424config ARCH_MPC8540 425 bool 426 select FSL_LAW 427 select SYS_FSL_HAS_DDR1 428 429config ARCH_MPC8541 430 bool 431 select FSL_LAW 432 select SYS_FSL_HAS_DDR1 433 select SYS_FSL_HAS_SEC 434 select SYS_FSL_SEC_BE 435 select SYS_FSL_SEC_COMPAT_2 436 437config ARCH_MPC8544 438 bool 439 select FSL_LAW 440 select SYS_FSL_ERRATUM_A005125 441 select SYS_FSL_HAS_DDR2 442 select SYS_FSL_HAS_SEC 443 select SYS_FSL_SEC_BE 444 select SYS_FSL_SEC_COMPAT_2 445 select SYS_PPC_E500_USE_DEBUG_TLB 446 447config ARCH_MPC8548 448 bool 449 select FSL_LAW 450 select SYS_FSL_ERRATUM_A005125 451 select SYS_FSL_ERRATUM_NMG_DDR120 452 select SYS_FSL_ERRATUM_NMG_LBC103 453 select SYS_FSL_ERRATUM_NMG_ETSEC129 454 select SYS_FSL_ERRATUM_I2C_A004447 455 select SYS_FSL_HAS_DDR2 456 select SYS_FSL_HAS_DDR1 457 select SYS_FSL_HAS_SEC 458 select SYS_FSL_SEC_BE 459 select SYS_FSL_SEC_COMPAT_2 460 select SYS_PPC_E500_USE_DEBUG_TLB 461 462config ARCH_MPC8555 463 bool 464 select FSL_LAW 465 select SYS_FSL_HAS_DDR1 466 select SYS_FSL_HAS_SEC 467 select SYS_FSL_SEC_BE 468 select SYS_FSL_SEC_COMPAT_2 469 470config ARCH_MPC8560 471 bool 472 select FSL_LAW 473 select SYS_FSL_HAS_DDR1 474 475config ARCH_MPC8568 476 bool 477 select FSL_LAW 478 select SYS_FSL_HAS_DDR2 479 select SYS_FSL_HAS_SEC 480 select SYS_FSL_SEC_BE 481 select SYS_FSL_SEC_COMPAT_2 482 483config ARCH_MPC8569 484 bool 485 select FSL_LAW 486 select SYS_FSL_ERRATUM_A004508 487 select SYS_FSL_ERRATUM_A005125 488 select SYS_FSL_HAS_DDR3 489 select SYS_FSL_HAS_SEC 490 select SYS_FSL_SEC_BE 491 select SYS_FSL_SEC_COMPAT_2 492 493config ARCH_MPC8572 494 bool 495 select FSL_LAW 496 select SYS_FSL_ERRATUM_A004508 497 select SYS_FSL_ERRATUM_A005125 498 select SYS_FSL_ERRATUM_DDR_115 499 select SYS_FSL_ERRATUM_DDR111_DDR134 500 select SYS_FSL_HAS_DDR2 501 select SYS_FSL_HAS_DDR3 502 select SYS_FSL_HAS_SEC 503 select SYS_FSL_SEC_BE 504 select SYS_FSL_SEC_COMPAT_2 505 select SYS_PPC_E500_USE_DEBUG_TLB 506 507config ARCH_P1010 508 bool 509 select FSL_LAW 510 select SYS_FSL_ERRATUM_A004477 511 select SYS_FSL_ERRATUM_A004508 512 select SYS_FSL_ERRATUM_A005125 513 select SYS_FSL_ERRATUM_A006261 514 select SYS_FSL_ERRATUM_A007075 515 select SYS_FSL_ERRATUM_ESDHC111 516 select SYS_FSL_ERRATUM_I2C_A004447 517 select SYS_FSL_ERRATUM_IFC_A002769 518 select SYS_FSL_ERRATUM_P1010_A003549 519 select SYS_FSL_ERRATUM_SEC_A003571 520 select SYS_FSL_ERRATUM_IFC_A003399 521 select SYS_FSL_HAS_DDR3 522 select SYS_FSL_HAS_SEC 523 select SYS_FSL_SEC_BE 524 select SYS_FSL_SEC_COMPAT_4 525 select SYS_PPC_E500_USE_DEBUG_TLB 526 527config ARCH_P1011 528 bool 529 select FSL_LAW 530 select SYS_FSL_ERRATUM_A004508 531 select SYS_FSL_ERRATUM_A005125 532 select SYS_FSL_ERRATUM_ELBC_A001 533 select SYS_FSL_ERRATUM_ESDHC111 534 select SYS_FSL_HAS_DDR3 535 select SYS_FSL_HAS_SEC 536 select SYS_FSL_SEC_BE 537 select SYS_FSL_SEC_COMPAT_2 538 select SYS_PPC_E500_USE_DEBUG_TLB 539 540config ARCH_P1020 541 bool 542 select FSL_LAW 543 select SYS_FSL_ERRATUM_A004508 544 select SYS_FSL_ERRATUM_A005125 545 select SYS_FSL_ERRATUM_ELBC_A001 546 select SYS_FSL_ERRATUM_ESDHC111 547 select SYS_FSL_HAS_DDR3 548 select SYS_FSL_HAS_SEC 549 select SYS_FSL_SEC_BE 550 select SYS_FSL_SEC_COMPAT_2 551 select SYS_PPC_E500_USE_DEBUG_TLB 552 553config ARCH_P1021 554 bool 555 select FSL_LAW 556 select SYS_FSL_ERRATUM_A004508 557 select SYS_FSL_ERRATUM_A005125 558 select SYS_FSL_ERRATUM_ELBC_A001 559 select SYS_FSL_ERRATUM_ESDHC111 560 select SYS_FSL_HAS_DDR3 561 select SYS_FSL_HAS_SEC 562 select SYS_FSL_SEC_BE 563 select SYS_FSL_SEC_COMPAT_2 564 select SYS_PPC_E500_USE_DEBUG_TLB 565 566config ARCH_P1022 567 bool 568 select FSL_LAW 569 select SYS_FSL_ERRATUM_A004477 570 select SYS_FSL_ERRATUM_A004508 571 select SYS_FSL_ERRATUM_A005125 572 select SYS_FSL_ERRATUM_ELBC_A001 573 select SYS_FSL_ERRATUM_ESDHC111 574 select SYS_FSL_ERRATUM_SATA_A001 575 select SYS_FSL_HAS_DDR3 576 select SYS_FSL_HAS_SEC 577 select SYS_FSL_SEC_BE 578 select SYS_FSL_SEC_COMPAT_2 579 select SYS_PPC_E500_USE_DEBUG_TLB 580 581config ARCH_P1023 582 bool 583 select FSL_LAW 584 select SYS_FSL_ERRATUM_A004508 585 select SYS_FSL_ERRATUM_A005125 586 select SYS_FSL_ERRATUM_I2C_A004447 587 select SYS_FSL_HAS_DDR3 588 select SYS_FSL_HAS_SEC 589 select SYS_FSL_SEC_BE 590 select SYS_FSL_SEC_COMPAT_4 591 592config ARCH_P1024 593 bool 594 select FSL_LAW 595 select SYS_FSL_ERRATUM_A004508 596 select SYS_FSL_ERRATUM_A005125 597 select SYS_FSL_ERRATUM_ELBC_A001 598 select SYS_FSL_ERRATUM_ESDHC111 599 select SYS_FSL_HAS_DDR3 600 select SYS_FSL_HAS_SEC 601 select SYS_FSL_SEC_BE 602 select SYS_FSL_SEC_COMPAT_2 603 select SYS_PPC_E500_USE_DEBUG_TLB 604 605config ARCH_P1025 606 bool 607 select FSL_LAW 608 select SYS_FSL_ERRATUM_A004508 609 select SYS_FSL_ERRATUM_A005125 610 select SYS_FSL_ERRATUM_ELBC_A001 611 select SYS_FSL_ERRATUM_ESDHC111 612 select SYS_FSL_HAS_DDR3 613 select SYS_FSL_HAS_SEC 614 select SYS_FSL_SEC_BE 615 select SYS_FSL_SEC_COMPAT_2 616 select SYS_PPC_E500_USE_DEBUG_TLB 617 618config ARCH_P2020 619 bool 620 select FSL_LAW 621 select SYS_FSL_ERRATUM_A004477 622 select SYS_FSL_ERRATUM_A004508 623 select SYS_FSL_ERRATUM_A005125 624 select SYS_FSL_ERRATUM_ESDHC111 625 select SYS_FSL_ERRATUM_ESDHC_A001 626 select SYS_FSL_HAS_DDR3 627 select SYS_FSL_HAS_SEC 628 select SYS_FSL_SEC_BE 629 select SYS_FSL_SEC_COMPAT_2 630 select SYS_PPC_E500_USE_DEBUG_TLB 631 632config ARCH_P2041 633 bool 634 select E500MC 635 select FSL_LAW 636 select SYS_FSL_ERRATUM_A004510 637 select SYS_FSL_ERRATUM_A004849 638 select SYS_FSL_ERRATUM_A006261 639 select SYS_FSL_ERRATUM_CPU_A003999 640 select SYS_FSL_ERRATUM_DDR_A003 641 select SYS_FSL_ERRATUM_DDR_A003474 642 select SYS_FSL_ERRATUM_ESDHC111 643 select SYS_FSL_ERRATUM_I2C_A004447 644 select SYS_FSL_ERRATUM_NMG_CPU_A011 645 select SYS_FSL_ERRATUM_SRIO_A004034 646 select SYS_FSL_ERRATUM_USB14 647 select SYS_FSL_HAS_DDR3 648 select SYS_FSL_HAS_SEC 649 select SYS_FSL_SEC_BE 650 select SYS_FSL_SEC_COMPAT_4 651 652config ARCH_P3041 653 bool 654 select E500MC 655 select FSL_LAW 656 select SYS_FSL_DDR_VER_44 657 select SYS_FSL_ERRATUM_A004510 658 select SYS_FSL_ERRATUM_A004849 659 select SYS_FSL_ERRATUM_A005812 660 select SYS_FSL_ERRATUM_A006261 661 select SYS_FSL_ERRATUM_CPU_A003999 662 select SYS_FSL_ERRATUM_DDR_A003 663 select SYS_FSL_ERRATUM_DDR_A003474 664 select SYS_FSL_ERRATUM_ESDHC111 665 select SYS_FSL_ERRATUM_I2C_A004447 666 select SYS_FSL_ERRATUM_NMG_CPU_A011 667 select SYS_FSL_ERRATUM_SRIO_A004034 668 select SYS_FSL_ERRATUM_USB14 669 select SYS_FSL_HAS_DDR3 670 select SYS_FSL_HAS_SEC 671 select SYS_FSL_SEC_BE 672 select SYS_FSL_SEC_COMPAT_4 673 674config ARCH_P4080 675 bool 676 select E500MC 677 select FSL_LAW 678 select SYS_FSL_DDR_VER_44 679 select SYS_FSL_ERRATUM_A004510 680 select SYS_FSL_ERRATUM_A004580 681 select SYS_FSL_ERRATUM_A004849 682 select SYS_FSL_ERRATUM_A005812 683 select SYS_FSL_ERRATUM_A007075 684 select SYS_FSL_ERRATUM_CPC_A002 685 select SYS_FSL_ERRATUM_CPC_A003 686 select SYS_FSL_ERRATUM_CPU_A003999 687 select SYS_FSL_ERRATUM_DDR_A003 688 select SYS_FSL_ERRATUM_DDR_A003474 689 select SYS_FSL_ERRATUM_ELBC_A001 690 select SYS_FSL_ERRATUM_ESDHC111 691 select SYS_FSL_ERRATUM_ESDHC13 692 select SYS_FSL_ERRATUM_ESDHC135 693 select SYS_FSL_ERRATUM_I2C_A004447 694 select SYS_FSL_ERRATUM_NMG_CPU_A011 695 select SYS_FSL_ERRATUM_SRIO_A004034 696 select SYS_P4080_ERRATUM_CPU22 697 select SYS_P4080_ERRATUM_PCIE_A003 698 select SYS_P4080_ERRATUM_SERDES8 699 select SYS_P4080_ERRATUM_SERDES9 700 select SYS_P4080_ERRATUM_SERDES_A001 701 select SYS_P4080_ERRATUM_SERDES_A005 702 select SYS_FSL_HAS_DDR3 703 select SYS_FSL_HAS_SEC 704 select SYS_FSL_SEC_BE 705 select SYS_FSL_SEC_COMPAT_4 706 707config ARCH_P5020 708 bool 709 select E500MC 710 select FSL_LAW 711 select SYS_FSL_DDR_VER_44 712 select SYS_FSL_ERRATUM_A004510 713 select SYS_FSL_ERRATUM_A006261 714 select SYS_FSL_ERRATUM_DDR_A003 715 select SYS_FSL_ERRATUM_DDR_A003474 716 select SYS_FSL_ERRATUM_ESDHC111 717 select SYS_FSL_ERRATUM_I2C_A004447 718 select SYS_FSL_ERRATUM_SRIO_A004034 719 select SYS_FSL_ERRATUM_USB14 720 select SYS_FSL_HAS_DDR3 721 select SYS_FSL_HAS_SEC 722 select SYS_FSL_SEC_BE 723 select SYS_FSL_SEC_COMPAT_4 724 725config ARCH_P5040 726 bool 727 select E500MC 728 select FSL_LAW 729 select SYS_FSL_DDR_VER_44 730 select SYS_FSL_ERRATUM_A004510 731 select SYS_FSL_ERRATUM_A004699 732 select SYS_FSL_ERRATUM_A005812 733 select SYS_FSL_ERRATUM_A006261 734 select SYS_FSL_ERRATUM_DDR_A003 735 select SYS_FSL_ERRATUM_DDR_A003474 736 select SYS_FSL_ERRATUM_ESDHC111 737 select SYS_FSL_ERRATUM_USB14 738 select SYS_FSL_HAS_DDR3 739 select SYS_FSL_HAS_SEC 740 select SYS_FSL_SEC_BE 741 select SYS_FSL_SEC_COMPAT_4 742 743config ARCH_QEMU_E500 744 bool 745 746config ARCH_T1023 747 bool 748 select E500MC 749 select FSL_LAW 750 select SYS_FSL_DDR_VER_50 751 select SYS_FSL_ERRATUM_A008378 752 select SYS_FSL_ERRATUM_A009663 753 select SYS_FSL_ERRATUM_A009942 754 select SYS_FSL_ERRATUM_ESDHC111 755 select SYS_FSL_HAS_DDR3 756 select SYS_FSL_HAS_DDR4 757 select SYS_FSL_HAS_SEC 758 select SYS_FSL_SEC_BE 759 select SYS_FSL_SEC_COMPAT_5 760 761config ARCH_T1024 762 bool 763 select E500MC 764 select FSL_LAW 765 select SYS_FSL_DDR_VER_50 766 select SYS_FSL_ERRATUM_A008378 767 select SYS_FSL_ERRATUM_A009663 768 select SYS_FSL_ERRATUM_A009942 769 select SYS_FSL_ERRATUM_ESDHC111 770 select SYS_FSL_HAS_DDR3 771 select SYS_FSL_HAS_DDR4 772 select SYS_FSL_HAS_SEC 773 select SYS_FSL_SEC_BE 774 select SYS_FSL_SEC_COMPAT_5 775 776config ARCH_T1040 777 bool 778 select E500MC 779 select FSL_LAW 780 select SYS_FSL_DDR_VER_50 781 select SYS_FSL_ERRATUM_A008044 782 select SYS_FSL_ERRATUM_A008378 783 select SYS_FSL_ERRATUM_A009663 784 select SYS_FSL_ERRATUM_A009942 785 select SYS_FSL_ERRATUM_ESDHC111 786 select SYS_FSL_HAS_DDR3 787 select SYS_FSL_HAS_DDR4 788 select SYS_FSL_HAS_SEC 789 select SYS_FSL_SEC_BE 790 select SYS_FSL_SEC_COMPAT_5 791 792config ARCH_T1042 793 bool 794 select E500MC 795 select FSL_LAW 796 select SYS_FSL_DDR_VER_50 797 select SYS_FSL_ERRATUM_A008044 798 select SYS_FSL_ERRATUM_A008378 799 select SYS_FSL_ERRATUM_A009663 800 select SYS_FSL_ERRATUM_A009942 801 select SYS_FSL_ERRATUM_ESDHC111 802 select SYS_FSL_HAS_DDR3 803 select SYS_FSL_HAS_DDR4 804 select SYS_FSL_HAS_SEC 805 select SYS_FSL_SEC_BE 806 select SYS_FSL_SEC_COMPAT_5 807 808config ARCH_T2080 809 bool 810 select E500MC 811 select E6500 812 select FSL_LAW 813 select SYS_FSL_DDR_VER_47 814 select SYS_FSL_ERRATUM_A006379 815 select SYS_FSL_ERRATUM_A006593 816 select SYS_FSL_ERRATUM_A007186 817 select SYS_FSL_ERRATUM_A007212 818 select SYS_FSL_ERRATUM_A009942 819 select SYS_FSL_ERRATUM_ESDHC111 820 select SYS_FSL_HAS_DDR3 821 select SYS_FSL_HAS_SEC 822 select SYS_FSL_SEC_BE 823 select SYS_FSL_SEC_COMPAT_4 824 825config ARCH_T2081 826 bool 827 select E500MC 828 select E6500 829 select FSL_LAW 830 select SYS_FSL_DDR_VER_47 831 select SYS_FSL_ERRATUM_A006379 832 select SYS_FSL_ERRATUM_A006593 833 select SYS_FSL_ERRATUM_A007186 834 select SYS_FSL_ERRATUM_A007212 835 select SYS_FSL_ERRATUM_A009942 836 select SYS_FSL_ERRATUM_ESDHC111 837 select SYS_FSL_HAS_DDR3 838 select SYS_FSL_HAS_SEC 839 select SYS_FSL_SEC_BE 840 select SYS_FSL_SEC_COMPAT_4 841 842config ARCH_T4160 843 bool 844 select E500MC 845 select E6500 846 select FSL_LAW 847 select SYS_FSL_DDR_VER_47 848 select SYS_FSL_ERRATUM_A004468 849 select SYS_FSL_ERRATUM_A005871 850 select SYS_FSL_ERRATUM_A006379 851 select SYS_FSL_ERRATUM_A006593 852 select SYS_FSL_ERRATUM_A007186 853 select SYS_FSL_ERRATUM_A007798 854 select SYS_FSL_ERRATUM_A009942 855 select SYS_FSL_HAS_DDR3 856 select SYS_FSL_HAS_SEC 857 select SYS_FSL_SEC_BE 858 select SYS_FSL_SEC_COMPAT_4 859 860config ARCH_T4240 861 bool 862 select E500MC 863 select E6500 864 select FSL_LAW 865 select SYS_FSL_DDR_VER_47 866 select SYS_FSL_ERRATUM_A004468 867 select SYS_FSL_ERRATUM_A005871 868 select SYS_FSL_ERRATUM_A006261 869 select SYS_FSL_ERRATUM_A006379 870 select SYS_FSL_ERRATUM_A006593 871 select SYS_FSL_ERRATUM_A007186 872 select SYS_FSL_ERRATUM_A007798 873 select SYS_FSL_ERRATUM_A009942 874 select SYS_FSL_HAS_DDR3 875 select SYS_FSL_HAS_SEC 876 select SYS_FSL_SEC_BE 877 select SYS_FSL_SEC_COMPAT_4 878 879config BOOKE 880 bool 881 default y 882 883config E500 884 bool 885 default y 886 help 887 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 888 889config E500MC 890 bool 891 help 892 Enble PowerPC E500MC core 893 894config E6500 895 bool 896 help 897 Enable PowerPC E6500 core 898 899config FSL_LAW 900 bool 901 help 902 Use Freescale common code for Local Access Window 903 904config SECURE_BOOT 905 bool "Secure Boot" 906 help 907 Enable Freescale Secure Boot feature. Normally selected 908 by defconfig. If unsure, do not change. 909 910config MAX_CPUS 911 int "Maximum number of CPUs permitted for MPC85xx" 912 default 12 if ARCH_T4240 913 default 8 if ARCH_P4080 || \ 914 ARCH_T4160 915 default 4 if ARCH_B4860 || \ 916 ARCH_P2041 || \ 917 ARCH_P3041 || \ 918 ARCH_P5040 || \ 919 ARCH_T1040 || \ 920 ARCH_T1042 || \ 921 ARCH_T2080 || \ 922 ARCH_T2081 923 default 2 if ARCH_B4420 || \ 924 ARCH_BSC9132 || \ 925 ARCH_MPC8572 || \ 926 ARCH_P1020 || \ 927 ARCH_P1021 || \ 928 ARCH_P1022 || \ 929 ARCH_P1023 || \ 930 ARCH_P1024 || \ 931 ARCH_P1025 || \ 932 ARCH_P2020 || \ 933 ARCH_P5020 || \ 934 ARCH_T1023 || \ 935 ARCH_T1024 936 default 1 937 help 938 Set this number to the maximum number of possible CPUs in the SoC. 939 SoCs may have multiple clusters with each cluster may have multiple 940 ports. If some ports are reserved but higher ports are used for 941 cores, count the reserved ports. This will allocate enough memory 942 in spin table to properly handle all cores. 943 944config SYS_CCSRBAR_DEFAULT 945 hex "Default CCSRBAR address" 946 default 0xff700000 if ARCH_BSC9131 || \ 947 ARCH_BSC9132 || \ 948 ARCH_C29X || \ 949 ARCH_MPC8536 || \ 950 ARCH_MPC8540 || \ 951 ARCH_MPC8541 || \ 952 ARCH_MPC8544 || \ 953 ARCH_MPC8548 || \ 954 ARCH_MPC8555 || \ 955 ARCH_MPC8560 || \ 956 ARCH_MPC8568 || \ 957 ARCH_MPC8569 || \ 958 ARCH_MPC8572 || \ 959 ARCH_P1010 || \ 960 ARCH_P1011 || \ 961 ARCH_P1020 || \ 962 ARCH_P1021 || \ 963 ARCH_P1022 || \ 964 ARCH_P1024 || \ 965 ARCH_P1025 || \ 966 ARCH_P2020 967 default 0xff600000 if ARCH_P1023 968 default 0xfe000000 if ARCH_B4420 || \ 969 ARCH_B4860 || \ 970 ARCH_P2041 || \ 971 ARCH_P3041 || \ 972 ARCH_P4080 || \ 973 ARCH_P5020 || \ 974 ARCH_P5040 || \ 975 ARCH_T1023 || \ 976 ARCH_T1024 || \ 977 ARCH_T1040 || \ 978 ARCH_T1042 || \ 979 ARCH_T2080 || \ 980 ARCH_T2081 || \ 981 ARCH_T4160 || \ 982 ARCH_T4240 983 default 0xe0000000 if ARCH_QEMU_E500 984 help 985 Default value of CCSRBAR comes from power-on-reset. It 986 is fixed on each SoC. Some SoCs can have different value 987 if changed by pre-boot regime. The value here must match 988 the current value in SoC. If not sure, do not change. 989 990config SYS_FSL_ERRATUM_A004468 991 bool 992 993config SYS_FSL_ERRATUM_A004477 994 bool 995 996config SYS_FSL_ERRATUM_A004508 997 bool 998 999config SYS_FSL_ERRATUM_A004580 1000 bool 1001 1002config SYS_FSL_ERRATUM_A004699 1003 bool 1004 1005config SYS_FSL_ERRATUM_A004849 1006 bool 1007 1008config SYS_FSL_ERRATUM_A004510 1009 bool 1010 1011config SYS_FSL_ERRATUM_A004510_SVR_REV 1012 hex 1013 depends on SYS_FSL_ERRATUM_A004510 1014 default 0x20 if ARCH_P4080 1015 default 0x10 1016 1017config SYS_FSL_ERRATUM_A004510_SVR_REV2 1018 hex 1019 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1020 default 0x11 1021 1022config SYS_FSL_ERRATUM_A005125 1023 bool 1024 1025config SYS_FSL_ERRATUM_A005434 1026 bool 1027 1028config SYS_FSL_ERRATUM_A005812 1029 bool 1030 1031config SYS_FSL_ERRATUM_A005871 1032 bool 1033 1034config SYS_FSL_ERRATUM_A006261 1035 bool 1036 1037config SYS_FSL_ERRATUM_A006379 1038 bool 1039 1040config SYS_FSL_ERRATUM_A006384 1041 bool 1042 1043config SYS_FSL_ERRATUM_A006475 1044 bool 1045 1046config SYS_FSL_ERRATUM_A006593 1047 bool 1048 1049config SYS_FSL_ERRATUM_A007075 1050 bool 1051 1052config SYS_FSL_ERRATUM_A007186 1053 bool 1054 1055config SYS_FSL_ERRATUM_A007212 1056 bool 1057 1058config SYS_FSL_ERRATUM_A007798 1059 bool 1060 1061config SYS_FSL_ERRATUM_A008044 1062 bool 1063 1064config SYS_FSL_ERRATUM_CPC_A002 1065 bool 1066 1067config SYS_FSL_ERRATUM_CPC_A003 1068 bool 1069 1070config SYS_FSL_ERRATUM_CPU_A003999 1071 bool 1072 1073config SYS_FSL_ERRATUM_ELBC_A001 1074 bool 1075 1076config SYS_FSL_ERRATUM_I2C_A004447 1077 bool 1078 1079config SYS_FSL_A004447_SVR_REV 1080 hex 1081 depends on SYS_FSL_ERRATUM_I2C_A004447 1082 default 0x00 if ARCH_MPC8548 1083 default 0x10 if ARCH_P1010 1084 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1085 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1086 1087config SYS_FSL_ERRATUM_IFC_A002769 1088 bool 1089 1090config SYS_FSL_ERRATUM_IFC_A003399 1091 bool 1092 1093config SYS_FSL_ERRATUM_NMG_CPU_A011 1094 bool 1095 1096config SYS_FSL_ERRATUM_NMG_ETSEC129 1097 bool 1098 1099config SYS_FSL_ERRATUM_NMG_LBC103 1100 bool 1101 1102config SYS_FSL_ERRATUM_P1010_A003549 1103 bool 1104 1105config SYS_FSL_ERRATUM_SATA_A001 1106 bool 1107 1108config SYS_FSL_ERRATUM_SEC_A003571 1109 bool 1110 1111config SYS_FSL_ERRATUM_SRIO_A004034 1112 bool 1113 1114config SYS_FSL_ERRATUM_USB14 1115 bool 1116 1117config SYS_P4080_ERRATUM_CPU22 1118 bool 1119 1120config SYS_P4080_ERRATUM_PCIE_A003 1121 bool 1122 1123config SYS_P4080_ERRATUM_SERDES8 1124 bool 1125 1126config SYS_P4080_ERRATUM_SERDES9 1127 bool 1128 1129config SYS_P4080_ERRATUM_SERDES_A001 1130 bool 1131 1132config SYS_P4080_ERRATUM_SERDES_A005 1133 bool 1134 1135config SYS_FSL_NUM_LAWS 1136 int "Number of local access windows" 1137 depends on FSL_LAW 1138 default 32 if ARCH_B4420 || \ 1139 ARCH_B4860 || \ 1140 ARCH_P2041 || \ 1141 ARCH_P3041 || \ 1142 ARCH_P4080 || \ 1143 ARCH_P5020 || \ 1144 ARCH_P5040 || \ 1145 ARCH_T2080 || \ 1146 ARCH_T2081 || \ 1147 ARCH_T4160 || \ 1148 ARCH_T4240 1149 default 16 if ARCH_T1023 || \ 1150 ARCH_T1024 || \ 1151 ARCH_T1040 || \ 1152 ARCH_T1042 1153 default 12 if ARCH_BSC9131 || \ 1154 ARCH_BSC9132 || \ 1155 ARCH_C29X || \ 1156 ARCH_MPC8536 || \ 1157 ARCH_MPC8572 || \ 1158 ARCH_P1010 || \ 1159 ARCH_P1011 || \ 1160 ARCH_P1020 || \ 1161 ARCH_P1021 || \ 1162 ARCH_P1022 || \ 1163 ARCH_P1023 || \ 1164 ARCH_P1024 || \ 1165 ARCH_P1025 || \ 1166 ARCH_P2020 1167 default 10 if ARCH_MPC8544 || \ 1168 ARCH_MPC8548 || \ 1169 ARCH_MPC8568 || \ 1170 ARCH_MPC8569 1171 default 8 if ARCH_MPC8540 || \ 1172 ARCH_MPC8541 || \ 1173 ARCH_MPC8555 || \ 1174 ARCH_MPC8560 1175 help 1176 Number of local access windows. This is fixed per SoC. 1177 If not sure, do not change. 1178 1179config SYS_FSL_THREADS_PER_CORE 1180 int 1181 default 2 if E6500 1182 default 1 1183 1184config SYS_NUM_TLBCAMS 1185 int "Number of TLB CAM entries" 1186 default 64 if E500MC 1187 default 16 1188 help 1189 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1190 16 for other E500 SoCs. 1191 1192config SYS_PPC_E500_USE_DEBUG_TLB 1193 bool 1194 1195config SYS_PPC_E500_DEBUG_TLB 1196 int "Temporary TLB entry for external debugger" 1197 depends on SYS_PPC_E500_USE_DEBUG_TLB 1198 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1199 default 1 if ARCH_MPC8536 1200 default 2 if ARCH_MPC8572 || \ 1201 ARCH_P1011 || \ 1202 ARCH_P1020 || \ 1203 ARCH_P1021 || \ 1204 ARCH_P1022 || \ 1205 ARCH_P1024 || \ 1206 ARCH_P1025 || \ 1207 ARCH_P2020 1208 default 3 if ARCH_P1010 || \ 1209 ARCH_BSC9132 || \ 1210 ARCH_C29X 1211 help 1212 Select a temporary TLB entry to be used during boot to work 1213 around limitations in e500v1 and e500v2 external debugger 1214 support. This reduces the portions of the boot code where 1215 breakpoints and single stepping do not work. The value of this 1216 symbol should be set to the TLB1 entry to be used for this 1217 purpose. If unsure, do not change. 1218 1219source "board/freescale/b4860qds/Kconfig" 1220source "board/freescale/bsc9131rdb/Kconfig" 1221source "board/freescale/bsc9132qds/Kconfig" 1222source "board/freescale/c29xpcie/Kconfig" 1223source "board/freescale/corenet_ds/Kconfig" 1224source "board/freescale/mpc8536ds/Kconfig" 1225source "board/freescale/mpc8540ads/Kconfig" 1226source "board/freescale/mpc8541cds/Kconfig" 1227source "board/freescale/mpc8544ds/Kconfig" 1228source "board/freescale/mpc8548cds/Kconfig" 1229source "board/freescale/mpc8555cds/Kconfig" 1230source "board/freescale/mpc8560ads/Kconfig" 1231source "board/freescale/mpc8568mds/Kconfig" 1232source "board/freescale/mpc8569mds/Kconfig" 1233source "board/freescale/mpc8572ds/Kconfig" 1234source "board/freescale/p1010rdb/Kconfig" 1235source "board/freescale/p1022ds/Kconfig" 1236source "board/freescale/p1023rdb/Kconfig" 1237source "board/freescale/p1_p2_rdb_pc/Kconfig" 1238source "board/freescale/p1_twr/Kconfig" 1239source "board/freescale/p2041rdb/Kconfig" 1240source "board/freescale/qemu-ppce500/Kconfig" 1241source "board/freescale/t102xqds/Kconfig" 1242source "board/freescale/t102xrdb/Kconfig" 1243source "board/freescale/t1040qds/Kconfig" 1244source "board/freescale/t104xrdb/Kconfig" 1245source "board/freescale/t208xqds/Kconfig" 1246source "board/freescale/t208xrdb/Kconfig" 1247source "board/freescale/t4qds/Kconfig" 1248source "board/freescale/t4rdb/Kconfig" 1249source "board/gdsys/p1022/Kconfig" 1250source "board/keymile/kmp204x/Kconfig" 1251source "board/sbc8548/Kconfig" 1252source "board/socrates/Kconfig" 1253source "board/varisys/cyrus/Kconfig" 1254source "board/xes/xpedite520x/Kconfig" 1255source "board/xes/xpedite537x/Kconfig" 1256source "board/xes/xpedite550x/Kconfig" 1257source "board/Arcturus/ucp1020/Kconfig" 1258 1259endmenu 1260