1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_SBC8548 12 bool "Support sbc8548" 13 select ARCH_MPC8548 14 15config TARGET_SOCRATES 16 bool "Support socrates" 17 select ARCH_MPC8544 18 19config TARGET_B4420QDS 20 bool "Support B4420QDS" 21 select ARCH_B4420 22 select SUPPORT_SPL 23 select PHYS_64BIT 24 25config TARGET_B4860QDS 26 bool "Support B4860QDS" 27 select ARCH_B4860 28 select SUPPORT_SPL 29 select PHYS_64BIT 30 31config TARGET_BSC9131RDB 32 bool "Support BSC9131RDB" 33 select ARCH_BSC9131 34 select SUPPORT_SPL 35 36config TARGET_BSC9132QDS 37 bool "Support BSC9132QDS" 38 select ARCH_BSC9132 39 select SUPPORT_SPL 40 41config TARGET_C29XPCIE 42 bool "Support C29XPCIE" 43 select ARCH_C29X 44 select SUPPORT_SPL 45 select SUPPORT_TPL 46 select PHYS_64BIT 47 48config TARGET_P3041DS 49 bool "Support P3041DS" 50 select PHYS_64BIT 51 select ARCH_P3041 52 53config TARGET_P4080DS 54 bool "Support P4080DS" 55 select PHYS_64BIT 56 select ARCH_P4080 57 58config TARGET_P5020DS 59 bool "Support P5020DS" 60 select PHYS_64BIT 61 select ARCH_P5020 62 63config TARGET_P5040DS 64 bool "Support P5040DS" 65 select PHYS_64BIT 66 select ARCH_P5040 67 68config TARGET_MPC8536DS 69 bool "Support MPC8536DS" 70 select ARCH_MPC8536 71# Use DDR3 controller with DDR2 DIMMs on this board 72 select SYS_FSL_DDRC_GEN3 73 74config TARGET_MPC8540ADS 75 bool "Support MPC8540ADS" 76 select ARCH_MPC8540 77 78config TARGET_MPC8541CDS 79 bool "Support MPC8541CDS" 80 select ARCH_MPC8541 81 82config TARGET_MPC8544DS 83 bool "Support MPC8544DS" 84 select ARCH_MPC8544 85 86config TARGET_MPC8548CDS 87 bool "Support MPC8548CDS" 88 select ARCH_MPC8548 89 90config TARGET_MPC8555CDS 91 bool "Support MPC8555CDS" 92 select ARCH_MPC8555 93 94config TARGET_MPC8560ADS 95 bool "Support MPC8560ADS" 96 select ARCH_MPC8560 97 98config TARGET_MPC8568MDS 99 bool "Support MPC8568MDS" 100 select ARCH_MPC8568 101 102config TARGET_MPC8569MDS 103 bool "Support MPC8569MDS" 104 select ARCH_MPC8569 105 106config TARGET_MPC8572DS 107 bool "Support MPC8572DS" 108 select ARCH_MPC8572 109# Use DDR3 controller with DDR2 DIMMs on this board 110 select SYS_FSL_DDRC_GEN3 111 112config TARGET_P1010RDB_PA 113 bool "Support P1010RDB_PA" 114 select ARCH_P1010 115 select SUPPORT_SPL 116 select SUPPORT_TPL 117 118config TARGET_P1010RDB_PB 119 bool "Support P1010RDB_PB" 120 select ARCH_P1010 121 select SUPPORT_SPL 122 select SUPPORT_TPL 123 124config TARGET_P1022DS 125 bool "Support P1022DS" 126 select ARCH_P1022 127 select SUPPORT_SPL 128 select SUPPORT_TPL 129 130config TARGET_P1023RDB 131 bool "Support P1023RDB" 132 select ARCH_P1023 133 134config TARGET_P1020MBG 135 bool "Support P1020MBG-PC" 136 select SUPPORT_SPL 137 select SUPPORT_TPL 138 select ARCH_P1020 139 140config TARGET_P1020RDB_PC 141 bool "Support P1020RDB-PC" 142 select SUPPORT_SPL 143 select SUPPORT_TPL 144 select ARCH_P1020 145 146config TARGET_P1020RDB_PD 147 bool "Support P1020RDB-PD" 148 select SUPPORT_SPL 149 select SUPPORT_TPL 150 select ARCH_P1020 151 152config TARGET_P1020UTM 153 bool "Support P1020UTM" 154 select SUPPORT_SPL 155 select SUPPORT_TPL 156 select ARCH_P1020 157 158config TARGET_P1021RDB 159 bool "Support P1021RDB" 160 select SUPPORT_SPL 161 select SUPPORT_TPL 162 select ARCH_P1021 163 164config TARGET_P1024RDB 165 bool "Support P1024RDB" 166 select SUPPORT_SPL 167 select SUPPORT_TPL 168 select ARCH_P1024 169 170config TARGET_P1025RDB 171 bool "Support P1025RDB" 172 select SUPPORT_SPL 173 select SUPPORT_TPL 174 select ARCH_P1025 175 176config TARGET_P2020RDB 177 bool "Support P2020RDB-PC" 178 select SUPPORT_SPL 179 select SUPPORT_TPL 180 select ARCH_P2020 181 182config TARGET_P1_TWR 183 bool "Support p1_twr" 184 select ARCH_P1025 185 186config TARGET_P2041RDB 187 bool "Support P2041RDB" 188 select ARCH_P2041 189 select PHYS_64BIT 190 191config TARGET_QEMU_PPCE500 192 bool "Support qemu-ppce500" 193 select ARCH_QEMU_E500 194 select PHYS_64BIT 195 196config TARGET_T1024QDS 197 bool "Support T1024QDS" 198 select ARCH_T1024 199 select SUPPORT_SPL 200 select PHYS_64BIT 201 202config TARGET_T1023RDB 203 bool "Support T1023RDB" 204 select ARCH_T1023 205 select SUPPORT_SPL 206 select PHYS_64BIT 207 208config TARGET_T1024RDB 209 bool "Support T1024RDB" 210 select ARCH_T1024 211 select SUPPORT_SPL 212 select PHYS_64BIT 213 214config TARGET_T1040QDS 215 bool "Support T1040QDS" 216 select ARCH_T1040 217 select PHYS_64BIT 218 219config TARGET_T1040RDB 220 bool "Support T1040RDB" 221 select ARCH_T1040 222 select SUPPORT_SPL 223 select PHYS_64BIT 224 225config TARGET_T1040D4RDB 226 bool "Support T1040D4RDB" 227 select ARCH_T1040 228 select SUPPORT_SPL 229 select PHYS_64BIT 230 231config TARGET_T1042RDB 232 bool "Support T1042RDB" 233 select ARCH_T1042 234 select SUPPORT_SPL 235 select PHYS_64BIT 236 237config TARGET_T1042D4RDB 238 bool "Support T1042D4RDB" 239 select ARCH_T1042 240 select SUPPORT_SPL 241 select PHYS_64BIT 242 243config TARGET_T1042RDB_PI 244 bool "Support T1042RDB_PI" 245 select ARCH_T1042 246 select SUPPORT_SPL 247 select PHYS_64BIT 248 249config TARGET_T2080QDS 250 bool "Support T2080QDS" 251 select ARCH_T2080 252 select SUPPORT_SPL 253 select PHYS_64BIT 254 255config TARGET_T2080RDB 256 bool "Support T2080RDB" 257 select ARCH_T2080 258 select SUPPORT_SPL 259 select PHYS_64BIT 260 261config TARGET_T2081QDS 262 bool "Support T2081QDS" 263 select ARCH_T2081 264 select SUPPORT_SPL 265 select PHYS_64BIT 266 267config TARGET_T4160QDS 268 bool "Support T4160QDS" 269 select ARCH_T4160 270 select SUPPORT_SPL 271 select PHYS_64BIT 272 273config TARGET_T4160RDB 274 bool "Support T4160RDB" 275 select ARCH_T4160 276 select SUPPORT_SPL 277 select PHYS_64BIT 278 279config TARGET_T4240QDS 280 bool "Support T4240QDS" 281 select ARCH_T4240 282 select SUPPORT_SPL 283 select PHYS_64BIT 284 285config TARGET_T4240RDB 286 bool "Support T4240RDB" 287 select ARCH_T4240 288 select SUPPORT_SPL 289 select PHYS_64BIT 290 291config TARGET_CONTROLCENTERD 292 bool "Support controlcenterd" 293 select ARCH_P1022 294 295config TARGET_KMP204X 296 bool "Support kmp204x" 297 select ARCH_P2041 298 select PHYS_64BIT 299 300config TARGET_XPEDITE520X 301 bool "Support xpedite520x" 302 select ARCH_MPC8548 303 304config TARGET_XPEDITE537X 305 bool "Support xpedite537x" 306 select ARCH_MPC8572 307# Use DDR3 controller with DDR2 DIMMs on this board 308 select SYS_FSL_DDRC_GEN3 309 310config TARGET_XPEDITE550X 311 bool "Support xpedite550x" 312 select ARCH_P2020 313 314config TARGET_UCP1020 315 bool "Support uCP1020" 316 select ARCH_P1020 317 318config TARGET_CYRUS_P5020 319 bool "Support Varisys Cyrus P5020" 320 select ARCH_P5020 321 select PHYS_64BIT 322 323config TARGET_CYRUS_P5040 324 bool "Support Varisys Cyrus P5040" 325 select ARCH_P5040 326 select PHYS_64BIT 327 328endchoice 329 330config ARCH_B4420 331 bool 332 select E500MC 333 select FSL_LAW 334 select SYS_FSL_ERRATUM_A004477 335 select SYS_FSL_ERRATUM_A005871 336 select SYS_FSL_ERRATUM_A006379 337 select SYS_FSL_ERRATUM_A006384 338 select SYS_FSL_ERRATUM_A006475 339 select SYS_FSL_ERRATUM_A006593 340 select SYS_FSL_ERRATUM_A007075 341 select SYS_FSL_ERRATUM_A007186 342 select SYS_FSL_ERRATUM_A007212 343 select SYS_FSL_ERRATUM_A009942 344 select SYS_FSL_HAS_DDR3 345 select SYS_FSL_HAS_SEC 346 select SYS_FSL_SEC_BE 347 select SYS_FSL_SEC_COMPAT_4 348 349config ARCH_B4860 350 bool 351 select E500MC 352 select FSL_LAW 353 select SYS_FSL_ERRATUM_A004477 354 select SYS_FSL_ERRATUM_A005871 355 select SYS_FSL_ERRATUM_A006379 356 select SYS_FSL_ERRATUM_A006384 357 select SYS_FSL_ERRATUM_A006475 358 select SYS_FSL_ERRATUM_A006593 359 select SYS_FSL_ERRATUM_A007075 360 select SYS_FSL_ERRATUM_A007186 361 select SYS_FSL_ERRATUM_A007212 362 select SYS_FSL_ERRATUM_A009942 363 select SYS_FSL_HAS_DDR3 364 select SYS_FSL_HAS_SEC 365 select SYS_FSL_SEC_BE 366 select SYS_FSL_SEC_COMPAT_4 367 368config ARCH_BSC9131 369 bool 370 select FSL_LAW 371 select SYS_FSL_ERRATUM_A004477 372 select SYS_FSL_ERRATUM_A005125 373 select SYS_FSL_ERRATUM_ESDHC111 374 select SYS_FSL_HAS_DDR3 375 select SYS_FSL_HAS_SEC 376 select SYS_FSL_SEC_BE 377 select SYS_FSL_SEC_COMPAT_4 378 379config ARCH_BSC9132 380 bool 381 select FSL_LAW 382 select SYS_FSL_ERRATUM_A004477 383 select SYS_FSL_ERRATUM_A005125 384 select SYS_FSL_ERRATUM_A005434 385 select SYS_FSL_ERRATUM_ESDHC111 386 select SYS_FSL_ERRATUM_I2C_A004447 387 select SYS_FSL_ERRATUM_IFC_A002769 388 select SYS_FSL_HAS_DDR3 389 select SYS_FSL_HAS_SEC 390 select SYS_FSL_SEC_BE 391 select SYS_FSL_SEC_COMPAT_4 392 select SYS_PPC_E500_USE_DEBUG_TLB 393 394config ARCH_C29X 395 bool 396 select FSL_LAW 397 select SYS_FSL_ERRATUM_A005125 398 select SYS_FSL_ERRATUM_ESDHC111 399 select SYS_FSL_HAS_DDR3 400 select SYS_FSL_HAS_SEC 401 select SYS_FSL_SEC_BE 402 select SYS_FSL_SEC_COMPAT_6 403 select SYS_PPC_E500_USE_DEBUG_TLB 404 405config ARCH_MPC8536 406 bool 407 select FSL_LAW 408 select SYS_FSL_ERRATUM_A004508 409 select SYS_FSL_ERRATUM_A005125 410 select SYS_FSL_HAS_DDR2 411 select SYS_FSL_HAS_DDR3 412 select SYS_FSL_HAS_SEC 413 select SYS_FSL_SEC_BE 414 select SYS_FSL_SEC_COMPAT_2 415 select SYS_PPC_E500_USE_DEBUG_TLB 416 417config ARCH_MPC8540 418 bool 419 select FSL_LAW 420 select SYS_FSL_HAS_DDR1 421 422config ARCH_MPC8541 423 bool 424 select FSL_LAW 425 select SYS_FSL_HAS_DDR1 426 select SYS_FSL_HAS_SEC 427 select SYS_FSL_SEC_BE 428 select SYS_FSL_SEC_COMPAT_2 429 430config ARCH_MPC8544 431 bool 432 select FSL_LAW 433 select SYS_FSL_ERRATUM_A005125 434 select SYS_FSL_HAS_DDR2 435 select SYS_FSL_HAS_SEC 436 select SYS_FSL_SEC_BE 437 select SYS_FSL_SEC_COMPAT_2 438 select SYS_PPC_E500_USE_DEBUG_TLB 439 440config ARCH_MPC8548 441 bool 442 select FSL_LAW 443 select SYS_FSL_ERRATUM_A005125 444 select SYS_FSL_ERRATUM_NMG_DDR120 445 select SYS_FSL_ERRATUM_NMG_LBC103 446 select SYS_FSL_ERRATUM_NMG_ETSEC129 447 select SYS_FSL_ERRATUM_I2C_A004447 448 select SYS_FSL_HAS_DDR2 449 select SYS_FSL_HAS_DDR1 450 select SYS_FSL_HAS_SEC 451 select SYS_FSL_SEC_BE 452 select SYS_FSL_SEC_COMPAT_2 453 select SYS_PPC_E500_USE_DEBUG_TLB 454 455config ARCH_MPC8555 456 bool 457 select FSL_LAW 458 select SYS_FSL_HAS_DDR1 459 select SYS_FSL_HAS_SEC 460 select SYS_FSL_SEC_BE 461 select SYS_FSL_SEC_COMPAT_2 462 463config ARCH_MPC8560 464 bool 465 select FSL_LAW 466 select SYS_FSL_HAS_DDR1 467 468config ARCH_MPC8568 469 bool 470 select FSL_LAW 471 select SYS_FSL_HAS_DDR2 472 select SYS_FSL_HAS_SEC 473 select SYS_FSL_SEC_BE 474 select SYS_FSL_SEC_COMPAT_2 475 476config ARCH_MPC8569 477 bool 478 select FSL_LAW 479 select SYS_FSL_ERRATUM_A004508 480 select SYS_FSL_ERRATUM_A005125 481 select SYS_FSL_HAS_DDR3 482 select SYS_FSL_HAS_SEC 483 select SYS_FSL_SEC_BE 484 select SYS_FSL_SEC_COMPAT_2 485 486config ARCH_MPC8572 487 bool 488 select FSL_LAW 489 select SYS_FSL_ERRATUM_A004508 490 select SYS_FSL_ERRATUM_A005125 491 select SYS_FSL_ERRATUM_DDR_115 492 select SYS_FSL_ERRATUM_DDR111_DDR134 493 select SYS_FSL_HAS_DDR2 494 select SYS_FSL_HAS_DDR3 495 select SYS_FSL_HAS_SEC 496 select SYS_FSL_SEC_BE 497 select SYS_FSL_SEC_COMPAT_2 498 select SYS_PPC_E500_USE_DEBUG_TLB 499 500config ARCH_P1010 501 bool 502 select FSL_LAW 503 select SYS_FSL_ERRATUM_A004477 504 select SYS_FSL_ERRATUM_A004508 505 select SYS_FSL_ERRATUM_A005125 506 select SYS_FSL_ERRATUM_A006261 507 select SYS_FSL_ERRATUM_A007075 508 select SYS_FSL_ERRATUM_ESDHC111 509 select SYS_FSL_ERRATUM_I2C_A004447 510 select SYS_FSL_ERRATUM_IFC_A002769 511 select SYS_FSL_ERRATUM_P1010_A003549 512 select SYS_FSL_ERRATUM_SEC_A003571 513 select SYS_FSL_ERRATUM_IFC_A003399 514 select SYS_FSL_HAS_DDR3 515 select SYS_FSL_HAS_SEC 516 select SYS_FSL_SEC_BE 517 select SYS_FSL_SEC_COMPAT_4 518 select SYS_PPC_E500_USE_DEBUG_TLB 519 520config ARCH_P1011 521 bool 522 select FSL_LAW 523 select SYS_FSL_ERRATUM_A004508 524 select SYS_FSL_ERRATUM_A005125 525 select SYS_FSL_ERRATUM_ELBC_A001 526 select SYS_FSL_ERRATUM_ESDHC111 527 select SYS_FSL_HAS_DDR3 528 select SYS_FSL_HAS_SEC 529 select SYS_FSL_SEC_BE 530 select SYS_FSL_SEC_COMPAT_2 531 select SYS_PPC_E500_USE_DEBUG_TLB 532 533config ARCH_P1020 534 bool 535 select FSL_LAW 536 select SYS_FSL_ERRATUM_A004508 537 select SYS_FSL_ERRATUM_A005125 538 select SYS_FSL_ERRATUM_ELBC_A001 539 select SYS_FSL_ERRATUM_ESDHC111 540 select SYS_FSL_HAS_DDR3 541 select SYS_FSL_HAS_SEC 542 select SYS_FSL_SEC_BE 543 select SYS_FSL_SEC_COMPAT_2 544 select SYS_PPC_E500_USE_DEBUG_TLB 545 546config ARCH_P1021 547 bool 548 select FSL_LAW 549 select SYS_FSL_ERRATUM_A004508 550 select SYS_FSL_ERRATUM_A005125 551 select SYS_FSL_ERRATUM_ELBC_A001 552 select SYS_FSL_ERRATUM_ESDHC111 553 select SYS_FSL_HAS_DDR3 554 select SYS_FSL_HAS_SEC 555 select SYS_FSL_SEC_BE 556 select SYS_FSL_SEC_COMPAT_2 557 select SYS_PPC_E500_USE_DEBUG_TLB 558 559config ARCH_P1022 560 bool 561 select FSL_LAW 562 select SYS_FSL_ERRATUM_A004477 563 select SYS_FSL_ERRATUM_A004508 564 select SYS_FSL_ERRATUM_A005125 565 select SYS_FSL_ERRATUM_ELBC_A001 566 select SYS_FSL_ERRATUM_ESDHC111 567 select SYS_FSL_ERRATUM_SATA_A001 568 select SYS_FSL_HAS_DDR3 569 select SYS_FSL_HAS_SEC 570 select SYS_FSL_SEC_BE 571 select SYS_FSL_SEC_COMPAT_2 572 select SYS_PPC_E500_USE_DEBUG_TLB 573 574config ARCH_P1023 575 bool 576 select FSL_LAW 577 select SYS_FSL_ERRATUM_A004508 578 select SYS_FSL_ERRATUM_A005125 579 select SYS_FSL_ERRATUM_I2C_A004447 580 select SYS_FSL_HAS_DDR3 581 select SYS_FSL_HAS_SEC 582 select SYS_FSL_SEC_BE 583 select SYS_FSL_SEC_COMPAT_4 584 585config ARCH_P1024 586 bool 587 select FSL_LAW 588 select SYS_FSL_ERRATUM_A004508 589 select SYS_FSL_ERRATUM_A005125 590 select SYS_FSL_ERRATUM_ELBC_A001 591 select SYS_FSL_ERRATUM_ESDHC111 592 select SYS_FSL_HAS_DDR3 593 select SYS_FSL_HAS_SEC 594 select SYS_FSL_SEC_BE 595 select SYS_FSL_SEC_COMPAT_2 596 select SYS_PPC_E500_USE_DEBUG_TLB 597 598config ARCH_P1025 599 bool 600 select FSL_LAW 601 select SYS_FSL_ERRATUM_A004508 602 select SYS_FSL_ERRATUM_A005125 603 select SYS_FSL_ERRATUM_ELBC_A001 604 select SYS_FSL_ERRATUM_ESDHC111 605 select SYS_FSL_HAS_DDR3 606 select SYS_FSL_HAS_SEC 607 select SYS_FSL_SEC_BE 608 select SYS_FSL_SEC_COMPAT_2 609 select SYS_PPC_E500_USE_DEBUG_TLB 610 611config ARCH_P2020 612 bool 613 select FSL_LAW 614 select SYS_FSL_ERRATUM_A004477 615 select SYS_FSL_ERRATUM_A004508 616 select SYS_FSL_ERRATUM_A005125 617 select SYS_FSL_ERRATUM_ESDHC111 618 select SYS_FSL_ERRATUM_ESDHC_A001 619 select SYS_FSL_HAS_DDR3 620 select SYS_FSL_HAS_SEC 621 select SYS_FSL_SEC_BE 622 select SYS_FSL_SEC_COMPAT_2 623 select SYS_PPC_E500_USE_DEBUG_TLB 624 625config ARCH_P2041 626 bool 627 select E500MC 628 select FSL_LAW 629 select SYS_FSL_ERRATUM_A004510 630 select SYS_FSL_ERRATUM_A004849 631 select SYS_FSL_ERRATUM_A006261 632 select SYS_FSL_ERRATUM_CPU_A003999 633 select SYS_FSL_ERRATUM_DDR_A003 634 select SYS_FSL_ERRATUM_DDR_A003474 635 select SYS_FSL_ERRATUM_ESDHC111 636 select SYS_FSL_ERRATUM_I2C_A004447 637 select SYS_FSL_ERRATUM_NMG_CPU_A011 638 select SYS_FSL_ERRATUM_SRIO_A004034 639 select SYS_FSL_ERRATUM_USB14 640 select SYS_FSL_HAS_DDR3 641 select SYS_FSL_HAS_SEC 642 select SYS_FSL_SEC_BE 643 select SYS_FSL_SEC_COMPAT_4 644 645config ARCH_P3041 646 bool 647 select E500MC 648 select FSL_LAW 649 select SYS_FSL_ERRATUM_A004510 650 select SYS_FSL_ERRATUM_A004849 651 select SYS_FSL_ERRATUM_A005812 652 select SYS_FSL_ERRATUM_A006261 653 select SYS_FSL_ERRATUM_CPU_A003999 654 select SYS_FSL_ERRATUM_DDR_A003 655 select SYS_FSL_ERRATUM_DDR_A003474 656 select SYS_FSL_ERRATUM_ESDHC111 657 select SYS_FSL_ERRATUM_I2C_A004447 658 select SYS_FSL_ERRATUM_NMG_CPU_A011 659 select SYS_FSL_ERRATUM_SRIO_A004034 660 select SYS_FSL_ERRATUM_USB14 661 select SYS_FSL_HAS_DDR3 662 select SYS_FSL_HAS_SEC 663 select SYS_FSL_SEC_BE 664 select SYS_FSL_SEC_COMPAT_4 665 666config ARCH_P4080 667 bool 668 select E500MC 669 select FSL_LAW 670 select SYS_FSL_ERRATUM_A004510 671 select SYS_FSL_ERRATUM_A004580 672 select SYS_FSL_ERRATUM_A004849 673 select SYS_FSL_ERRATUM_A005812 674 select SYS_FSL_ERRATUM_A007075 675 select SYS_FSL_ERRATUM_CPC_A002 676 select SYS_FSL_ERRATUM_CPC_A003 677 select SYS_FSL_ERRATUM_CPU_A003999 678 select SYS_FSL_ERRATUM_DDR_A003 679 select SYS_FSL_ERRATUM_DDR_A003474 680 select SYS_FSL_ERRATUM_ELBC_A001 681 select SYS_FSL_ERRATUM_ESDHC111 682 select SYS_FSL_ERRATUM_ESDHC13 683 select SYS_FSL_ERRATUM_ESDHC135 684 select SYS_FSL_ERRATUM_I2C_A004447 685 select SYS_FSL_ERRATUM_NMG_CPU_A011 686 select SYS_FSL_ERRATUM_SRIO_A004034 687 select SYS_P4080_ERRATUM_CPU22 688 select SYS_P4080_ERRATUM_PCIE_A003 689 select SYS_P4080_ERRATUM_SERDES8 690 select SYS_P4080_ERRATUM_SERDES9 691 select SYS_P4080_ERRATUM_SERDES_A001 692 select SYS_P4080_ERRATUM_SERDES_A005 693 select SYS_FSL_HAS_DDR3 694 select SYS_FSL_HAS_SEC 695 select SYS_FSL_SEC_BE 696 select SYS_FSL_SEC_COMPAT_4 697 698config ARCH_P5020 699 bool 700 select E500MC 701 select FSL_LAW 702 select SYS_FSL_ERRATUM_A004510 703 select SYS_FSL_ERRATUM_A006261 704 select SYS_FSL_ERRATUM_DDR_A003 705 select SYS_FSL_ERRATUM_DDR_A003474 706 select SYS_FSL_ERRATUM_ESDHC111 707 select SYS_FSL_ERRATUM_I2C_A004447 708 select SYS_FSL_ERRATUM_SRIO_A004034 709 select SYS_FSL_ERRATUM_USB14 710 select SYS_FSL_HAS_DDR3 711 select SYS_FSL_HAS_SEC 712 select SYS_FSL_SEC_BE 713 select SYS_FSL_SEC_COMPAT_4 714 715config ARCH_P5040 716 bool 717 select E500MC 718 select FSL_LAW 719 select SYS_FSL_ERRATUM_A004510 720 select SYS_FSL_ERRATUM_A004699 721 select SYS_FSL_ERRATUM_A005812 722 select SYS_FSL_ERRATUM_A006261 723 select SYS_FSL_ERRATUM_DDR_A003 724 select SYS_FSL_ERRATUM_DDR_A003474 725 select SYS_FSL_ERRATUM_ESDHC111 726 select SYS_FSL_ERRATUM_USB14 727 select SYS_FSL_HAS_DDR3 728 select SYS_FSL_HAS_SEC 729 select SYS_FSL_SEC_BE 730 select SYS_FSL_SEC_COMPAT_4 731 732config ARCH_QEMU_E500 733 bool 734 735config ARCH_T1023 736 bool 737 select E500MC 738 select FSL_LAW 739 select SYS_FSL_ERRATUM_A008378 740 select SYS_FSL_ERRATUM_A009663 741 select SYS_FSL_ERRATUM_A009942 742 select SYS_FSL_ERRATUM_ESDHC111 743 select SYS_FSL_HAS_DDR3 744 select SYS_FSL_HAS_DDR4 745 select SYS_FSL_HAS_SEC 746 select SYS_FSL_SEC_BE 747 select SYS_FSL_SEC_COMPAT_5 748 749config ARCH_T1024 750 bool 751 select E500MC 752 select FSL_LAW 753 select SYS_FSL_ERRATUM_A008378 754 select SYS_FSL_ERRATUM_A009663 755 select SYS_FSL_ERRATUM_A009942 756 select SYS_FSL_ERRATUM_ESDHC111 757 select SYS_FSL_HAS_DDR3 758 select SYS_FSL_HAS_DDR4 759 select SYS_FSL_HAS_SEC 760 select SYS_FSL_SEC_BE 761 select SYS_FSL_SEC_COMPAT_5 762 763config ARCH_T1040 764 bool 765 select E500MC 766 select FSL_LAW 767 select SYS_FSL_ERRATUM_A008044 768 select SYS_FSL_ERRATUM_A008378 769 select SYS_FSL_ERRATUM_A009663 770 select SYS_FSL_ERRATUM_A009942 771 select SYS_FSL_ERRATUM_ESDHC111 772 select SYS_FSL_HAS_DDR3 773 select SYS_FSL_HAS_DDR4 774 select SYS_FSL_HAS_SEC 775 select SYS_FSL_SEC_BE 776 select SYS_FSL_SEC_COMPAT_5 777 778config ARCH_T1042 779 bool 780 select E500MC 781 select FSL_LAW 782 select SYS_FSL_ERRATUM_A008044 783 select SYS_FSL_ERRATUM_A008378 784 select SYS_FSL_ERRATUM_A009663 785 select SYS_FSL_ERRATUM_A009942 786 select SYS_FSL_ERRATUM_ESDHC111 787 select SYS_FSL_HAS_DDR3 788 select SYS_FSL_HAS_DDR4 789 select SYS_FSL_HAS_SEC 790 select SYS_FSL_SEC_BE 791 select SYS_FSL_SEC_COMPAT_5 792 793config ARCH_T2080 794 bool 795 select E500MC 796 select FSL_LAW 797 select SYS_FSL_ERRATUM_A006379 798 select SYS_FSL_ERRATUM_A006593 799 select SYS_FSL_ERRATUM_A007186 800 select SYS_FSL_ERRATUM_A007212 801 select SYS_FSL_ERRATUM_A009942 802 select SYS_FSL_ERRATUM_ESDHC111 803 select SYS_FSL_HAS_DDR3 804 select SYS_FSL_HAS_SEC 805 select SYS_FSL_SEC_BE 806 select SYS_FSL_SEC_COMPAT_4 807 808config ARCH_T2081 809 bool 810 select E500MC 811 select FSL_LAW 812 select SYS_FSL_ERRATUM_A006379 813 select SYS_FSL_ERRATUM_A006593 814 select SYS_FSL_ERRATUM_A007186 815 select SYS_FSL_ERRATUM_A007212 816 select SYS_FSL_ERRATUM_A009942 817 select SYS_FSL_ERRATUM_ESDHC111 818 select SYS_FSL_HAS_DDR3 819 select SYS_FSL_HAS_SEC 820 select SYS_FSL_SEC_BE 821 select SYS_FSL_SEC_COMPAT_4 822 823config ARCH_T4160 824 bool 825 select E500MC 826 select FSL_LAW 827 select SYS_FSL_ERRATUM_A004468 828 select SYS_FSL_ERRATUM_A005871 829 select SYS_FSL_ERRATUM_A006379 830 select SYS_FSL_ERRATUM_A006593 831 select SYS_FSL_ERRATUM_A007186 832 select SYS_FSL_ERRATUM_A007798 833 select SYS_FSL_ERRATUM_A009942 834 select SYS_FSL_HAS_DDR3 835 select SYS_FSL_HAS_SEC 836 select SYS_FSL_SEC_BE 837 select SYS_FSL_SEC_COMPAT_4 838 839config ARCH_T4240 840 bool 841 select E500MC 842 select FSL_LAW 843 select SYS_FSL_ERRATUM_A004468 844 select SYS_FSL_ERRATUM_A005871 845 select SYS_FSL_ERRATUM_A006261 846 select SYS_FSL_ERRATUM_A006379 847 select SYS_FSL_ERRATUM_A006593 848 select SYS_FSL_ERRATUM_A007186 849 select SYS_FSL_ERRATUM_A007798 850 select SYS_FSL_ERRATUM_A009942 851 select SYS_FSL_HAS_DDR3 852 select SYS_FSL_HAS_SEC 853 select SYS_FSL_SEC_BE 854 select SYS_FSL_SEC_COMPAT_4 855 856config BOOKE 857 bool 858 default y 859 860config E500 861 bool 862 default y 863 help 864 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 865 866config E500MC 867 bool 868 help 869 Enble PowerPC E500MC core 870 871config FSL_LAW 872 bool 873 help 874 Use Freescale common code for Local Access Window 875 876config SECURE_BOOT 877 bool "Secure Boot" 878 help 879 Enable Freescale Secure Boot feature. Normally selected 880 by defconfig. If unsure, do not change. 881 882config MAX_CPUS 883 int "Maximum number of CPUs permitted for MPC85xx" 884 default 12 if ARCH_T4240 885 default 8 if ARCH_P4080 || \ 886 ARCH_T4160 887 default 4 if ARCH_B4860 || \ 888 ARCH_P2041 || \ 889 ARCH_P3041 || \ 890 ARCH_P5040 || \ 891 ARCH_T1040 || \ 892 ARCH_T1042 || \ 893 ARCH_T2080 || \ 894 ARCH_T2081 895 default 2 if ARCH_B4420 || \ 896 ARCH_BSC9132 || \ 897 ARCH_MPC8572 || \ 898 ARCH_P1020 || \ 899 ARCH_P1021 || \ 900 ARCH_P1022 || \ 901 ARCH_P1023 || \ 902 ARCH_P1024 || \ 903 ARCH_P1025 || \ 904 ARCH_P2020 || \ 905 ARCH_P5020 || \ 906 ARCH_T1023 || \ 907 ARCH_T1024 908 default 1 909 help 910 Set this number to the maximum number of possible CPUs in the SoC. 911 SoCs may have multiple clusters with each cluster may have multiple 912 ports. If some ports are reserved but higher ports are used for 913 cores, count the reserved ports. This will allocate enough memory 914 in spin table to properly handle all cores. 915 916config SYS_CCSRBAR_DEFAULT 917 hex "Default CCSRBAR address" 918 default 0xff700000 if ARCH_BSC9131 || \ 919 ARCH_BSC9132 || \ 920 ARCH_C29X || \ 921 ARCH_MPC8536 || \ 922 ARCH_MPC8540 || \ 923 ARCH_MPC8541 || \ 924 ARCH_MPC8544 || \ 925 ARCH_MPC8548 || \ 926 ARCH_MPC8555 || \ 927 ARCH_MPC8560 || \ 928 ARCH_MPC8568 || \ 929 ARCH_MPC8569 || \ 930 ARCH_MPC8572 || \ 931 ARCH_P1010 || \ 932 ARCH_P1011 || \ 933 ARCH_P1020 || \ 934 ARCH_P1021 || \ 935 ARCH_P1022 || \ 936 ARCH_P1024 || \ 937 ARCH_P1025 || \ 938 ARCH_P2020 939 default 0xff600000 if ARCH_P1023 940 default 0xfe000000 if ARCH_B4420 || \ 941 ARCH_B4860 || \ 942 ARCH_P2041 || \ 943 ARCH_P3041 || \ 944 ARCH_P4080 || \ 945 ARCH_P5020 || \ 946 ARCH_P5040 || \ 947 ARCH_T1023 || \ 948 ARCH_T1024 || \ 949 ARCH_T1040 || \ 950 ARCH_T1042 || \ 951 ARCH_T2080 || \ 952 ARCH_T2081 || \ 953 ARCH_T4160 || \ 954 ARCH_T4240 955 default 0xe0000000 if ARCH_QEMU_E500 956 help 957 Default value of CCSRBAR comes from power-on-reset. It 958 is fixed on each SoC. Some SoCs can have different value 959 if changed by pre-boot regime. The value here must match 960 the current value in SoC. If not sure, do not change. 961 962config SYS_FSL_ERRATUM_A004468 963 bool 964 965config SYS_FSL_ERRATUM_A004477 966 bool 967 968config SYS_FSL_ERRATUM_A004508 969 bool 970 971config SYS_FSL_ERRATUM_A004580 972 bool 973 974config SYS_FSL_ERRATUM_A004699 975 bool 976 977config SYS_FSL_ERRATUM_A004849 978 bool 979 980config SYS_FSL_ERRATUM_A004510 981 bool 982 983config SYS_FSL_ERRATUM_A004510_SVR_REV 984 hex 985 depends on SYS_FSL_ERRATUM_A004510 986 default 0x20 if ARCH_P4080 987 default 0x10 988 989config SYS_FSL_ERRATUM_A004510_SVR_REV2 990 hex 991 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 992 default 0x11 993 994config SYS_FSL_ERRATUM_A005125 995 bool 996 997config SYS_FSL_ERRATUM_A005434 998 bool 999 1000config SYS_FSL_ERRATUM_A005812 1001 bool 1002 1003config SYS_FSL_ERRATUM_A005871 1004 bool 1005 1006config SYS_FSL_ERRATUM_A006261 1007 bool 1008 1009config SYS_FSL_ERRATUM_A006379 1010 bool 1011 1012config SYS_FSL_ERRATUM_A006384 1013 bool 1014 1015config SYS_FSL_ERRATUM_A006475 1016 bool 1017 1018config SYS_FSL_ERRATUM_A006593 1019 bool 1020 1021config SYS_FSL_ERRATUM_A007075 1022 bool 1023 1024config SYS_FSL_ERRATUM_A007186 1025 bool 1026 1027config SYS_FSL_ERRATUM_A007212 1028 bool 1029 1030config SYS_FSL_ERRATUM_A007798 1031 bool 1032 1033config SYS_FSL_ERRATUM_A008044 1034 bool 1035 1036config SYS_FSL_ERRATUM_CPC_A002 1037 bool 1038 1039config SYS_FSL_ERRATUM_CPC_A003 1040 bool 1041 1042config SYS_FSL_ERRATUM_CPU_A003999 1043 bool 1044 1045config SYS_FSL_ERRATUM_ELBC_A001 1046 bool 1047 1048config SYS_FSL_ERRATUM_I2C_A004447 1049 bool 1050 1051config SYS_FSL_A004447_SVR_REV 1052 hex 1053 depends on SYS_FSL_ERRATUM_I2C_A004447 1054 default 0x00 if ARCH_MPC8548 1055 default 0x10 if ARCH_P1010 1056 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1057 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1058 1059config SYS_FSL_ERRATUM_IFC_A002769 1060 bool 1061 1062config SYS_FSL_ERRATUM_IFC_A003399 1063 bool 1064 1065config SYS_FSL_ERRATUM_NMG_CPU_A011 1066 bool 1067 1068config SYS_FSL_ERRATUM_NMG_ETSEC129 1069 bool 1070 1071config SYS_FSL_ERRATUM_NMG_LBC103 1072 bool 1073 1074config SYS_FSL_ERRATUM_P1010_A003549 1075 bool 1076 1077config SYS_FSL_ERRATUM_SATA_A001 1078 bool 1079 1080config SYS_FSL_ERRATUM_SEC_A003571 1081 bool 1082 1083config SYS_FSL_ERRATUM_SRIO_A004034 1084 bool 1085 1086config SYS_FSL_ERRATUM_USB14 1087 bool 1088 1089config SYS_P4080_ERRATUM_CPU22 1090 bool 1091 1092config SYS_P4080_ERRATUM_PCIE_A003 1093 bool 1094 1095config SYS_P4080_ERRATUM_SERDES8 1096 bool 1097 1098config SYS_P4080_ERRATUM_SERDES9 1099 bool 1100 1101config SYS_P4080_ERRATUM_SERDES_A001 1102 bool 1103 1104config SYS_P4080_ERRATUM_SERDES_A005 1105 bool 1106 1107config SYS_FSL_NUM_LAWS 1108 int "Number of local access windows" 1109 depends on FSL_LAW 1110 default 32 if ARCH_B4420 || \ 1111 ARCH_B4860 || \ 1112 ARCH_P2041 || \ 1113 ARCH_P3041 || \ 1114 ARCH_P4080 || \ 1115 ARCH_P5020 || \ 1116 ARCH_P5040 || \ 1117 ARCH_T2080 || \ 1118 ARCH_T2081 || \ 1119 ARCH_T4160 || \ 1120 ARCH_T4240 1121 default 16 if ARCH_T1023 || \ 1122 ARCH_T1024 || \ 1123 ARCH_T1040 || \ 1124 ARCH_T1042 1125 default 12 if ARCH_BSC9131 || \ 1126 ARCH_BSC9132 || \ 1127 ARCH_C29X || \ 1128 ARCH_MPC8536 || \ 1129 ARCH_MPC8572 || \ 1130 ARCH_P1010 || \ 1131 ARCH_P1011 || \ 1132 ARCH_P1020 || \ 1133 ARCH_P1021 || \ 1134 ARCH_P1022 || \ 1135 ARCH_P1023 || \ 1136 ARCH_P1024 || \ 1137 ARCH_P1025 || \ 1138 ARCH_P2020 1139 default 10 if ARCH_MPC8544 || \ 1140 ARCH_MPC8548 || \ 1141 ARCH_MPC8568 || \ 1142 ARCH_MPC8569 1143 default 8 if ARCH_MPC8540 || \ 1144 ARCH_MPC8541 || \ 1145 ARCH_MPC8555 || \ 1146 ARCH_MPC8560 1147 help 1148 Number of local access windows. This is fixed per SoC. 1149 If not sure, do not change. 1150 1151config SYS_NUM_TLBCAMS 1152 int "Number of TLB CAM entries" 1153 default 64 if E500MC 1154 default 16 1155 help 1156 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1157 16 for other E500 SoCs. 1158 1159config SYS_PPC_E500_USE_DEBUG_TLB 1160 bool 1161 1162config SYS_PPC_E500_DEBUG_TLB 1163 int "Temporary TLB entry for external debugger" 1164 depends on SYS_PPC_E500_USE_DEBUG_TLB 1165 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1166 default 1 if ARCH_MPC8536 1167 default 2 if ARCH_MPC8572 || \ 1168 ARCH_P1011 || \ 1169 ARCH_P1020 || \ 1170 ARCH_P1021 || \ 1171 ARCH_P1022 || \ 1172 ARCH_P1024 || \ 1173 ARCH_P1025 || \ 1174 ARCH_P2020 1175 default 3 if ARCH_P1010 || \ 1176 ARCH_BSC9132 || \ 1177 ARCH_C29X 1178 help 1179 Select a temporary TLB entry to be used during boot to work 1180 around limitations in e500v1 and e500v2 external debugger 1181 support. This reduces the portions of the boot code where 1182 breakpoints and single stepping do not work. The value of this 1183 symbol should be set to the TLB1 entry to be used for this 1184 purpose. If unsure, do not change. 1185 1186source "board/freescale/b4860qds/Kconfig" 1187source "board/freescale/bsc9131rdb/Kconfig" 1188source "board/freescale/bsc9132qds/Kconfig" 1189source "board/freescale/c29xpcie/Kconfig" 1190source "board/freescale/corenet_ds/Kconfig" 1191source "board/freescale/mpc8536ds/Kconfig" 1192source "board/freescale/mpc8540ads/Kconfig" 1193source "board/freescale/mpc8541cds/Kconfig" 1194source "board/freescale/mpc8544ds/Kconfig" 1195source "board/freescale/mpc8548cds/Kconfig" 1196source "board/freescale/mpc8555cds/Kconfig" 1197source "board/freescale/mpc8560ads/Kconfig" 1198source "board/freescale/mpc8568mds/Kconfig" 1199source "board/freescale/mpc8569mds/Kconfig" 1200source "board/freescale/mpc8572ds/Kconfig" 1201source "board/freescale/p1010rdb/Kconfig" 1202source "board/freescale/p1022ds/Kconfig" 1203source "board/freescale/p1023rdb/Kconfig" 1204source "board/freescale/p1_p2_rdb_pc/Kconfig" 1205source "board/freescale/p1_twr/Kconfig" 1206source "board/freescale/p2041rdb/Kconfig" 1207source "board/freescale/qemu-ppce500/Kconfig" 1208source "board/freescale/t102xqds/Kconfig" 1209source "board/freescale/t102xrdb/Kconfig" 1210source "board/freescale/t1040qds/Kconfig" 1211source "board/freescale/t104xrdb/Kconfig" 1212source "board/freescale/t208xqds/Kconfig" 1213source "board/freescale/t208xrdb/Kconfig" 1214source "board/freescale/t4qds/Kconfig" 1215source "board/freescale/t4rdb/Kconfig" 1216source "board/gdsys/p1022/Kconfig" 1217source "board/keymile/kmp204x/Kconfig" 1218source "board/sbc8548/Kconfig" 1219source "board/socrates/Kconfig" 1220source "board/varisys/cyrus/Kconfig" 1221source "board/xes/xpedite520x/Kconfig" 1222source "board/xes/xpedite537x/Kconfig" 1223source "board/xes/xpedite550x/Kconfig" 1224source "board/Arcturus/ucp1020/Kconfig" 1225 1226endmenu 1227