1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 23config TARGET_SOCRATES 24 bool "Support socrates" 25 select ARCH_MPC8544 26 27config TARGET_B4420QDS 28 bool "Support B4420QDS" 29 select ARCH_B4420 30 select SUPPORT_SPL 31 select PHYS_64BIT 32 33config TARGET_B4860QDS 34 bool "Support B4860QDS" 35 select ARCH_B4860 36 select BOARD_LATE_INIT if CHAIN_OF_TRUST 37 select SUPPORT_SPL 38 select PHYS_64BIT 39 40config TARGET_BSC9131RDB 41 bool "Support BSC9131RDB" 42 select ARCH_BSC9131 43 select SUPPORT_SPL 44 select BOARD_EARLY_INIT_F 45 46config TARGET_BSC9132QDS 47 bool "Support BSC9132QDS" 48 select ARCH_BSC9132 49 select BOARD_LATE_INIT if CHAIN_OF_TRUST 50 select SUPPORT_SPL 51 select BOARD_EARLY_INIT_F 52 53config TARGET_C29XPCIE 54 bool "Support C29XPCIE" 55 select ARCH_C29X 56 select BOARD_LATE_INIT if CHAIN_OF_TRUST 57 select SUPPORT_SPL 58 select SUPPORT_TPL 59 select PHYS_64BIT 60 61config TARGET_P3041DS 62 bool "Support P3041DS" 63 select PHYS_64BIT 64 select ARCH_P3041 65 select BOARD_LATE_INIT if CHAIN_OF_TRUST 66 67config TARGET_P4080DS 68 bool "Support P4080DS" 69 select PHYS_64BIT 70 select ARCH_P4080 71 select BOARD_LATE_INIT if CHAIN_OF_TRUST 72 73config TARGET_P5020DS 74 bool "Support P5020DS" 75 select PHYS_64BIT 76 select ARCH_P5020 77 select BOARD_LATE_INIT if CHAIN_OF_TRUST 78 79config TARGET_P5040DS 80 bool "Support P5040DS" 81 select PHYS_64BIT 82 select ARCH_P5040 83 select BOARD_LATE_INIT if CHAIN_OF_TRUST 84 85config TARGET_MPC8536DS 86 bool "Support MPC8536DS" 87 select ARCH_MPC8536 88# Use DDR3 controller with DDR2 DIMMs on this board 89 select SYS_FSL_DDRC_GEN3 90 91config TARGET_MPC8541CDS 92 bool "Support MPC8541CDS" 93 select ARCH_MPC8541 94 95config TARGET_MPC8544DS 96 bool "Support MPC8544DS" 97 select ARCH_MPC8544 98 99config TARGET_MPC8548CDS 100 bool "Support MPC8548CDS" 101 select ARCH_MPC8548 102 103config TARGET_MPC8555CDS 104 bool "Support MPC8555CDS" 105 select ARCH_MPC8555 106 107config TARGET_MPC8568MDS 108 bool "Support MPC8568MDS" 109 select ARCH_MPC8568 110 111config TARGET_MPC8569MDS 112 bool "Support MPC8569MDS" 113 select ARCH_MPC8569 114 115config TARGET_MPC8572DS 116 bool "Support MPC8572DS" 117 select ARCH_MPC8572 118# Use DDR3 controller with DDR2 DIMMs on this board 119 select SYS_FSL_DDRC_GEN3 120 121config TARGET_P1010RDB_PA 122 bool "Support P1010RDB_PA" 123 select ARCH_P1010 124 select BOARD_LATE_INIT if CHAIN_OF_TRUST 125 select SUPPORT_SPL 126 select SUPPORT_TPL 127 imply CMD_EEPROM 128 129config TARGET_P1010RDB_PB 130 bool "Support P1010RDB_PB" 131 select ARCH_P1010 132 select BOARD_LATE_INIT if CHAIN_OF_TRUST 133 select SUPPORT_SPL 134 select SUPPORT_TPL 135 imply CMD_EEPROM 136 137config TARGET_P1022DS 138 bool "Support P1022DS" 139 select ARCH_P1022 140 select SUPPORT_SPL 141 select SUPPORT_TPL 142 143config TARGET_P1023RDB 144 bool "Support P1023RDB" 145 select ARCH_P1023 146 imply CMD_EEPROM 147 148config TARGET_P1020MBG 149 bool "Support P1020MBG-PC" 150 select SUPPORT_SPL 151 select SUPPORT_TPL 152 select ARCH_P1020 153 imply CMD_EEPROM 154 155config TARGET_P1020RDB_PC 156 bool "Support P1020RDB-PC" 157 select SUPPORT_SPL 158 select SUPPORT_TPL 159 select ARCH_P1020 160 imply CMD_EEPROM 161 162config TARGET_P1020RDB_PD 163 bool "Support P1020RDB-PD" 164 select SUPPORT_SPL 165 select SUPPORT_TPL 166 select ARCH_P1020 167 imply CMD_EEPROM 168 169config TARGET_P1020UTM 170 bool "Support P1020UTM" 171 select SUPPORT_SPL 172 select SUPPORT_TPL 173 select ARCH_P1020 174 imply CMD_EEPROM 175 176config TARGET_P1021RDB 177 bool "Support P1021RDB" 178 select SUPPORT_SPL 179 select SUPPORT_TPL 180 select ARCH_P1021 181 imply CMD_EEPROM 182 183config TARGET_P1024RDB 184 bool "Support P1024RDB" 185 select SUPPORT_SPL 186 select SUPPORT_TPL 187 select ARCH_P1024 188 imply CMD_EEPROM 189 190config TARGET_P1025RDB 191 bool "Support P1025RDB" 192 select SUPPORT_SPL 193 select SUPPORT_TPL 194 select ARCH_P1025 195 imply CMD_EEPROM 196 197config TARGET_P2020RDB 198 bool "Support P2020RDB-PC" 199 select SUPPORT_SPL 200 select SUPPORT_TPL 201 select ARCH_P2020 202 imply CMD_EEPROM 203 204config TARGET_P1_TWR 205 bool "Support p1_twr" 206 select ARCH_P1025 207 208config TARGET_P2041RDB 209 bool "Support P2041RDB" 210 select ARCH_P2041 211 select BOARD_LATE_INIT if CHAIN_OF_TRUST 212 select PHYS_64BIT 213 214config TARGET_QEMU_PPCE500 215 bool "Support qemu-ppce500" 216 select ARCH_QEMU_E500 217 select PHYS_64BIT 218 219config TARGET_T1024QDS 220 bool "Support T1024QDS" 221 select ARCH_T1024 222 select BOARD_LATE_INIT if CHAIN_OF_TRUST 223 select SUPPORT_SPL 224 select PHYS_64BIT 225 imply CMD_EEPROM 226 227config TARGET_T1023RDB 228 bool "Support T1023RDB" 229 select ARCH_T1023 230 select BOARD_LATE_INIT if CHAIN_OF_TRUST 231 select SUPPORT_SPL 232 select PHYS_64BIT 233 imply CMD_EEPROM 234 235config TARGET_T1024RDB 236 bool "Support T1024RDB" 237 select ARCH_T1024 238 select BOARD_LATE_INIT if CHAIN_OF_TRUST 239 select SUPPORT_SPL 240 select PHYS_64BIT 241 imply CMD_EEPROM 242 243config TARGET_T1040QDS 244 bool "Support T1040QDS" 245 select ARCH_T1040 246 select BOARD_LATE_INIT if CHAIN_OF_TRUST 247 select PHYS_64BIT 248 imply CMD_EEPROM 249 250config TARGET_T1040RDB 251 bool "Support T1040RDB" 252 select ARCH_T1040 253 select BOARD_LATE_INIT if CHAIN_OF_TRUST 254 select SUPPORT_SPL 255 select PHYS_64BIT 256 257config TARGET_T1040D4RDB 258 bool "Support T1040D4RDB" 259 select ARCH_T1040 260 select BOARD_LATE_INIT if CHAIN_OF_TRUST 261 select SUPPORT_SPL 262 select PHYS_64BIT 263 264config TARGET_T1042RDB 265 bool "Support T1042RDB" 266 select ARCH_T1042 267 select BOARD_LATE_INIT if CHAIN_OF_TRUST 268 select SUPPORT_SPL 269 select PHYS_64BIT 270 271config TARGET_T1042D4RDB 272 bool "Support T1042D4RDB" 273 select ARCH_T1042 274 select BOARD_LATE_INIT if CHAIN_OF_TRUST 275 select SUPPORT_SPL 276 select PHYS_64BIT 277 278config TARGET_T1042RDB_PI 279 bool "Support T1042RDB_PI" 280 select ARCH_T1042 281 select BOARD_LATE_INIT if CHAIN_OF_TRUST 282 select SUPPORT_SPL 283 select PHYS_64BIT 284 285config TARGET_T2080QDS 286 bool "Support T2080QDS" 287 select ARCH_T2080 288 select BOARD_LATE_INIT if CHAIN_OF_TRUST 289 select SUPPORT_SPL 290 select PHYS_64BIT 291 292config TARGET_T2080RDB 293 bool "Support T2080RDB" 294 select ARCH_T2080 295 select BOARD_LATE_INIT if CHAIN_OF_TRUST 296 select SUPPORT_SPL 297 select PHYS_64BIT 298 299config TARGET_T2081QDS 300 bool "Support T2081QDS" 301 select ARCH_T2081 302 select SUPPORT_SPL 303 select PHYS_64BIT 304 305config TARGET_T4160QDS 306 bool "Support T4160QDS" 307 select ARCH_T4160 308 select BOARD_LATE_INIT if CHAIN_OF_TRUST 309 select SUPPORT_SPL 310 select PHYS_64BIT 311 312config TARGET_T4160RDB 313 bool "Support T4160RDB" 314 select ARCH_T4160 315 select SUPPORT_SPL 316 select PHYS_64BIT 317 318config TARGET_T4240QDS 319 bool "Support T4240QDS" 320 select ARCH_T4240 321 select BOARD_LATE_INIT if CHAIN_OF_TRUST 322 select SUPPORT_SPL 323 select PHYS_64BIT 324 325config TARGET_T4240RDB 326 bool "Support T4240RDB" 327 select ARCH_T4240 328 select SUPPORT_SPL 329 select PHYS_64BIT 330 331config TARGET_CONTROLCENTERD 332 bool "Support controlcenterd" 333 select ARCH_P1022 334 335config TARGET_KMP204X 336 bool "Support kmp204x" 337 select ARCH_P2041 338 select PHYS_64BIT 339 imply CMD_CRAMFS 340 imply FS_CRAMFS 341 342config TARGET_XPEDITE520X 343 bool "Support xpedite520x" 344 select ARCH_MPC8548 345 346config TARGET_XPEDITE537X 347 bool "Support xpedite537x" 348 select ARCH_MPC8572 349# Use DDR3 controller with DDR2 DIMMs on this board 350 select SYS_FSL_DDRC_GEN3 351 352config TARGET_XPEDITE550X 353 bool "Support xpedite550x" 354 select ARCH_P2020 355 356config TARGET_UCP1020 357 bool "Support uCP1020" 358 select ARCH_P1020 359 360config TARGET_CYRUS_P5020 361 bool "Support Varisys Cyrus P5020" 362 select ARCH_P5020 363 select PHYS_64BIT 364 365config TARGET_CYRUS_P5040 366 bool "Support Varisys Cyrus P5040" 367 select ARCH_P5040 368 select PHYS_64BIT 369 370endchoice 371 372config ARCH_B4420 373 bool 374 select E500MC 375 select E6500 376 select FSL_LAW 377 select SYS_FSL_DDR_VER_47 378 select SYS_FSL_ERRATUM_A004477 379 select SYS_FSL_ERRATUM_A005871 380 select SYS_FSL_ERRATUM_A006379 381 select SYS_FSL_ERRATUM_A006384 382 select SYS_FSL_ERRATUM_A006475 383 select SYS_FSL_ERRATUM_A006593 384 select SYS_FSL_ERRATUM_A007075 385 select SYS_FSL_ERRATUM_A007186 386 select SYS_FSL_ERRATUM_A007212 387 select SYS_FSL_ERRATUM_A009942 388 select SYS_FSL_HAS_DDR3 389 select SYS_FSL_HAS_SEC 390 select SYS_FSL_QORIQ_CHASSIS2 391 select SYS_FSL_SEC_BE 392 select SYS_FSL_SEC_COMPAT_4 393 select SYS_PPC64 394 select FSL_IFC 395 imply CMD_EEPROM 396 397config ARCH_B4860 398 bool 399 select E500MC 400 select E6500 401 select FSL_LAW 402 select SYS_FSL_DDR_VER_47 403 select SYS_FSL_ERRATUM_A004477 404 select SYS_FSL_ERRATUM_A005871 405 select SYS_FSL_ERRATUM_A006379 406 select SYS_FSL_ERRATUM_A006384 407 select SYS_FSL_ERRATUM_A006475 408 select SYS_FSL_ERRATUM_A006593 409 select SYS_FSL_ERRATUM_A007075 410 select SYS_FSL_ERRATUM_A007186 411 select SYS_FSL_ERRATUM_A007212 412 select SYS_FSL_ERRATUM_A007907 413 select SYS_FSL_ERRATUM_A009942 414 select SYS_FSL_HAS_DDR3 415 select SYS_FSL_HAS_SEC 416 select SYS_FSL_QORIQ_CHASSIS2 417 select SYS_FSL_SEC_BE 418 select SYS_FSL_SEC_COMPAT_4 419 select SYS_PPC64 420 select FSL_IFC 421 imply CMD_EEPROM 422 423config ARCH_BSC9131 424 bool 425 select FSL_LAW 426 select SYS_FSL_DDR_VER_44 427 select SYS_FSL_ERRATUM_A004477 428 select SYS_FSL_ERRATUM_A005125 429 select SYS_FSL_ERRATUM_ESDHC111 430 select SYS_FSL_HAS_DDR3 431 select SYS_FSL_HAS_SEC 432 select SYS_FSL_SEC_BE 433 select SYS_FSL_SEC_COMPAT_4 434 select FSL_IFC 435 imply CMD_EEPROM 436 437config ARCH_BSC9132 438 bool 439 select FSL_LAW 440 select SYS_FSL_DDR_VER_46 441 select SYS_FSL_ERRATUM_A004477 442 select SYS_FSL_ERRATUM_A005125 443 select SYS_FSL_ERRATUM_A005434 444 select SYS_FSL_ERRATUM_ESDHC111 445 select SYS_FSL_ERRATUM_I2C_A004447 446 select SYS_FSL_ERRATUM_IFC_A002769 447 select SYS_FSL_HAS_DDR3 448 select SYS_FSL_HAS_SEC 449 select SYS_FSL_SEC_BE 450 select SYS_FSL_SEC_COMPAT_4 451 select SYS_PPC_E500_USE_DEBUG_TLB 452 select FSL_IFC 453 imply CMD_EEPROM 454 455config ARCH_C29X 456 bool 457 select FSL_LAW 458 select SYS_FSL_DDR_VER_46 459 select SYS_FSL_ERRATUM_A005125 460 select SYS_FSL_ERRATUM_ESDHC111 461 select SYS_FSL_HAS_DDR3 462 select SYS_FSL_HAS_SEC 463 select SYS_FSL_SEC_BE 464 select SYS_FSL_SEC_COMPAT_6 465 select SYS_PPC_E500_USE_DEBUG_TLB 466 select FSL_IFC 467 468config ARCH_MPC8536 469 bool 470 select FSL_LAW 471 select SYS_FSL_ERRATUM_A004508 472 select SYS_FSL_ERRATUM_A005125 473 select SYS_FSL_HAS_DDR2 474 select SYS_FSL_HAS_DDR3 475 select SYS_FSL_HAS_SEC 476 select SYS_FSL_SEC_BE 477 select SYS_FSL_SEC_COMPAT_2 478 select SYS_PPC_E500_USE_DEBUG_TLB 479 select FSL_ELBC 480 481config ARCH_MPC8540 482 bool 483 select FSL_LAW 484 select SYS_FSL_HAS_DDR1 485 486config ARCH_MPC8541 487 bool 488 select FSL_LAW 489 select SYS_FSL_HAS_DDR1 490 select SYS_FSL_HAS_SEC 491 select SYS_FSL_SEC_BE 492 select SYS_FSL_SEC_COMPAT_2 493 494config ARCH_MPC8544 495 bool 496 select FSL_LAW 497 select SYS_FSL_ERRATUM_A005125 498 select SYS_FSL_HAS_DDR2 499 select SYS_FSL_HAS_SEC 500 select SYS_FSL_SEC_BE 501 select SYS_FSL_SEC_COMPAT_2 502 select SYS_PPC_E500_USE_DEBUG_TLB 503 select FSL_ELBC 504 505config ARCH_MPC8548 506 bool 507 select FSL_LAW 508 select SYS_FSL_ERRATUM_A005125 509 select SYS_FSL_ERRATUM_NMG_DDR120 510 select SYS_FSL_ERRATUM_NMG_LBC103 511 select SYS_FSL_ERRATUM_NMG_ETSEC129 512 select SYS_FSL_ERRATUM_I2C_A004447 513 select SYS_FSL_HAS_DDR2 514 select SYS_FSL_HAS_DDR1 515 select SYS_FSL_HAS_SEC 516 select SYS_FSL_SEC_BE 517 select SYS_FSL_SEC_COMPAT_2 518 select SYS_PPC_E500_USE_DEBUG_TLB 519 520config ARCH_MPC8555 521 bool 522 select FSL_LAW 523 select SYS_FSL_HAS_DDR1 524 select SYS_FSL_HAS_SEC 525 select SYS_FSL_SEC_BE 526 select SYS_FSL_SEC_COMPAT_2 527 528config ARCH_MPC8560 529 bool 530 select FSL_LAW 531 select SYS_FSL_HAS_DDR1 532 533config ARCH_MPC8568 534 bool 535 select FSL_LAW 536 select SYS_FSL_HAS_DDR2 537 select SYS_FSL_HAS_SEC 538 select SYS_FSL_SEC_BE 539 select SYS_FSL_SEC_COMPAT_2 540 541config ARCH_MPC8569 542 bool 543 select FSL_LAW 544 select SYS_FSL_ERRATUM_A004508 545 select SYS_FSL_ERRATUM_A005125 546 select SYS_FSL_HAS_DDR3 547 select SYS_FSL_HAS_SEC 548 select SYS_FSL_SEC_BE 549 select SYS_FSL_SEC_COMPAT_2 550 select FSL_ELBC 551 552config ARCH_MPC8572 553 bool 554 select FSL_LAW 555 select SYS_FSL_ERRATUM_A004508 556 select SYS_FSL_ERRATUM_A005125 557 select SYS_FSL_ERRATUM_DDR_115 558 select SYS_FSL_ERRATUM_DDR111_DDR134 559 select SYS_FSL_HAS_DDR2 560 select SYS_FSL_HAS_DDR3 561 select SYS_FSL_HAS_SEC 562 select SYS_FSL_SEC_BE 563 select SYS_FSL_SEC_COMPAT_2 564 select SYS_PPC_E500_USE_DEBUG_TLB 565 select FSL_ELBC 566 567config ARCH_P1010 568 bool 569 select FSL_LAW 570 select SYS_FSL_ERRATUM_A004477 571 select SYS_FSL_ERRATUM_A004508 572 select SYS_FSL_ERRATUM_A005125 573 select SYS_FSL_ERRATUM_A006261 574 select SYS_FSL_ERRATUM_A007075 575 select SYS_FSL_ERRATUM_ESDHC111 576 select SYS_FSL_ERRATUM_I2C_A004447 577 select SYS_FSL_ERRATUM_IFC_A002769 578 select SYS_FSL_ERRATUM_P1010_A003549 579 select SYS_FSL_ERRATUM_SEC_A003571 580 select SYS_FSL_ERRATUM_IFC_A003399 581 select SYS_FSL_HAS_DDR3 582 select SYS_FSL_HAS_SEC 583 select SYS_FSL_SEC_BE 584 select SYS_FSL_SEC_COMPAT_4 585 select SYS_PPC_E500_USE_DEBUG_TLB 586 select FSL_IFC 587 imply CMD_EEPROM 588 589config ARCH_P1011 590 bool 591 select FSL_LAW 592 select SYS_FSL_ERRATUM_A004508 593 select SYS_FSL_ERRATUM_A005125 594 select SYS_FSL_ERRATUM_ELBC_A001 595 select SYS_FSL_ERRATUM_ESDHC111 596 select SYS_FSL_HAS_DDR3 597 select SYS_FSL_HAS_SEC 598 select SYS_FSL_SEC_BE 599 select SYS_FSL_SEC_COMPAT_2 600 select SYS_PPC_E500_USE_DEBUG_TLB 601 select FSL_ELBC 602 603config ARCH_P1020 604 bool 605 select FSL_LAW 606 select SYS_FSL_ERRATUM_A004508 607 select SYS_FSL_ERRATUM_A005125 608 select SYS_FSL_ERRATUM_ELBC_A001 609 select SYS_FSL_ERRATUM_ESDHC111 610 select SYS_FSL_HAS_DDR3 611 select SYS_FSL_HAS_SEC 612 select SYS_FSL_SEC_BE 613 select SYS_FSL_SEC_COMPAT_2 614 select SYS_PPC_E500_USE_DEBUG_TLB 615 select FSL_ELBC 616 617config ARCH_P1021 618 bool 619 select FSL_LAW 620 select SYS_FSL_ERRATUM_A004508 621 select SYS_FSL_ERRATUM_A005125 622 select SYS_FSL_ERRATUM_ELBC_A001 623 select SYS_FSL_ERRATUM_ESDHC111 624 select SYS_FSL_HAS_DDR3 625 select SYS_FSL_HAS_SEC 626 select SYS_FSL_SEC_BE 627 select SYS_FSL_SEC_COMPAT_2 628 select SYS_PPC_E500_USE_DEBUG_TLB 629 select FSL_ELBC 630 631config ARCH_P1022 632 bool 633 select FSL_LAW 634 select SYS_FSL_ERRATUM_A004477 635 select SYS_FSL_ERRATUM_A004508 636 select SYS_FSL_ERRATUM_A005125 637 select SYS_FSL_ERRATUM_ELBC_A001 638 select SYS_FSL_ERRATUM_ESDHC111 639 select SYS_FSL_ERRATUM_SATA_A001 640 select SYS_FSL_HAS_DDR3 641 select SYS_FSL_HAS_SEC 642 select SYS_FSL_SEC_BE 643 select SYS_FSL_SEC_COMPAT_2 644 select SYS_PPC_E500_USE_DEBUG_TLB 645 select FSL_ELBC 646 647config ARCH_P1023 648 bool 649 select FSL_LAW 650 select SYS_FSL_ERRATUM_A004508 651 select SYS_FSL_ERRATUM_A005125 652 select SYS_FSL_ERRATUM_I2C_A004447 653 select SYS_FSL_HAS_DDR3 654 select SYS_FSL_HAS_SEC 655 select SYS_FSL_SEC_BE 656 select SYS_FSL_SEC_COMPAT_4 657 select FSL_ELBC 658 659config ARCH_P1024 660 bool 661 select FSL_LAW 662 select SYS_FSL_ERRATUM_A004508 663 select SYS_FSL_ERRATUM_A005125 664 select SYS_FSL_ERRATUM_ELBC_A001 665 select SYS_FSL_ERRATUM_ESDHC111 666 select SYS_FSL_HAS_DDR3 667 select SYS_FSL_HAS_SEC 668 select SYS_FSL_SEC_BE 669 select SYS_FSL_SEC_COMPAT_2 670 select SYS_PPC_E500_USE_DEBUG_TLB 671 select FSL_ELBC 672 imply CMD_EEPROM 673 674config ARCH_P1025 675 bool 676 select FSL_LAW 677 select SYS_FSL_ERRATUM_A004508 678 select SYS_FSL_ERRATUM_A005125 679 select SYS_FSL_ERRATUM_ELBC_A001 680 select SYS_FSL_ERRATUM_ESDHC111 681 select SYS_FSL_HAS_DDR3 682 select SYS_FSL_HAS_SEC 683 select SYS_FSL_SEC_BE 684 select SYS_FSL_SEC_COMPAT_2 685 select SYS_PPC_E500_USE_DEBUG_TLB 686 select FSL_ELBC 687 688config ARCH_P2020 689 bool 690 select FSL_LAW 691 select SYS_FSL_ERRATUM_A004477 692 select SYS_FSL_ERRATUM_A004508 693 select SYS_FSL_ERRATUM_A005125 694 select SYS_FSL_ERRATUM_ESDHC111 695 select SYS_FSL_ERRATUM_ESDHC_A001 696 select SYS_FSL_HAS_DDR3 697 select SYS_FSL_HAS_SEC 698 select SYS_FSL_SEC_BE 699 select SYS_FSL_SEC_COMPAT_2 700 select SYS_PPC_E500_USE_DEBUG_TLB 701 select FSL_ELBC 702 imply CMD_EEPROM 703 704config ARCH_P2041 705 bool 706 select E500MC 707 select FSL_LAW 708 select SYS_FSL_ERRATUM_A004510 709 select SYS_FSL_ERRATUM_A004849 710 select SYS_FSL_ERRATUM_A006261 711 select SYS_FSL_ERRATUM_CPU_A003999 712 select SYS_FSL_ERRATUM_DDR_A003 713 select SYS_FSL_ERRATUM_DDR_A003474 714 select SYS_FSL_ERRATUM_ESDHC111 715 select SYS_FSL_ERRATUM_I2C_A004447 716 select SYS_FSL_ERRATUM_NMG_CPU_A011 717 select SYS_FSL_ERRATUM_SRIO_A004034 718 select SYS_FSL_ERRATUM_USB14 719 select SYS_FSL_HAS_DDR3 720 select SYS_FSL_HAS_SEC 721 select SYS_FSL_QORIQ_CHASSIS1 722 select SYS_FSL_SEC_BE 723 select SYS_FSL_SEC_COMPAT_4 724 select FSL_ELBC 725 726config ARCH_P3041 727 bool 728 select E500MC 729 select FSL_LAW 730 select SYS_FSL_DDR_VER_44 731 select SYS_FSL_ERRATUM_A004510 732 select SYS_FSL_ERRATUM_A004849 733 select SYS_FSL_ERRATUM_A005812 734 select SYS_FSL_ERRATUM_A006261 735 select SYS_FSL_ERRATUM_CPU_A003999 736 select SYS_FSL_ERRATUM_DDR_A003 737 select SYS_FSL_ERRATUM_DDR_A003474 738 select SYS_FSL_ERRATUM_ESDHC111 739 select SYS_FSL_ERRATUM_I2C_A004447 740 select SYS_FSL_ERRATUM_NMG_CPU_A011 741 select SYS_FSL_ERRATUM_SRIO_A004034 742 select SYS_FSL_ERRATUM_USB14 743 select SYS_FSL_HAS_DDR3 744 select SYS_FSL_HAS_SEC 745 select SYS_FSL_QORIQ_CHASSIS1 746 select SYS_FSL_SEC_BE 747 select SYS_FSL_SEC_COMPAT_4 748 select FSL_ELBC 749 750config ARCH_P4080 751 bool 752 select E500MC 753 select FSL_LAW 754 select SYS_FSL_DDR_VER_44 755 select SYS_FSL_ERRATUM_A004510 756 select SYS_FSL_ERRATUM_A004580 757 select SYS_FSL_ERRATUM_A004849 758 select SYS_FSL_ERRATUM_A005812 759 select SYS_FSL_ERRATUM_A007075 760 select SYS_FSL_ERRATUM_CPC_A002 761 select SYS_FSL_ERRATUM_CPC_A003 762 select SYS_FSL_ERRATUM_CPU_A003999 763 select SYS_FSL_ERRATUM_DDR_A003 764 select SYS_FSL_ERRATUM_DDR_A003474 765 select SYS_FSL_ERRATUM_ELBC_A001 766 select SYS_FSL_ERRATUM_ESDHC111 767 select SYS_FSL_ERRATUM_ESDHC13 768 select SYS_FSL_ERRATUM_ESDHC135 769 select SYS_FSL_ERRATUM_I2C_A004447 770 select SYS_FSL_ERRATUM_NMG_CPU_A011 771 select SYS_FSL_ERRATUM_SRIO_A004034 772 select SYS_P4080_ERRATUM_CPU22 773 select SYS_P4080_ERRATUM_PCIE_A003 774 select SYS_P4080_ERRATUM_SERDES8 775 select SYS_P4080_ERRATUM_SERDES9 776 select SYS_P4080_ERRATUM_SERDES_A001 777 select SYS_P4080_ERRATUM_SERDES_A005 778 select SYS_FSL_HAS_DDR3 779 select SYS_FSL_HAS_SEC 780 select SYS_FSL_QORIQ_CHASSIS1 781 select SYS_FSL_SEC_BE 782 select SYS_FSL_SEC_COMPAT_4 783 select FSL_ELBC 784 785config ARCH_P5020 786 bool 787 select E500MC 788 select FSL_LAW 789 select SYS_FSL_DDR_VER_44 790 select SYS_FSL_ERRATUM_A004510 791 select SYS_FSL_ERRATUM_A006261 792 select SYS_FSL_ERRATUM_DDR_A003 793 select SYS_FSL_ERRATUM_DDR_A003474 794 select SYS_FSL_ERRATUM_ESDHC111 795 select SYS_FSL_ERRATUM_I2C_A004447 796 select SYS_FSL_ERRATUM_SRIO_A004034 797 select SYS_FSL_ERRATUM_USB14 798 select SYS_FSL_HAS_DDR3 799 select SYS_FSL_HAS_SEC 800 select SYS_FSL_QORIQ_CHASSIS1 801 select SYS_FSL_SEC_BE 802 select SYS_FSL_SEC_COMPAT_4 803 select SYS_PPC64 804 select FSL_ELBC 805 806config ARCH_P5040 807 bool 808 select E500MC 809 select FSL_LAW 810 select SYS_FSL_DDR_VER_44 811 select SYS_FSL_ERRATUM_A004510 812 select SYS_FSL_ERRATUM_A004699 813 select SYS_FSL_ERRATUM_A005812 814 select SYS_FSL_ERRATUM_A006261 815 select SYS_FSL_ERRATUM_DDR_A003 816 select SYS_FSL_ERRATUM_DDR_A003474 817 select SYS_FSL_ERRATUM_ESDHC111 818 select SYS_FSL_ERRATUM_USB14 819 select SYS_FSL_HAS_DDR3 820 select SYS_FSL_HAS_SEC 821 select SYS_FSL_QORIQ_CHASSIS1 822 select SYS_FSL_SEC_BE 823 select SYS_FSL_SEC_COMPAT_4 824 select SYS_PPC64 825 select FSL_ELBC 826 827config ARCH_QEMU_E500 828 bool 829 830config ARCH_T1023 831 bool 832 select E500MC 833 select FSL_LAW 834 select SYS_FSL_DDR_VER_50 835 select SYS_FSL_ERRATUM_A008378 836 select SYS_FSL_ERRATUM_A009663 837 select SYS_FSL_ERRATUM_A009942 838 select SYS_FSL_ERRATUM_ESDHC111 839 select SYS_FSL_HAS_DDR3 840 select SYS_FSL_HAS_DDR4 841 select SYS_FSL_HAS_SEC 842 select SYS_FSL_QORIQ_CHASSIS2 843 select SYS_FSL_SEC_BE 844 select SYS_FSL_SEC_COMPAT_5 845 select FSL_IFC 846 imply CMD_EEPROM 847 848config ARCH_T1024 849 bool 850 select E500MC 851 select FSL_LAW 852 select SYS_FSL_DDR_VER_50 853 select SYS_FSL_ERRATUM_A008378 854 select SYS_FSL_ERRATUM_A009663 855 select SYS_FSL_ERRATUM_A009942 856 select SYS_FSL_ERRATUM_ESDHC111 857 select SYS_FSL_HAS_DDR3 858 select SYS_FSL_HAS_DDR4 859 select SYS_FSL_HAS_SEC 860 select SYS_FSL_QORIQ_CHASSIS2 861 select SYS_FSL_SEC_BE 862 select SYS_FSL_SEC_COMPAT_5 863 select FSL_IFC 864 imply CMD_EEPROM 865 866config ARCH_T1040 867 bool 868 select E500MC 869 select FSL_LAW 870 select SYS_FSL_DDR_VER_50 871 select SYS_FSL_ERRATUM_A008044 872 select SYS_FSL_ERRATUM_A008378 873 select SYS_FSL_ERRATUM_A009663 874 select SYS_FSL_ERRATUM_A009942 875 select SYS_FSL_ERRATUM_ESDHC111 876 select SYS_FSL_HAS_DDR3 877 select SYS_FSL_HAS_DDR4 878 select SYS_FSL_HAS_SEC 879 select SYS_FSL_QORIQ_CHASSIS2 880 select SYS_FSL_SEC_BE 881 select SYS_FSL_SEC_COMPAT_5 882 select FSL_IFC 883 884config ARCH_T1042 885 bool 886 select E500MC 887 select FSL_LAW 888 select SYS_FSL_DDR_VER_50 889 select SYS_FSL_ERRATUM_A008044 890 select SYS_FSL_ERRATUM_A008378 891 select SYS_FSL_ERRATUM_A009663 892 select SYS_FSL_ERRATUM_A009942 893 select SYS_FSL_ERRATUM_ESDHC111 894 select SYS_FSL_HAS_DDR3 895 select SYS_FSL_HAS_DDR4 896 select SYS_FSL_HAS_SEC 897 select SYS_FSL_QORIQ_CHASSIS2 898 select SYS_FSL_SEC_BE 899 select SYS_FSL_SEC_COMPAT_5 900 select FSL_IFC 901 902config ARCH_T2080 903 bool 904 select E500MC 905 select E6500 906 select FSL_LAW 907 select SYS_FSL_DDR_VER_47 908 select SYS_FSL_ERRATUM_A006379 909 select SYS_FSL_ERRATUM_A006593 910 select SYS_FSL_ERRATUM_A007186 911 select SYS_FSL_ERRATUM_A007212 912 select SYS_FSL_ERRATUM_A007815 913 select SYS_FSL_ERRATUM_A007907 914 select SYS_FSL_ERRATUM_A009942 915 select SYS_FSL_ERRATUM_ESDHC111 916 select SYS_FSL_HAS_DDR3 917 select SYS_FSL_HAS_SEC 918 select SYS_FSL_QORIQ_CHASSIS2 919 select SYS_FSL_SEC_BE 920 select SYS_FSL_SEC_COMPAT_4 921 select SYS_PPC64 922 select FSL_IFC 923 924config ARCH_T2081 925 bool 926 select E500MC 927 select E6500 928 select FSL_LAW 929 select SYS_FSL_DDR_VER_47 930 select SYS_FSL_ERRATUM_A006379 931 select SYS_FSL_ERRATUM_A006593 932 select SYS_FSL_ERRATUM_A007186 933 select SYS_FSL_ERRATUM_A007212 934 select SYS_FSL_ERRATUM_A009942 935 select SYS_FSL_ERRATUM_ESDHC111 936 select SYS_FSL_HAS_DDR3 937 select SYS_FSL_HAS_SEC 938 select SYS_FSL_QORIQ_CHASSIS2 939 select SYS_FSL_SEC_BE 940 select SYS_FSL_SEC_COMPAT_4 941 select SYS_PPC64 942 select FSL_IFC 943 944config ARCH_T4160 945 bool 946 select E500MC 947 select E6500 948 select FSL_LAW 949 select SYS_FSL_DDR_VER_47 950 select SYS_FSL_ERRATUM_A004468 951 select SYS_FSL_ERRATUM_A005871 952 select SYS_FSL_ERRATUM_A006379 953 select SYS_FSL_ERRATUM_A006593 954 select SYS_FSL_ERRATUM_A007186 955 select SYS_FSL_ERRATUM_A007798 956 select SYS_FSL_ERRATUM_A009942 957 select SYS_FSL_HAS_DDR3 958 select SYS_FSL_HAS_SEC 959 select SYS_FSL_QORIQ_CHASSIS2 960 select SYS_FSL_SEC_BE 961 select SYS_FSL_SEC_COMPAT_4 962 select SYS_PPC64 963 select FSL_IFC 964 965config ARCH_T4240 966 bool 967 select E500MC 968 select E6500 969 select FSL_LAW 970 select SYS_FSL_DDR_VER_47 971 select SYS_FSL_ERRATUM_A004468 972 select SYS_FSL_ERRATUM_A005871 973 select SYS_FSL_ERRATUM_A006261 974 select SYS_FSL_ERRATUM_A006379 975 select SYS_FSL_ERRATUM_A006593 976 select SYS_FSL_ERRATUM_A007186 977 select SYS_FSL_ERRATUM_A007798 978 select SYS_FSL_ERRATUM_A007815 979 select SYS_FSL_ERRATUM_A007907 980 select SYS_FSL_ERRATUM_A009942 981 select SYS_FSL_HAS_DDR3 982 select SYS_FSL_HAS_SEC 983 select SYS_FSL_QORIQ_CHASSIS2 984 select SYS_FSL_SEC_BE 985 select SYS_FSL_SEC_COMPAT_4 986 select SYS_PPC64 987 select FSL_IFC 988 989config BOOKE 990 bool 991 default y 992 993config E500 994 bool 995 default y 996 help 997 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 998 999config E500MC 1000 bool 1001 help 1002 Enble PowerPC E500MC core 1003 1004config E6500 1005 bool 1006 help 1007 Enable PowerPC E6500 core 1008 1009config FSL_LAW 1010 bool 1011 help 1012 Use Freescale common code for Local Access Window 1013 1014config SECURE_BOOT 1015 bool "Secure Boot" 1016 help 1017 Enable Freescale Secure Boot feature. Normally selected 1018 by defconfig. If unsure, do not change. 1019 1020config MAX_CPUS 1021 int "Maximum number of CPUs permitted for MPC85xx" 1022 default 12 if ARCH_T4240 1023 default 8 if ARCH_P4080 || \ 1024 ARCH_T4160 1025 default 4 if ARCH_B4860 || \ 1026 ARCH_P2041 || \ 1027 ARCH_P3041 || \ 1028 ARCH_P5040 || \ 1029 ARCH_T1040 || \ 1030 ARCH_T1042 || \ 1031 ARCH_T2080 || \ 1032 ARCH_T2081 1033 default 2 if ARCH_B4420 || \ 1034 ARCH_BSC9132 || \ 1035 ARCH_MPC8572 || \ 1036 ARCH_P1020 || \ 1037 ARCH_P1021 || \ 1038 ARCH_P1022 || \ 1039 ARCH_P1023 || \ 1040 ARCH_P1024 || \ 1041 ARCH_P1025 || \ 1042 ARCH_P2020 || \ 1043 ARCH_P5020 || \ 1044 ARCH_T1023 || \ 1045 ARCH_T1024 1046 default 1 1047 help 1048 Set this number to the maximum number of possible CPUs in the SoC. 1049 SoCs may have multiple clusters with each cluster may have multiple 1050 ports. If some ports are reserved but higher ports are used for 1051 cores, count the reserved ports. This will allocate enough memory 1052 in spin table to properly handle all cores. 1053 1054config SYS_CCSRBAR_DEFAULT 1055 hex "Default CCSRBAR address" 1056 default 0xff700000 if ARCH_BSC9131 || \ 1057 ARCH_BSC9132 || \ 1058 ARCH_C29X || \ 1059 ARCH_MPC8536 || \ 1060 ARCH_MPC8540 || \ 1061 ARCH_MPC8541 || \ 1062 ARCH_MPC8544 || \ 1063 ARCH_MPC8548 || \ 1064 ARCH_MPC8555 || \ 1065 ARCH_MPC8560 || \ 1066 ARCH_MPC8568 || \ 1067 ARCH_MPC8569 || \ 1068 ARCH_MPC8572 || \ 1069 ARCH_P1010 || \ 1070 ARCH_P1011 || \ 1071 ARCH_P1020 || \ 1072 ARCH_P1021 || \ 1073 ARCH_P1022 || \ 1074 ARCH_P1024 || \ 1075 ARCH_P1025 || \ 1076 ARCH_P2020 1077 default 0xff600000 if ARCH_P1023 1078 default 0xfe000000 if ARCH_B4420 || \ 1079 ARCH_B4860 || \ 1080 ARCH_P2041 || \ 1081 ARCH_P3041 || \ 1082 ARCH_P4080 || \ 1083 ARCH_P5020 || \ 1084 ARCH_P5040 || \ 1085 ARCH_T1023 || \ 1086 ARCH_T1024 || \ 1087 ARCH_T1040 || \ 1088 ARCH_T1042 || \ 1089 ARCH_T2080 || \ 1090 ARCH_T2081 || \ 1091 ARCH_T4160 || \ 1092 ARCH_T4240 1093 default 0xe0000000 if ARCH_QEMU_E500 1094 help 1095 Default value of CCSRBAR comes from power-on-reset. It 1096 is fixed on each SoC. Some SoCs can have different value 1097 if changed by pre-boot regime. The value here must match 1098 the current value in SoC. If not sure, do not change. 1099 1100config SYS_FSL_ERRATUM_A004468 1101 bool 1102 1103config SYS_FSL_ERRATUM_A004477 1104 bool 1105 1106config SYS_FSL_ERRATUM_A004508 1107 bool 1108 1109config SYS_FSL_ERRATUM_A004580 1110 bool 1111 1112config SYS_FSL_ERRATUM_A004699 1113 bool 1114 1115config SYS_FSL_ERRATUM_A004849 1116 bool 1117 1118config SYS_FSL_ERRATUM_A004510 1119 bool 1120 1121config SYS_FSL_ERRATUM_A004510_SVR_REV 1122 hex 1123 depends on SYS_FSL_ERRATUM_A004510 1124 default 0x20 if ARCH_P4080 1125 default 0x10 1126 1127config SYS_FSL_ERRATUM_A004510_SVR_REV2 1128 hex 1129 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1130 default 0x11 1131 1132config SYS_FSL_ERRATUM_A005125 1133 bool 1134 1135config SYS_FSL_ERRATUM_A005434 1136 bool 1137 1138config SYS_FSL_ERRATUM_A005812 1139 bool 1140 1141config SYS_FSL_ERRATUM_A005871 1142 bool 1143 1144config SYS_FSL_ERRATUM_A006261 1145 bool 1146 1147config SYS_FSL_ERRATUM_A006379 1148 bool 1149 1150config SYS_FSL_ERRATUM_A006384 1151 bool 1152 1153config SYS_FSL_ERRATUM_A006475 1154 bool 1155 1156config SYS_FSL_ERRATUM_A006593 1157 bool 1158 1159config SYS_FSL_ERRATUM_A007075 1160 bool 1161 1162config SYS_FSL_ERRATUM_A007186 1163 bool 1164 1165config SYS_FSL_ERRATUM_A007212 1166 bool 1167 1168config SYS_FSL_ERRATUM_A007815 1169 bool 1170 1171config SYS_FSL_ERRATUM_A007798 1172 bool 1173 1174config SYS_FSL_ERRATUM_A007907 1175 bool 1176 1177config SYS_FSL_ERRATUM_A008044 1178 bool 1179 1180config SYS_FSL_ERRATUM_CPC_A002 1181 bool 1182 1183config SYS_FSL_ERRATUM_CPC_A003 1184 bool 1185 1186config SYS_FSL_ERRATUM_CPU_A003999 1187 bool 1188 1189config SYS_FSL_ERRATUM_ELBC_A001 1190 bool 1191 1192config SYS_FSL_ERRATUM_I2C_A004447 1193 bool 1194 1195config SYS_FSL_A004447_SVR_REV 1196 hex 1197 depends on SYS_FSL_ERRATUM_I2C_A004447 1198 default 0x00 if ARCH_MPC8548 1199 default 0x10 if ARCH_P1010 1200 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1201 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1202 1203config SYS_FSL_ERRATUM_IFC_A002769 1204 bool 1205 1206config SYS_FSL_ERRATUM_IFC_A003399 1207 bool 1208 1209config SYS_FSL_ERRATUM_NMG_CPU_A011 1210 bool 1211 1212config SYS_FSL_ERRATUM_NMG_ETSEC129 1213 bool 1214 1215config SYS_FSL_ERRATUM_NMG_LBC103 1216 bool 1217 1218config SYS_FSL_ERRATUM_P1010_A003549 1219 bool 1220 1221config SYS_FSL_ERRATUM_SATA_A001 1222 bool 1223 1224config SYS_FSL_ERRATUM_SEC_A003571 1225 bool 1226 1227config SYS_FSL_ERRATUM_SRIO_A004034 1228 bool 1229 1230config SYS_FSL_ERRATUM_USB14 1231 bool 1232 1233config SYS_P4080_ERRATUM_CPU22 1234 bool 1235 1236config SYS_P4080_ERRATUM_PCIE_A003 1237 bool 1238 1239config SYS_P4080_ERRATUM_SERDES8 1240 bool 1241 1242config SYS_P4080_ERRATUM_SERDES9 1243 bool 1244 1245config SYS_P4080_ERRATUM_SERDES_A001 1246 bool 1247 1248config SYS_P4080_ERRATUM_SERDES_A005 1249 bool 1250 1251config SYS_FSL_QORIQ_CHASSIS1 1252 bool 1253 1254config SYS_FSL_QORIQ_CHASSIS2 1255 bool 1256 1257config SYS_FSL_NUM_LAWS 1258 int "Number of local access windows" 1259 depends on FSL_LAW 1260 default 32 if ARCH_B4420 || \ 1261 ARCH_B4860 || \ 1262 ARCH_P2041 || \ 1263 ARCH_P3041 || \ 1264 ARCH_P4080 || \ 1265 ARCH_P5020 || \ 1266 ARCH_P5040 || \ 1267 ARCH_T2080 || \ 1268 ARCH_T2081 || \ 1269 ARCH_T4160 || \ 1270 ARCH_T4240 1271 default 16 if ARCH_T1023 || \ 1272 ARCH_T1024 || \ 1273 ARCH_T1040 || \ 1274 ARCH_T1042 1275 default 12 if ARCH_BSC9131 || \ 1276 ARCH_BSC9132 || \ 1277 ARCH_C29X || \ 1278 ARCH_MPC8536 || \ 1279 ARCH_MPC8572 || \ 1280 ARCH_P1010 || \ 1281 ARCH_P1011 || \ 1282 ARCH_P1020 || \ 1283 ARCH_P1021 || \ 1284 ARCH_P1022 || \ 1285 ARCH_P1023 || \ 1286 ARCH_P1024 || \ 1287 ARCH_P1025 || \ 1288 ARCH_P2020 1289 default 10 if ARCH_MPC8544 || \ 1290 ARCH_MPC8548 || \ 1291 ARCH_MPC8568 || \ 1292 ARCH_MPC8569 1293 default 8 if ARCH_MPC8540 || \ 1294 ARCH_MPC8541 || \ 1295 ARCH_MPC8555 || \ 1296 ARCH_MPC8560 1297 help 1298 Number of local access windows. This is fixed per SoC. 1299 If not sure, do not change. 1300 1301config SYS_FSL_THREADS_PER_CORE 1302 int 1303 default 2 if E6500 1304 default 1 1305 1306config SYS_NUM_TLBCAMS 1307 int "Number of TLB CAM entries" 1308 default 64 if E500MC 1309 default 16 1310 help 1311 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1312 16 for other E500 SoCs. 1313 1314config SYS_PPC64 1315 bool 1316 1317config SYS_PPC_E500_USE_DEBUG_TLB 1318 bool 1319 1320config FSL_IFC 1321 bool 1322 1323config FSL_ELBC 1324 bool 1325 1326config SYS_PPC_E500_DEBUG_TLB 1327 int "Temporary TLB entry for external debugger" 1328 depends on SYS_PPC_E500_USE_DEBUG_TLB 1329 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1330 default 1 if ARCH_MPC8536 1331 default 2 if ARCH_MPC8572 || \ 1332 ARCH_P1011 || \ 1333 ARCH_P1020 || \ 1334 ARCH_P1021 || \ 1335 ARCH_P1022 || \ 1336 ARCH_P1024 || \ 1337 ARCH_P1025 || \ 1338 ARCH_P2020 1339 default 3 if ARCH_P1010 || \ 1340 ARCH_BSC9132 || \ 1341 ARCH_C29X 1342 help 1343 Select a temporary TLB entry to be used during boot to work 1344 around limitations in e500v1 and e500v2 external debugger 1345 support. This reduces the portions of the boot code where 1346 breakpoints and single stepping do not work. The value of this 1347 symbol should be set to the TLB1 entry to be used for this 1348 purpose. If unsure, do not change. 1349 1350config SYS_FSL_IFC_CLK_DIV 1351 int "Divider of platform clock" 1352 depends on FSL_IFC 1353 default 2 if ARCH_B4420 || \ 1354 ARCH_B4860 || \ 1355 ARCH_T1024 || \ 1356 ARCH_T1023 || \ 1357 ARCH_T1040 || \ 1358 ARCH_T1042 || \ 1359 ARCH_T4160 || \ 1360 ARCH_T4240 1361 default 1 1362 help 1363 Defines divider of platform clock(clock input to 1364 IFC controller). 1365 1366config SYS_FSL_LBC_CLK_DIV 1367 int "Divider of platform clock" 1368 depends on FSL_ELBC || ARCH_MPC8540 || \ 1369 ARCH_MPC8548 || ARCH_MPC8541 || \ 1370 ARCH_MPC8555 || ARCH_MPC8560 || \ 1371 ARCH_MPC8568 1372 1373 default 2 if ARCH_P2041 || \ 1374 ARCH_P3041 || \ 1375 ARCH_P4080 || \ 1376 ARCH_P5020 || \ 1377 ARCH_P5040 1378 default 1 1379 1380 help 1381 Defines divider of platform clock(clock input to 1382 eLBC controller). 1383 1384source "board/freescale/b4860qds/Kconfig" 1385source "board/freescale/bsc9131rdb/Kconfig" 1386source "board/freescale/bsc9132qds/Kconfig" 1387source "board/freescale/c29xpcie/Kconfig" 1388source "board/freescale/corenet_ds/Kconfig" 1389source "board/freescale/mpc8536ds/Kconfig" 1390source "board/freescale/mpc8541cds/Kconfig" 1391source "board/freescale/mpc8544ds/Kconfig" 1392source "board/freescale/mpc8548cds/Kconfig" 1393source "board/freescale/mpc8555cds/Kconfig" 1394source "board/freescale/mpc8568mds/Kconfig" 1395source "board/freescale/mpc8569mds/Kconfig" 1396source "board/freescale/mpc8572ds/Kconfig" 1397source "board/freescale/p1010rdb/Kconfig" 1398source "board/freescale/p1022ds/Kconfig" 1399source "board/freescale/p1023rdb/Kconfig" 1400source "board/freescale/p1_p2_rdb_pc/Kconfig" 1401source "board/freescale/p1_twr/Kconfig" 1402source "board/freescale/p2041rdb/Kconfig" 1403source "board/freescale/qemu-ppce500/Kconfig" 1404source "board/freescale/t102xqds/Kconfig" 1405source "board/freescale/t102xrdb/Kconfig" 1406source "board/freescale/t1040qds/Kconfig" 1407source "board/freescale/t104xrdb/Kconfig" 1408source "board/freescale/t208xqds/Kconfig" 1409source "board/freescale/t208xrdb/Kconfig" 1410source "board/freescale/t4qds/Kconfig" 1411source "board/freescale/t4rdb/Kconfig" 1412source "board/gdsys/p1022/Kconfig" 1413source "board/keymile/kmp204x/Kconfig" 1414source "board/sbc8548/Kconfig" 1415source "board/socrates/Kconfig" 1416source "board/varisys/cyrus/Kconfig" 1417source "board/xes/xpedite520x/Kconfig" 1418source "board/xes/xpedite537x/Kconfig" 1419source "board/xes/xpedite550x/Kconfig" 1420source "board/Arcturus/ucp1020/Kconfig" 1421 1422endmenu 1423