1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 23config TARGET_SOCRATES 24 bool "Support socrates" 25 select ARCH_MPC8544 26 27config TARGET_B4420QDS 28 bool "Support B4420QDS" 29 select ARCH_B4420 30 select SUPPORT_SPL 31 select PHYS_64BIT 32 33config TARGET_B4860QDS 34 bool "Support B4860QDS" 35 select ARCH_B4860 36 select BOARD_LATE_INIT if CHAIN_OF_TRUST 37 select SUPPORT_SPL 38 select PHYS_64BIT 39 40config TARGET_BSC9131RDB 41 bool "Support BSC9131RDB" 42 select ARCH_BSC9131 43 select SUPPORT_SPL 44 select BOARD_EARLY_INIT_F 45 46config TARGET_BSC9132QDS 47 bool "Support BSC9132QDS" 48 select ARCH_BSC9132 49 select BOARD_LATE_INIT if CHAIN_OF_TRUST 50 select SUPPORT_SPL 51 select BOARD_EARLY_INIT_F 52 53config TARGET_C29XPCIE 54 bool "Support C29XPCIE" 55 select ARCH_C29X 56 select BOARD_LATE_INIT if CHAIN_OF_TRUST 57 select SUPPORT_SPL 58 select SUPPORT_TPL 59 select PHYS_64BIT 60 61config TARGET_P3041DS 62 bool "Support P3041DS" 63 select PHYS_64BIT 64 select ARCH_P3041 65 select BOARD_LATE_INIT if CHAIN_OF_TRUST 66 imply CMD_SATA 67 68config TARGET_P4080DS 69 bool "Support P4080DS" 70 select PHYS_64BIT 71 select ARCH_P4080 72 select BOARD_LATE_INIT if CHAIN_OF_TRUST 73 imply CMD_SATA 74 75config TARGET_P5020DS 76 bool "Support P5020DS" 77 select PHYS_64BIT 78 select ARCH_P5020 79 select BOARD_LATE_INIT if CHAIN_OF_TRUST 80 imply CMD_SATA 81 82config TARGET_P5040DS 83 bool "Support P5040DS" 84 select PHYS_64BIT 85 select ARCH_P5040 86 select BOARD_LATE_INIT if CHAIN_OF_TRUST 87 imply CMD_SATA 88 89config TARGET_MPC8536DS 90 bool "Support MPC8536DS" 91 select ARCH_MPC8536 92# Use DDR3 controller with DDR2 DIMMs on this board 93 select SYS_FSL_DDRC_GEN3 94 imply CMD_SATA 95 96config TARGET_MPC8541CDS 97 bool "Support MPC8541CDS" 98 select ARCH_MPC8541 99 100config TARGET_MPC8544DS 101 bool "Support MPC8544DS" 102 select ARCH_MPC8544 103 104config TARGET_MPC8548CDS 105 bool "Support MPC8548CDS" 106 select ARCH_MPC8548 107 108config TARGET_MPC8555CDS 109 bool "Support MPC8555CDS" 110 select ARCH_MPC8555 111 112config TARGET_MPC8568MDS 113 bool "Support MPC8568MDS" 114 select ARCH_MPC8568 115 116config TARGET_MPC8569MDS 117 bool "Support MPC8569MDS" 118 select ARCH_MPC8569 119 120config TARGET_MPC8572DS 121 bool "Support MPC8572DS" 122 select ARCH_MPC8572 123# Use DDR3 controller with DDR2 DIMMs on this board 124 select SYS_FSL_DDRC_GEN3 125 imply SCSI 126 127config TARGET_P1010RDB_PA 128 bool "Support P1010RDB_PA" 129 select ARCH_P1010 130 select BOARD_LATE_INIT if CHAIN_OF_TRUST 131 select SUPPORT_SPL 132 select SUPPORT_TPL 133 imply CMD_EEPROM 134 imply CMD_SATA 135 136config TARGET_P1010RDB_PB 137 bool "Support P1010RDB_PB" 138 select ARCH_P1010 139 select BOARD_LATE_INIT if CHAIN_OF_TRUST 140 select SUPPORT_SPL 141 select SUPPORT_TPL 142 imply CMD_EEPROM 143 imply CMD_SATA 144 145config TARGET_P1022DS 146 bool "Support P1022DS" 147 select ARCH_P1022 148 select SUPPORT_SPL 149 select SUPPORT_TPL 150 imply CMD_SATA 151 152config TARGET_P1023RDB 153 bool "Support P1023RDB" 154 select ARCH_P1023 155 imply CMD_EEPROM 156 157config TARGET_P1020MBG 158 bool "Support P1020MBG-PC" 159 select SUPPORT_SPL 160 select SUPPORT_TPL 161 select ARCH_P1020 162 imply CMD_EEPROM 163 imply CMD_SATA 164 165config TARGET_P1020RDB_PC 166 bool "Support P1020RDB-PC" 167 select SUPPORT_SPL 168 select SUPPORT_TPL 169 select ARCH_P1020 170 imply CMD_EEPROM 171 imply CMD_SATA 172 173config TARGET_P1020RDB_PD 174 bool "Support P1020RDB-PD" 175 select SUPPORT_SPL 176 select SUPPORT_TPL 177 select ARCH_P1020 178 imply CMD_EEPROM 179 imply CMD_SATA 180 181config TARGET_P1020UTM 182 bool "Support P1020UTM" 183 select SUPPORT_SPL 184 select SUPPORT_TPL 185 select ARCH_P1020 186 imply CMD_EEPROM 187 imply CMD_SATA 188 189config TARGET_P1021RDB 190 bool "Support P1021RDB" 191 select SUPPORT_SPL 192 select SUPPORT_TPL 193 select ARCH_P1021 194 imply CMD_EEPROM 195 imply CMD_SATA 196 197config TARGET_P1024RDB 198 bool "Support P1024RDB" 199 select SUPPORT_SPL 200 select SUPPORT_TPL 201 select ARCH_P1024 202 imply CMD_EEPROM 203 imply CMD_SATA 204 205config TARGET_P1025RDB 206 bool "Support P1025RDB" 207 select SUPPORT_SPL 208 select SUPPORT_TPL 209 select ARCH_P1025 210 imply CMD_EEPROM 211 imply CMD_SATA 212 213config TARGET_P2020RDB 214 bool "Support P2020RDB-PC" 215 select SUPPORT_SPL 216 select SUPPORT_TPL 217 select ARCH_P2020 218 imply CMD_EEPROM 219 imply CMD_SATA 220 221config TARGET_P1_TWR 222 bool "Support p1_twr" 223 select ARCH_P1025 224 225config TARGET_P2041RDB 226 bool "Support P2041RDB" 227 select ARCH_P2041 228 select BOARD_LATE_INIT if CHAIN_OF_TRUST 229 select PHYS_64BIT 230 imply CMD_SATA 231 232config TARGET_QEMU_PPCE500 233 bool "Support qemu-ppce500" 234 select ARCH_QEMU_E500 235 select PHYS_64BIT 236 237config TARGET_T1024QDS 238 bool "Support T1024QDS" 239 select ARCH_T1024 240 select BOARD_LATE_INIT if CHAIN_OF_TRUST 241 select SUPPORT_SPL 242 select PHYS_64BIT 243 imply CMD_EEPROM 244 imply CMD_SATA 245 246config TARGET_T1023RDB 247 bool "Support T1023RDB" 248 select ARCH_T1023 249 select BOARD_LATE_INIT if CHAIN_OF_TRUST 250 select SUPPORT_SPL 251 select PHYS_64BIT 252 imply CMD_EEPROM 253 254config TARGET_T1024RDB 255 bool "Support T1024RDB" 256 select ARCH_T1024 257 select BOARD_LATE_INIT if CHAIN_OF_TRUST 258 select SUPPORT_SPL 259 select PHYS_64BIT 260 imply CMD_EEPROM 261 262config TARGET_T1040QDS 263 bool "Support T1040QDS" 264 select ARCH_T1040 265 select BOARD_LATE_INIT if CHAIN_OF_TRUST 266 select PHYS_64BIT 267 imply CMD_EEPROM 268 imply CMD_SATA 269 270config TARGET_T1040RDB 271 bool "Support T1040RDB" 272 select ARCH_T1040 273 select BOARD_LATE_INIT if CHAIN_OF_TRUST 274 select SUPPORT_SPL 275 select PHYS_64BIT 276 imply CMD_SATA 277 278config TARGET_T1040D4RDB 279 bool "Support T1040D4RDB" 280 select ARCH_T1040 281 select BOARD_LATE_INIT if CHAIN_OF_TRUST 282 select SUPPORT_SPL 283 select PHYS_64BIT 284 imply CMD_SATA 285 286config TARGET_T1042RDB 287 bool "Support T1042RDB" 288 select ARCH_T1042 289 select BOARD_LATE_INIT if CHAIN_OF_TRUST 290 select SUPPORT_SPL 291 select PHYS_64BIT 292 imply CMD_SATA 293 294config TARGET_T1042D4RDB 295 bool "Support T1042D4RDB" 296 select ARCH_T1042 297 select BOARD_LATE_INIT if CHAIN_OF_TRUST 298 select SUPPORT_SPL 299 select PHYS_64BIT 300 imply CMD_SATA 301 302config TARGET_T1042RDB_PI 303 bool "Support T1042RDB_PI" 304 select ARCH_T1042 305 select BOARD_LATE_INIT if CHAIN_OF_TRUST 306 select SUPPORT_SPL 307 select PHYS_64BIT 308 imply CMD_SATA 309 310config TARGET_T2080QDS 311 bool "Support T2080QDS" 312 select ARCH_T2080 313 select BOARD_LATE_INIT if CHAIN_OF_TRUST 314 select SUPPORT_SPL 315 select PHYS_64BIT 316 imply CMD_SATA 317 318config TARGET_T2080RDB 319 bool "Support T2080RDB" 320 select ARCH_T2080 321 select BOARD_LATE_INIT if CHAIN_OF_TRUST 322 select SUPPORT_SPL 323 select PHYS_64BIT 324 imply CMD_SATA 325 326config TARGET_T2081QDS 327 bool "Support T2081QDS" 328 select ARCH_T2081 329 select SUPPORT_SPL 330 select PHYS_64BIT 331 332config TARGET_T4160QDS 333 bool "Support T4160QDS" 334 select ARCH_T4160 335 select BOARD_LATE_INIT if CHAIN_OF_TRUST 336 select SUPPORT_SPL 337 select PHYS_64BIT 338 imply CMD_SATA 339 340config TARGET_T4160RDB 341 bool "Support T4160RDB" 342 select ARCH_T4160 343 select SUPPORT_SPL 344 select PHYS_64BIT 345 346config TARGET_T4240QDS 347 bool "Support T4240QDS" 348 select ARCH_T4240 349 select BOARD_LATE_INIT if CHAIN_OF_TRUST 350 select SUPPORT_SPL 351 select PHYS_64BIT 352 imply CMD_SATA 353 354config TARGET_T4240RDB 355 bool "Support T4240RDB" 356 select ARCH_T4240 357 select SUPPORT_SPL 358 select PHYS_64BIT 359 imply CMD_SATA 360 361config TARGET_CONTROLCENTERD 362 bool "Support controlcenterd" 363 select ARCH_P1022 364 365config TARGET_KMP204X 366 bool "Support kmp204x" 367 select ARCH_P2041 368 select PHYS_64BIT 369 imply CMD_CRAMFS 370 imply FS_CRAMFS 371 372config TARGET_XPEDITE520X 373 bool "Support xpedite520x" 374 select ARCH_MPC8548 375 376config TARGET_XPEDITE537X 377 bool "Support xpedite537x" 378 select ARCH_MPC8572 379# Use DDR3 controller with DDR2 DIMMs on this board 380 select SYS_FSL_DDRC_GEN3 381 382config TARGET_XPEDITE550X 383 bool "Support xpedite550x" 384 select ARCH_P2020 385 386config TARGET_UCP1020 387 bool "Support uCP1020" 388 select ARCH_P1020 389 imply CMD_SATA 390 391config TARGET_CYRUS_P5020 392 bool "Support Varisys Cyrus P5020" 393 select ARCH_P5020 394 select PHYS_64BIT 395 396config TARGET_CYRUS_P5040 397 bool "Support Varisys Cyrus P5040" 398 select ARCH_P5040 399 select PHYS_64BIT 400 401endchoice 402 403config ARCH_B4420 404 bool 405 select E500MC 406 select E6500 407 select FSL_LAW 408 select SYS_FSL_DDR_VER_47 409 select SYS_FSL_ERRATUM_A004477 410 select SYS_FSL_ERRATUM_A005871 411 select SYS_FSL_ERRATUM_A006379 412 select SYS_FSL_ERRATUM_A006384 413 select SYS_FSL_ERRATUM_A006475 414 select SYS_FSL_ERRATUM_A006593 415 select SYS_FSL_ERRATUM_A007075 416 select SYS_FSL_ERRATUM_A007186 417 select SYS_FSL_ERRATUM_A007212 418 select SYS_FSL_ERRATUM_A009942 419 select SYS_FSL_HAS_DDR3 420 select SYS_FSL_HAS_SEC 421 select SYS_FSL_QORIQ_CHASSIS2 422 select SYS_FSL_SEC_BE 423 select SYS_FSL_SEC_COMPAT_4 424 select SYS_PPC64 425 select FSL_IFC 426 imply CMD_EEPROM 427 428config ARCH_B4860 429 bool 430 select E500MC 431 select E6500 432 select FSL_LAW 433 select SYS_FSL_DDR_VER_47 434 select SYS_FSL_ERRATUM_A004477 435 select SYS_FSL_ERRATUM_A005871 436 select SYS_FSL_ERRATUM_A006379 437 select SYS_FSL_ERRATUM_A006384 438 select SYS_FSL_ERRATUM_A006475 439 select SYS_FSL_ERRATUM_A006593 440 select SYS_FSL_ERRATUM_A007075 441 select SYS_FSL_ERRATUM_A007186 442 select SYS_FSL_ERRATUM_A007212 443 select SYS_FSL_ERRATUM_A007907 444 select SYS_FSL_ERRATUM_A009942 445 select SYS_FSL_HAS_DDR3 446 select SYS_FSL_HAS_SEC 447 select SYS_FSL_QORIQ_CHASSIS2 448 select SYS_FSL_SEC_BE 449 select SYS_FSL_SEC_COMPAT_4 450 select SYS_PPC64 451 select FSL_IFC 452 imply CMD_EEPROM 453 454config ARCH_BSC9131 455 bool 456 select FSL_LAW 457 select SYS_FSL_DDR_VER_44 458 select SYS_FSL_ERRATUM_A004477 459 select SYS_FSL_ERRATUM_A005125 460 select SYS_FSL_ERRATUM_ESDHC111 461 select SYS_FSL_HAS_DDR3 462 select SYS_FSL_HAS_SEC 463 select SYS_FSL_SEC_BE 464 select SYS_FSL_SEC_COMPAT_4 465 select FSL_IFC 466 imply CMD_EEPROM 467 468config ARCH_BSC9132 469 bool 470 select FSL_LAW 471 select SYS_FSL_DDR_VER_46 472 select SYS_FSL_ERRATUM_A004477 473 select SYS_FSL_ERRATUM_A005125 474 select SYS_FSL_ERRATUM_A005434 475 select SYS_FSL_ERRATUM_ESDHC111 476 select SYS_FSL_ERRATUM_I2C_A004447 477 select SYS_FSL_ERRATUM_IFC_A002769 478 select SYS_FSL_HAS_DDR3 479 select SYS_FSL_HAS_SEC 480 select SYS_FSL_SEC_BE 481 select SYS_FSL_SEC_COMPAT_4 482 select SYS_PPC_E500_USE_DEBUG_TLB 483 select FSL_IFC 484 imply CMD_EEPROM 485 486config ARCH_C29X 487 bool 488 select FSL_LAW 489 select SYS_FSL_DDR_VER_46 490 select SYS_FSL_ERRATUM_A005125 491 select SYS_FSL_ERRATUM_ESDHC111 492 select SYS_FSL_HAS_DDR3 493 select SYS_FSL_HAS_SEC 494 select SYS_FSL_SEC_BE 495 select SYS_FSL_SEC_COMPAT_6 496 select SYS_PPC_E500_USE_DEBUG_TLB 497 select FSL_IFC 498 499config ARCH_MPC8536 500 bool 501 select FSL_LAW 502 select SYS_FSL_ERRATUM_A004508 503 select SYS_FSL_ERRATUM_A005125 504 select SYS_FSL_HAS_DDR2 505 select SYS_FSL_HAS_DDR3 506 select SYS_FSL_HAS_SEC 507 select SYS_FSL_SEC_BE 508 select SYS_FSL_SEC_COMPAT_2 509 select SYS_PPC_E500_USE_DEBUG_TLB 510 select FSL_ELBC 511 imply CMD_SATA 512 513config ARCH_MPC8540 514 bool 515 select FSL_LAW 516 select SYS_FSL_HAS_DDR1 517 518config ARCH_MPC8541 519 bool 520 select FSL_LAW 521 select SYS_FSL_HAS_DDR1 522 select SYS_FSL_HAS_SEC 523 select SYS_FSL_SEC_BE 524 select SYS_FSL_SEC_COMPAT_2 525 526config ARCH_MPC8544 527 bool 528 select FSL_LAW 529 select SYS_FSL_ERRATUM_A005125 530 select SYS_FSL_HAS_DDR2 531 select SYS_FSL_HAS_SEC 532 select SYS_FSL_SEC_BE 533 select SYS_FSL_SEC_COMPAT_2 534 select SYS_PPC_E500_USE_DEBUG_TLB 535 select FSL_ELBC 536 537config ARCH_MPC8548 538 bool 539 select FSL_LAW 540 select SYS_FSL_ERRATUM_A005125 541 select SYS_FSL_ERRATUM_NMG_DDR120 542 select SYS_FSL_ERRATUM_NMG_LBC103 543 select SYS_FSL_ERRATUM_NMG_ETSEC129 544 select SYS_FSL_ERRATUM_I2C_A004447 545 select SYS_FSL_HAS_DDR2 546 select SYS_FSL_HAS_DDR1 547 select SYS_FSL_HAS_SEC 548 select SYS_FSL_SEC_BE 549 select SYS_FSL_SEC_COMPAT_2 550 select SYS_PPC_E500_USE_DEBUG_TLB 551 552config ARCH_MPC8555 553 bool 554 select FSL_LAW 555 select SYS_FSL_HAS_DDR1 556 select SYS_FSL_HAS_SEC 557 select SYS_FSL_SEC_BE 558 select SYS_FSL_SEC_COMPAT_2 559 560config ARCH_MPC8560 561 bool 562 select FSL_LAW 563 select SYS_FSL_HAS_DDR1 564 565config ARCH_MPC8568 566 bool 567 select FSL_LAW 568 select SYS_FSL_HAS_DDR2 569 select SYS_FSL_HAS_SEC 570 select SYS_FSL_SEC_BE 571 select SYS_FSL_SEC_COMPAT_2 572 573config ARCH_MPC8569 574 bool 575 select FSL_LAW 576 select SYS_FSL_ERRATUM_A004508 577 select SYS_FSL_ERRATUM_A005125 578 select SYS_FSL_HAS_DDR3 579 select SYS_FSL_HAS_SEC 580 select SYS_FSL_SEC_BE 581 select SYS_FSL_SEC_COMPAT_2 582 select FSL_ELBC 583 584config ARCH_MPC8572 585 bool 586 select FSL_LAW 587 select SYS_FSL_ERRATUM_A004508 588 select SYS_FSL_ERRATUM_A005125 589 select SYS_FSL_ERRATUM_DDR_115 590 select SYS_FSL_ERRATUM_DDR111_DDR134 591 select SYS_FSL_HAS_DDR2 592 select SYS_FSL_HAS_DDR3 593 select SYS_FSL_HAS_SEC 594 select SYS_FSL_SEC_BE 595 select SYS_FSL_SEC_COMPAT_2 596 select SYS_PPC_E500_USE_DEBUG_TLB 597 select FSL_ELBC 598 599config ARCH_P1010 600 bool 601 select FSL_LAW 602 select SYS_FSL_ERRATUM_A004477 603 select SYS_FSL_ERRATUM_A004508 604 select SYS_FSL_ERRATUM_A005125 605 select SYS_FSL_ERRATUM_A006261 606 select SYS_FSL_ERRATUM_A007075 607 select SYS_FSL_ERRATUM_ESDHC111 608 select SYS_FSL_ERRATUM_I2C_A004447 609 select SYS_FSL_ERRATUM_IFC_A002769 610 select SYS_FSL_ERRATUM_P1010_A003549 611 select SYS_FSL_ERRATUM_SEC_A003571 612 select SYS_FSL_ERRATUM_IFC_A003399 613 select SYS_FSL_HAS_DDR3 614 select SYS_FSL_HAS_SEC 615 select SYS_FSL_SEC_BE 616 select SYS_FSL_SEC_COMPAT_4 617 select SYS_PPC_E500_USE_DEBUG_TLB 618 select FSL_IFC 619 imply CMD_EEPROM 620 imply CMD_SATA 621 622config ARCH_P1011 623 bool 624 select FSL_LAW 625 select SYS_FSL_ERRATUM_A004508 626 select SYS_FSL_ERRATUM_A005125 627 select SYS_FSL_ERRATUM_ELBC_A001 628 select SYS_FSL_ERRATUM_ESDHC111 629 select SYS_FSL_HAS_DDR3 630 select SYS_FSL_HAS_SEC 631 select SYS_FSL_SEC_BE 632 select SYS_FSL_SEC_COMPAT_2 633 select SYS_PPC_E500_USE_DEBUG_TLB 634 select FSL_ELBC 635 636config ARCH_P1020 637 bool 638 select FSL_LAW 639 select SYS_FSL_ERRATUM_A004508 640 select SYS_FSL_ERRATUM_A005125 641 select SYS_FSL_ERRATUM_ELBC_A001 642 select SYS_FSL_ERRATUM_ESDHC111 643 select SYS_FSL_HAS_DDR3 644 select SYS_FSL_HAS_SEC 645 select SYS_FSL_SEC_BE 646 select SYS_FSL_SEC_COMPAT_2 647 select SYS_PPC_E500_USE_DEBUG_TLB 648 select FSL_ELBC 649 imply CMD_SATA 650 651config ARCH_P1021 652 bool 653 select FSL_LAW 654 select SYS_FSL_ERRATUM_A004508 655 select SYS_FSL_ERRATUM_A005125 656 select SYS_FSL_ERRATUM_ELBC_A001 657 select SYS_FSL_ERRATUM_ESDHC111 658 select SYS_FSL_HAS_DDR3 659 select SYS_FSL_HAS_SEC 660 select SYS_FSL_SEC_BE 661 select SYS_FSL_SEC_COMPAT_2 662 select SYS_PPC_E500_USE_DEBUG_TLB 663 select FSL_ELBC 664 imply CMD_SATA 665 666config ARCH_P1022 667 bool 668 select FSL_LAW 669 select SYS_FSL_ERRATUM_A004477 670 select SYS_FSL_ERRATUM_A004508 671 select SYS_FSL_ERRATUM_A005125 672 select SYS_FSL_ERRATUM_ELBC_A001 673 select SYS_FSL_ERRATUM_ESDHC111 674 select SYS_FSL_ERRATUM_SATA_A001 675 select SYS_FSL_HAS_DDR3 676 select SYS_FSL_HAS_SEC 677 select SYS_FSL_SEC_BE 678 select SYS_FSL_SEC_COMPAT_2 679 select SYS_PPC_E500_USE_DEBUG_TLB 680 select FSL_ELBC 681 682config ARCH_P1023 683 bool 684 select FSL_LAW 685 select SYS_FSL_ERRATUM_A004508 686 select SYS_FSL_ERRATUM_A005125 687 select SYS_FSL_ERRATUM_I2C_A004447 688 select SYS_FSL_HAS_DDR3 689 select SYS_FSL_HAS_SEC 690 select SYS_FSL_SEC_BE 691 select SYS_FSL_SEC_COMPAT_4 692 select FSL_ELBC 693 694config ARCH_P1024 695 bool 696 select FSL_LAW 697 select SYS_FSL_ERRATUM_A004508 698 select SYS_FSL_ERRATUM_A005125 699 select SYS_FSL_ERRATUM_ELBC_A001 700 select SYS_FSL_ERRATUM_ESDHC111 701 select SYS_FSL_HAS_DDR3 702 select SYS_FSL_HAS_SEC 703 select SYS_FSL_SEC_BE 704 select SYS_FSL_SEC_COMPAT_2 705 select SYS_PPC_E500_USE_DEBUG_TLB 706 select FSL_ELBC 707 imply CMD_EEPROM 708 imply CMD_SATA 709 710config ARCH_P1025 711 bool 712 select FSL_LAW 713 select SYS_FSL_ERRATUM_A004508 714 select SYS_FSL_ERRATUM_A005125 715 select SYS_FSL_ERRATUM_ELBC_A001 716 select SYS_FSL_ERRATUM_ESDHC111 717 select SYS_FSL_HAS_DDR3 718 select SYS_FSL_HAS_SEC 719 select SYS_FSL_SEC_BE 720 select SYS_FSL_SEC_COMPAT_2 721 select SYS_PPC_E500_USE_DEBUG_TLB 722 select FSL_ELBC 723 imply CMD_SATA 724 725config ARCH_P2020 726 bool 727 select FSL_LAW 728 select SYS_FSL_ERRATUM_A004477 729 select SYS_FSL_ERRATUM_A004508 730 select SYS_FSL_ERRATUM_A005125 731 select SYS_FSL_ERRATUM_ESDHC111 732 select SYS_FSL_ERRATUM_ESDHC_A001 733 select SYS_FSL_HAS_DDR3 734 select SYS_FSL_HAS_SEC 735 select SYS_FSL_SEC_BE 736 select SYS_FSL_SEC_COMPAT_2 737 select SYS_PPC_E500_USE_DEBUG_TLB 738 select FSL_ELBC 739 imply CMD_EEPROM 740 741config ARCH_P2041 742 bool 743 select E500MC 744 select FSL_LAW 745 select SYS_FSL_ERRATUM_A004510 746 select SYS_FSL_ERRATUM_A004849 747 select SYS_FSL_ERRATUM_A006261 748 select SYS_FSL_ERRATUM_CPU_A003999 749 select SYS_FSL_ERRATUM_DDR_A003 750 select SYS_FSL_ERRATUM_DDR_A003474 751 select SYS_FSL_ERRATUM_ESDHC111 752 select SYS_FSL_ERRATUM_I2C_A004447 753 select SYS_FSL_ERRATUM_NMG_CPU_A011 754 select SYS_FSL_ERRATUM_SRIO_A004034 755 select SYS_FSL_ERRATUM_USB14 756 select SYS_FSL_HAS_DDR3 757 select SYS_FSL_HAS_SEC 758 select SYS_FSL_QORIQ_CHASSIS1 759 select SYS_FSL_SEC_BE 760 select SYS_FSL_SEC_COMPAT_4 761 select FSL_ELBC 762 763config ARCH_P3041 764 bool 765 select E500MC 766 select FSL_LAW 767 select SYS_FSL_DDR_VER_44 768 select SYS_FSL_ERRATUM_A004510 769 select SYS_FSL_ERRATUM_A004849 770 select SYS_FSL_ERRATUM_A005812 771 select SYS_FSL_ERRATUM_A006261 772 select SYS_FSL_ERRATUM_CPU_A003999 773 select SYS_FSL_ERRATUM_DDR_A003 774 select SYS_FSL_ERRATUM_DDR_A003474 775 select SYS_FSL_ERRATUM_ESDHC111 776 select SYS_FSL_ERRATUM_I2C_A004447 777 select SYS_FSL_ERRATUM_NMG_CPU_A011 778 select SYS_FSL_ERRATUM_SRIO_A004034 779 select SYS_FSL_ERRATUM_USB14 780 select SYS_FSL_HAS_DDR3 781 select SYS_FSL_HAS_SEC 782 select SYS_FSL_QORIQ_CHASSIS1 783 select SYS_FSL_SEC_BE 784 select SYS_FSL_SEC_COMPAT_4 785 select FSL_ELBC 786 imply CMD_SATA 787 788config ARCH_P4080 789 bool 790 select E500MC 791 select FSL_LAW 792 select SYS_FSL_DDR_VER_44 793 select SYS_FSL_ERRATUM_A004510 794 select SYS_FSL_ERRATUM_A004580 795 select SYS_FSL_ERRATUM_A004849 796 select SYS_FSL_ERRATUM_A005812 797 select SYS_FSL_ERRATUM_A007075 798 select SYS_FSL_ERRATUM_CPC_A002 799 select SYS_FSL_ERRATUM_CPC_A003 800 select SYS_FSL_ERRATUM_CPU_A003999 801 select SYS_FSL_ERRATUM_DDR_A003 802 select SYS_FSL_ERRATUM_DDR_A003474 803 select SYS_FSL_ERRATUM_ELBC_A001 804 select SYS_FSL_ERRATUM_ESDHC111 805 select SYS_FSL_ERRATUM_ESDHC13 806 select SYS_FSL_ERRATUM_ESDHC135 807 select SYS_FSL_ERRATUM_I2C_A004447 808 select SYS_FSL_ERRATUM_NMG_CPU_A011 809 select SYS_FSL_ERRATUM_SRIO_A004034 810 select SYS_P4080_ERRATUM_CPU22 811 select SYS_P4080_ERRATUM_PCIE_A003 812 select SYS_P4080_ERRATUM_SERDES8 813 select SYS_P4080_ERRATUM_SERDES9 814 select SYS_P4080_ERRATUM_SERDES_A001 815 select SYS_P4080_ERRATUM_SERDES_A005 816 select SYS_FSL_HAS_DDR3 817 select SYS_FSL_HAS_SEC 818 select SYS_FSL_QORIQ_CHASSIS1 819 select SYS_FSL_SEC_BE 820 select SYS_FSL_SEC_COMPAT_4 821 select FSL_ELBC 822 imply CMD_SATA 823 824config ARCH_P5020 825 bool 826 select E500MC 827 select FSL_LAW 828 select SYS_FSL_DDR_VER_44 829 select SYS_FSL_ERRATUM_A004510 830 select SYS_FSL_ERRATUM_A006261 831 select SYS_FSL_ERRATUM_DDR_A003 832 select SYS_FSL_ERRATUM_DDR_A003474 833 select SYS_FSL_ERRATUM_ESDHC111 834 select SYS_FSL_ERRATUM_I2C_A004447 835 select SYS_FSL_ERRATUM_SRIO_A004034 836 select SYS_FSL_ERRATUM_USB14 837 select SYS_FSL_HAS_DDR3 838 select SYS_FSL_HAS_SEC 839 select SYS_FSL_QORIQ_CHASSIS1 840 select SYS_FSL_SEC_BE 841 select SYS_FSL_SEC_COMPAT_4 842 select SYS_PPC64 843 select FSL_ELBC 844 imply CMD_SATA 845 846config ARCH_P5040 847 bool 848 select E500MC 849 select FSL_LAW 850 select SYS_FSL_DDR_VER_44 851 select SYS_FSL_ERRATUM_A004510 852 select SYS_FSL_ERRATUM_A004699 853 select SYS_FSL_ERRATUM_A005812 854 select SYS_FSL_ERRATUM_A006261 855 select SYS_FSL_ERRATUM_DDR_A003 856 select SYS_FSL_ERRATUM_DDR_A003474 857 select SYS_FSL_ERRATUM_ESDHC111 858 select SYS_FSL_ERRATUM_USB14 859 select SYS_FSL_HAS_DDR3 860 select SYS_FSL_HAS_SEC 861 select SYS_FSL_QORIQ_CHASSIS1 862 select SYS_FSL_SEC_BE 863 select SYS_FSL_SEC_COMPAT_4 864 select SYS_PPC64 865 select FSL_ELBC 866 imply CMD_SATA 867 868config ARCH_QEMU_E500 869 bool 870 871config ARCH_T1023 872 bool 873 select E500MC 874 select FSL_LAW 875 select SYS_FSL_DDR_VER_50 876 select SYS_FSL_ERRATUM_A008378 877 select SYS_FSL_ERRATUM_A009663 878 select SYS_FSL_ERRATUM_A009942 879 select SYS_FSL_ERRATUM_ESDHC111 880 select SYS_FSL_HAS_DDR3 881 select SYS_FSL_HAS_DDR4 882 select SYS_FSL_HAS_SEC 883 select SYS_FSL_QORIQ_CHASSIS2 884 select SYS_FSL_SEC_BE 885 select SYS_FSL_SEC_COMPAT_5 886 select FSL_IFC 887 imply CMD_EEPROM 888 889config ARCH_T1024 890 bool 891 select E500MC 892 select FSL_LAW 893 select SYS_FSL_DDR_VER_50 894 select SYS_FSL_ERRATUM_A008378 895 select SYS_FSL_ERRATUM_A009663 896 select SYS_FSL_ERRATUM_A009942 897 select SYS_FSL_ERRATUM_ESDHC111 898 select SYS_FSL_HAS_DDR3 899 select SYS_FSL_HAS_DDR4 900 select SYS_FSL_HAS_SEC 901 select SYS_FSL_QORIQ_CHASSIS2 902 select SYS_FSL_SEC_BE 903 select SYS_FSL_SEC_COMPAT_5 904 select FSL_IFC 905 imply CMD_EEPROM 906 907config ARCH_T1040 908 bool 909 select E500MC 910 select FSL_LAW 911 select SYS_FSL_DDR_VER_50 912 select SYS_FSL_ERRATUM_A008044 913 select SYS_FSL_ERRATUM_A008378 914 select SYS_FSL_ERRATUM_A009663 915 select SYS_FSL_ERRATUM_A009942 916 select SYS_FSL_ERRATUM_ESDHC111 917 select SYS_FSL_HAS_DDR3 918 select SYS_FSL_HAS_DDR4 919 select SYS_FSL_HAS_SEC 920 select SYS_FSL_QORIQ_CHASSIS2 921 select SYS_FSL_SEC_BE 922 select SYS_FSL_SEC_COMPAT_5 923 select FSL_IFC 924 imply CMD_SATA 925 926config ARCH_T1042 927 bool 928 select E500MC 929 select FSL_LAW 930 select SYS_FSL_DDR_VER_50 931 select SYS_FSL_ERRATUM_A008044 932 select SYS_FSL_ERRATUM_A008378 933 select SYS_FSL_ERRATUM_A009663 934 select SYS_FSL_ERRATUM_A009942 935 select SYS_FSL_ERRATUM_ESDHC111 936 select SYS_FSL_HAS_DDR3 937 select SYS_FSL_HAS_DDR4 938 select SYS_FSL_HAS_SEC 939 select SYS_FSL_QORIQ_CHASSIS2 940 select SYS_FSL_SEC_BE 941 select SYS_FSL_SEC_COMPAT_5 942 select FSL_IFC 943 imply CMD_SATA 944 945config ARCH_T2080 946 bool 947 select E500MC 948 select E6500 949 select FSL_LAW 950 select SYS_FSL_DDR_VER_47 951 select SYS_FSL_ERRATUM_A006379 952 select SYS_FSL_ERRATUM_A006593 953 select SYS_FSL_ERRATUM_A007186 954 select SYS_FSL_ERRATUM_A007212 955 select SYS_FSL_ERRATUM_A007815 956 select SYS_FSL_ERRATUM_A007907 957 select SYS_FSL_ERRATUM_A009942 958 select SYS_FSL_ERRATUM_ESDHC111 959 select SYS_FSL_HAS_DDR3 960 select SYS_FSL_HAS_SEC 961 select SYS_FSL_QORIQ_CHASSIS2 962 select SYS_FSL_SEC_BE 963 select SYS_FSL_SEC_COMPAT_4 964 select SYS_PPC64 965 select FSL_IFC 966 imply CMD_SATA 967 968config ARCH_T2081 969 bool 970 select E500MC 971 select E6500 972 select FSL_LAW 973 select SYS_FSL_DDR_VER_47 974 select SYS_FSL_ERRATUM_A006379 975 select SYS_FSL_ERRATUM_A006593 976 select SYS_FSL_ERRATUM_A007186 977 select SYS_FSL_ERRATUM_A007212 978 select SYS_FSL_ERRATUM_A009942 979 select SYS_FSL_ERRATUM_ESDHC111 980 select SYS_FSL_HAS_DDR3 981 select SYS_FSL_HAS_SEC 982 select SYS_FSL_QORIQ_CHASSIS2 983 select SYS_FSL_SEC_BE 984 select SYS_FSL_SEC_COMPAT_4 985 select SYS_PPC64 986 select FSL_IFC 987 988config ARCH_T4160 989 bool 990 select E500MC 991 select E6500 992 select FSL_LAW 993 select SYS_FSL_DDR_VER_47 994 select SYS_FSL_ERRATUM_A004468 995 select SYS_FSL_ERRATUM_A005871 996 select SYS_FSL_ERRATUM_A006379 997 select SYS_FSL_ERRATUM_A006593 998 select SYS_FSL_ERRATUM_A007186 999 select SYS_FSL_ERRATUM_A007798 1000 select SYS_FSL_ERRATUM_A009942 1001 select SYS_FSL_HAS_DDR3 1002 select SYS_FSL_HAS_SEC 1003 select SYS_FSL_QORIQ_CHASSIS2 1004 select SYS_FSL_SEC_BE 1005 select SYS_FSL_SEC_COMPAT_4 1006 select SYS_PPC64 1007 select FSL_IFC 1008 imply CMD_SATA 1009 1010config ARCH_T4240 1011 bool 1012 select E500MC 1013 select E6500 1014 select FSL_LAW 1015 select SYS_FSL_DDR_VER_47 1016 select SYS_FSL_ERRATUM_A004468 1017 select SYS_FSL_ERRATUM_A005871 1018 select SYS_FSL_ERRATUM_A006261 1019 select SYS_FSL_ERRATUM_A006379 1020 select SYS_FSL_ERRATUM_A006593 1021 select SYS_FSL_ERRATUM_A007186 1022 select SYS_FSL_ERRATUM_A007798 1023 select SYS_FSL_ERRATUM_A007815 1024 select SYS_FSL_ERRATUM_A007907 1025 select SYS_FSL_ERRATUM_A009942 1026 select SYS_FSL_HAS_DDR3 1027 select SYS_FSL_HAS_SEC 1028 select SYS_FSL_QORIQ_CHASSIS2 1029 select SYS_FSL_SEC_BE 1030 select SYS_FSL_SEC_COMPAT_4 1031 select SYS_PPC64 1032 select FSL_IFC 1033 imply CMD_SATA 1034 1035config BOOKE 1036 bool 1037 default y 1038 1039config E500 1040 bool 1041 default y 1042 help 1043 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 1044 1045config E500MC 1046 bool 1047 help 1048 Enble PowerPC E500MC core 1049 1050config E6500 1051 bool 1052 help 1053 Enable PowerPC E6500 core 1054 1055config FSL_LAW 1056 bool 1057 help 1058 Use Freescale common code for Local Access Window 1059 1060config SECURE_BOOT 1061 bool "Secure Boot" 1062 help 1063 Enable Freescale Secure Boot feature. Normally selected 1064 by defconfig. If unsure, do not change. 1065 1066config MAX_CPUS 1067 int "Maximum number of CPUs permitted for MPC85xx" 1068 default 12 if ARCH_T4240 1069 default 8 if ARCH_P4080 || \ 1070 ARCH_T4160 1071 default 4 if ARCH_B4860 || \ 1072 ARCH_P2041 || \ 1073 ARCH_P3041 || \ 1074 ARCH_P5040 || \ 1075 ARCH_T1040 || \ 1076 ARCH_T1042 || \ 1077 ARCH_T2080 || \ 1078 ARCH_T2081 1079 default 2 if ARCH_B4420 || \ 1080 ARCH_BSC9132 || \ 1081 ARCH_MPC8572 || \ 1082 ARCH_P1020 || \ 1083 ARCH_P1021 || \ 1084 ARCH_P1022 || \ 1085 ARCH_P1023 || \ 1086 ARCH_P1024 || \ 1087 ARCH_P1025 || \ 1088 ARCH_P2020 || \ 1089 ARCH_P5020 || \ 1090 ARCH_T1023 || \ 1091 ARCH_T1024 1092 default 1 1093 help 1094 Set this number to the maximum number of possible CPUs in the SoC. 1095 SoCs may have multiple clusters with each cluster may have multiple 1096 ports. If some ports are reserved but higher ports are used for 1097 cores, count the reserved ports. This will allocate enough memory 1098 in spin table to properly handle all cores. 1099 1100config SYS_CCSRBAR_DEFAULT 1101 hex "Default CCSRBAR address" 1102 default 0xff700000 if ARCH_BSC9131 || \ 1103 ARCH_BSC9132 || \ 1104 ARCH_C29X || \ 1105 ARCH_MPC8536 || \ 1106 ARCH_MPC8540 || \ 1107 ARCH_MPC8541 || \ 1108 ARCH_MPC8544 || \ 1109 ARCH_MPC8548 || \ 1110 ARCH_MPC8555 || \ 1111 ARCH_MPC8560 || \ 1112 ARCH_MPC8568 || \ 1113 ARCH_MPC8569 || \ 1114 ARCH_MPC8572 || \ 1115 ARCH_P1010 || \ 1116 ARCH_P1011 || \ 1117 ARCH_P1020 || \ 1118 ARCH_P1021 || \ 1119 ARCH_P1022 || \ 1120 ARCH_P1024 || \ 1121 ARCH_P1025 || \ 1122 ARCH_P2020 1123 default 0xff600000 if ARCH_P1023 1124 default 0xfe000000 if ARCH_B4420 || \ 1125 ARCH_B4860 || \ 1126 ARCH_P2041 || \ 1127 ARCH_P3041 || \ 1128 ARCH_P4080 || \ 1129 ARCH_P5020 || \ 1130 ARCH_P5040 || \ 1131 ARCH_T1023 || \ 1132 ARCH_T1024 || \ 1133 ARCH_T1040 || \ 1134 ARCH_T1042 || \ 1135 ARCH_T2080 || \ 1136 ARCH_T2081 || \ 1137 ARCH_T4160 || \ 1138 ARCH_T4240 1139 default 0xe0000000 if ARCH_QEMU_E500 1140 help 1141 Default value of CCSRBAR comes from power-on-reset. It 1142 is fixed on each SoC. Some SoCs can have different value 1143 if changed by pre-boot regime. The value here must match 1144 the current value in SoC. If not sure, do not change. 1145 1146config SYS_FSL_ERRATUM_A004468 1147 bool 1148 1149config SYS_FSL_ERRATUM_A004477 1150 bool 1151 1152config SYS_FSL_ERRATUM_A004508 1153 bool 1154 1155config SYS_FSL_ERRATUM_A004580 1156 bool 1157 1158config SYS_FSL_ERRATUM_A004699 1159 bool 1160 1161config SYS_FSL_ERRATUM_A004849 1162 bool 1163 1164config SYS_FSL_ERRATUM_A004510 1165 bool 1166 1167config SYS_FSL_ERRATUM_A004510_SVR_REV 1168 hex 1169 depends on SYS_FSL_ERRATUM_A004510 1170 default 0x20 if ARCH_P4080 1171 default 0x10 1172 1173config SYS_FSL_ERRATUM_A004510_SVR_REV2 1174 hex 1175 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1176 default 0x11 1177 1178config SYS_FSL_ERRATUM_A005125 1179 bool 1180 1181config SYS_FSL_ERRATUM_A005434 1182 bool 1183 1184config SYS_FSL_ERRATUM_A005812 1185 bool 1186 1187config SYS_FSL_ERRATUM_A005871 1188 bool 1189 1190config SYS_FSL_ERRATUM_A006261 1191 bool 1192 1193config SYS_FSL_ERRATUM_A006379 1194 bool 1195 1196config SYS_FSL_ERRATUM_A006384 1197 bool 1198 1199config SYS_FSL_ERRATUM_A006475 1200 bool 1201 1202config SYS_FSL_ERRATUM_A006593 1203 bool 1204 1205config SYS_FSL_ERRATUM_A007075 1206 bool 1207 1208config SYS_FSL_ERRATUM_A007186 1209 bool 1210 1211config SYS_FSL_ERRATUM_A007212 1212 bool 1213 1214config SYS_FSL_ERRATUM_A007815 1215 bool 1216 1217config SYS_FSL_ERRATUM_A007798 1218 bool 1219 1220config SYS_FSL_ERRATUM_A007907 1221 bool 1222 1223config SYS_FSL_ERRATUM_A008044 1224 bool 1225 1226config SYS_FSL_ERRATUM_CPC_A002 1227 bool 1228 1229config SYS_FSL_ERRATUM_CPC_A003 1230 bool 1231 1232config SYS_FSL_ERRATUM_CPU_A003999 1233 bool 1234 1235config SYS_FSL_ERRATUM_ELBC_A001 1236 bool 1237 1238config SYS_FSL_ERRATUM_I2C_A004447 1239 bool 1240 1241config SYS_FSL_A004447_SVR_REV 1242 hex 1243 depends on SYS_FSL_ERRATUM_I2C_A004447 1244 default 0x00 if ARCH_MPC8548 1245 default 0x10 if ARCH_P1010 1246 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1247 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1248 1249config SYS_FSL_ERRATUM_IFC_A002769 1250 bool 1251 1252config SYS_FSL_ERRATUM_IFC_A003399 1253 bool 1254 1255config SYS_FSL_ERRATUM_NMG_CPU_A011 1256 bool 1257 1258config SYS_FSL_ERRATUM_NMG_ETSEC129 1259 bool 1260 1261config SYS_FSL_ERRATUM_NMG_LBC103 1262 bool 1263 1264config SYS_FSL_ERRATUM_P1010_A003549 1265 bool 1266 1267config SYS_FSL_ERRATUM_SATA_A001 1268 bool 1269 1270config SYS_FSL_ERRATUM_SEC_A003571 1271 bool 1272 1273config SYS_FSL_ERRATUM_SRIO_A004034 1274 bool 1275 1276config SYS_FSL_ERRATUM_USB14 1277 bool 1278 1279config SYS_P4080_ERRATUM_CPU22 1280 bool 1281 1282config SYS_P4080_ERRATUM_PCIE_A003 1283 bool 1284 1285config SYS_P4080_ERRATUM_SERDES8 1286 bool 1287 1288config SYS_P4080_ERRATUM_SERDES9 1289 bool 1290 1291config SYS_P4080_ERRATUM_SERDES_A001 1292 bool 1293 1294config SYS_P4080_ERRATUM_SERDES_A005 1295 bool 1296 1297config SYS_FSL_QORIQ_CHASSIS1 1298 bool 1299 1300config SYS_FSL_QORIQ_CHASSIS2 1301 bool 1302 1303config SYS_FSL_NUM_LAWS 1304 int "Number of local access windows" 1305 depends on FSL_LAW 1306 default 32 if ARCH_B4420 || \ 1307 ARCH_B4860 || \ 1308 ARCH_P2041 || \ 1309 ARCH_P3041 || \ 1310 ARCH_P4080 || \ 1311 ARCH_P5020 || \ 1312 ARCH_P5040 || \ 1313 ARCH_T2080 || \ 1314 ARCH_T2081 || \ 1315 ARCH_T4160 || \ 1316 ARCH_T4240 1317 default 16 if ARCH_T1023 || \ 1318 ARCH_T1024 || \ 1319 ARCH_T1040 || \ 1320 ARCH_T1042 1321 default 12 if ARCH_BSC9131 || \ 1322 ARCH_BSC9132 || \ 1323 ARCH_C29X || \ 1324 ARCH_MPC8536 || \ 1325 ARCH_MPC8572 || \ 1326 ARCH_P1010 || \ 1327 ARCH_P1011 || \ 1328 ARCH_P1020 || \ 1329 ARCH_P1021 || \ 1330 ARCH_P1022 || \ 1331 ARCH_P1023 || \ 1332 ARCH_P1024 || \ 1333 ARCH_P1025 || \ 1334 ARCH_P2020 1335 default 10 if ARCH_MPC8544 || \ 1336 ARCH_MPC8548 || \ 1337 ARCH_MPC8568 || \ 1338 ARCH_MPC8569 1339 default 8 if ARCH_MPC8540 || \ 1340 ARCH_MPC8541 || \ 1341 ARCH_MPC8555 || \ 1342 ARCH_MPC8560 1343 help 1344 Number of local access windows. This is fixed per SoC. 1345 If not sure, do not change. 1346 1347config SYS_FSL_THREADS_PER_CORE 1348 int 1349 default 2 if E6500 1350 default 1 1351 1352config SYS_NUM_TLBCAMS 1353 int "Number of TLB CAM entries" 1354 default 64 if E500MC 1355 default 16 1356 help 1357 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1358 16 for other E500 SoCs. 1359 1360config SYS_PPC64 1361 bool 1362 1363config SYS_PPC_E500_USE_DEBUG_TLB 1364 bool 1365 1366config FSL_IFC 1367 bool 1368 1369config FSL_ELBC 1370 bool 1371 1372config SYS_PPC_E500_DEBUG_TLB 1373 int "Temporary TLB entry for external debugger" 1374 depends on SYS_PPC_E500_USE_DEBUG_TLB 1375 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1376 default 1 if ARCH_MPC8536 1377 default 2 if ARCH_MPC8572 || \ 1378 ARCH_P1011 || \ 1379 ARCH_P1020 || \ 1380 ARCH_P1021 || \ 1381 ARCH_P1022 || \ 1382 ARCH_P1024 || \ 1383 ARCH_P1025 || \ 1384 ARCH_P2020 1385 default 3 if ARCH_P1010 || \ 1386 ARCH_BSC9132 || \ 1387 ARCH_C29X 1388 help 1389 Select a temporary TLB entry to be used during boot to work 1390 around limitations in e500v1 and e500v2 external debugger 1391 support. This reduces the portions of the boot code where 1392 breakpoints and single stepping do not work. The value of this 1393 symbol should be set to the TLB1 entry to be used for this 1394 purpose. If unsure, do not change. 1395 1396config SYS_FSL_IFC_CLK_DIV 1397 int "Divider of platform clock" 1398 depends on FSL_IFC 1399 default 2 if ARCH_B4420 || \ 1400 ARCH_B4860 || \ 1401 ARCH_T1024 || \ 1402 ARCH_T1023 || \ 1403 ARCH_T1040 || \ 1404 ARCH_T1042 || \ 1405 ARCH_T4160 || \ 1406 ARCH_T4240 1407 default 1 1408 help 1409 Defines divider of platform clock(clock input to 1410 IFC controller). 1411 1412config SYS_FSL_LBC_CLK_DIV 1413 int "Divider of platform clock" 1414 depends on FSL_ELBC || ARCH_MPC8540 || \ 1415 ARCH_MPC8548 || ARCH_MPC8541 || \ 1416 ARCH_MPC8555 || ARCH_MPC8560 || \ 1417 ARCH_MPC8568 1418 1419 default 2 if ARCH_P2041 || \ 1420 ARCH_P3041 || \ 1421 ARCH_P4080 || \ 1422 ARCH_P5020 || \ 1423 ARCH_P5040 1424 default 1 1425 1426 help 1427 Defines divider of platform clock(clock input to 1428 eLBC controller). 1429 1430source "board/freescale/b4860qds/Kconfig" 1431source "board/freescale/bsc9131rdb/Kconfig" 1432source "board/freescale/bsc9132qds/Kconfig" 1433source "board/freescale/c29xpcie/Kconfig" 1434source "board/freescale/corenet_ds/Kconfig" 1435source "board/freescale/mpc8536ds/Kconfig" 1436source "board/freescale/mpc8541cds/Kconfig" 1437source "board/freescale/mpc8544ds/Kconfig" 1438source "board/freescale/mpc8548cds/Kconfig" 1439source "board/freescale/mpc8555cds/Kconfig" 1440source "board/freescale/mpc8568mds/Kconfig" 1441source "board/freescale/mpc8569mds/Kconfig" 1442source "board/freescale/mpc8572ds/Kconfig" 1443source "board/freescale/p1010rdb/Kconfig" 1444source "board/freescale/p1022ds/Kconfig" 1445source "board/freescale/p1023rdb/Kconfig" 1446source "board/freescale/p1_p2_rdb_pc/Kconfig" 1447source "board/freescale/p1_twr/Kconfig" 1448source "board/freescale/p2041rdb/Kconfig" 1449source "board/freescale/qemu-ppce500/Kconfig" 1450source "board/freescale/t102xqds/Kconfig" 1451source "board/freescale/t102xrdb/Kconfig" 1452source "board/freescale/t1040qds/Kconfig" 1453source "board/freescale/t104xrdb/Kconfig" 1454source "board/freescale/t208xqds/Kconfig" 1455source "board/freescale/t208xrdb/Kconfig" 1456source "board/freescale/t4qds/Kconfig" 1457source "board/freescale/t4rdb/Kconfig" 1458source "board/gdsys/p1022/Kconfig" 1459source "board/keymile/kmp204x/Kconfig" 1460source "board/sbc8548/Kconfig" 1461source "board/socrates/Kconfig" 1462source "board/varisys/cyrus/Kconfig" 1463source "board/xes/xpedite520x/Kconfig" 1464source "board/xes/xpedite537x/Kconfig" 1465source "board/xes/xpedite550x/Kconfig" 1466source "board/Arcturus/ucp1020/Kconfig" 1467 1468endmenu 1469