1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7choice 8 prompt "Target select" 9 optional 10 11config TARGET_SBC8548 12 bool "Support sbc8548" 13 select ARCH_MPC8548 14 15config TARGET_SOCRATES 16 bool "Support socrates" 17 select ARCH_MPC8544 18 19config TARGET_B4420QDS 20 bool "Support B4420QDS" 21 select ARCH_B4420 22 select SUPPORT_SPL 23 select PHYS_64BIT 24 25config TARGET_B4860QDS 26 bool "Support B4860QDS" 27 select ARCH_B4860 28 select SUPPORT_SPL 29 select PHYS_64BIT 30 31config TARGET_BSC9131RDB 32 bool "Support BSC9131RDB" 33 select ARCH_BSC9131 34 select SUPPORT_SPL 35 36config TARGET_BSC9132QDS 37 bool "Support BSC9132QDS" 38 select ARCH_BSC9132 39 select SUPPORT_SPL 40 41config TARGET_C29XPCIE 42 bool "Support C29XPCIE" 43 select ARCH_C29X 44 select SUPPORT_SPL 45 select SUPPORT_TPL 46 select PHYS_64BIT 47 48config TARGET_P3041DS 49 bool "Support P3041DS" 50 select PHYS_64BIT 51 select ARCH_P3041 52 53config TARGET_P4080DS 54 bool "Support P4080DS" 55 select PHYS_64BIT 56 select ARCH_P4080 57 58config TARGET_P5020DS 59 bool "Support P5020DS" 60 select PHYS_64BIT 61 select ARCH_P5020 62 63config TARGET_P5040DS 64 bool "Support P5040DS" 65 select PHYS_64BIT 66 select ARCH_P5040 67 68config TARGET_MPC8536DS 69 bool "Support MPC8536DS" 70 select ARCH_MPC8536 71# Use DDR3 controller with DDR2 DIMMs on this board 72 select SYS_FSL_DDRC_GEN3 73 74config TARGET_MPC8540ADS 75 bool "Support MPC8540ADS" 76 select ARCH_MPC8540 77 78config TARGET_MPC8541CDS 79 bool "Support MPC8541CDS" 80 select ARCH_MPC8541 81 82config TARGET_MPC8544DS 83 bool "Support MPC8544DS" 84 select ARCH_MPC8544 85 86config TARGET_MPC8548CDS 87 bool "Support MPC8548CDS" 88 select ARCH_MPC8548 89 90config TARGET_MPC8555CDS 91 bool "Support MPC8555CDS" 92 select ARCH_MPC8555 93 94config TARGET_MPC8560ADS 95 bool "Support MPC8560ADS" 96 select ARCH_MPC8560 97 98config TARGET_MPC8568MDS 99 bool "Support MPC8568MDS" 100 select ARCH_MPC8568 101 102config TARGET_MPC8569MDS 103 bool "Support MPC8569MDS" 104 select ARCH_MPC8569 105 106config TARGET_MPC8572DS 107 bool "Support MPC8572DS" 108 select ARCH_MPC8572 109# Use DDR3 controller with DDR2 DIMMs on this board 110 select SYS_FSL_DDRC_GEN3 111 112config TARGET_P1010RDB_PA 113 bool "Support P1010RDB_PA" 114 select ARCH_P1010 115 select SUPPORT_SPL 116 select SUPPORT_TPL 117 118config TARGET_P1010RDB_PB 119 bool "Support P1010RDB_PB" 120 select ARCH_P1010 121 select SUPPORT_SPL 122 select SUPPORT_TPL 123 124config TARGET_P1022DS 125 bool "Support P1022DS" 126 select ARCH_P1022 127 select SUPPORT_SPL 128 select SUPPORT_TPL 129 130config TARGET_P1023RDB 131 bool "Support P1023RDB" 132 select ARCH_P1023 133 134config TARGET_P1020MBG 135 bool "Support P1020MBG-PC" 136 select SUPPORT_SPL 137 select SUPPORT_TPL 138 select ARCH_P1020 139 140config TARGET_P1020RDB_PC 141 bool "Support P1020RDB-PC" 142 select SUPPORT_SPL 143 select SUPPORT_TPL 144 select ARCH_P1020 145 146config TARGET_P1020RDB_PD 147 bool "Support P1020RDB-PD" 148 select SUPPORT_SPL 149 select SUPPORT_TPL 150 select ARCH_P1020 151 152config TARGET_P1020UTM 153 bool "Support P1020UTM" 154 select SUPPORT_SPL 155 select SUPPORT_TPL 156 select ARCH_P1020 157 158config TARGET_P1021RDB 159 bool "Support P1021RDB" 160 select SUPPORT_SPL 161 select SUPPORT_TPL 162 select ARCH_P1021 163 164config TARGET_P1024RDB 165 bool "Support P1024RDB" 166 select SUPPORT_SPL 167 select SUPPORT_TPL 168 select ARCH_P1024 169 170config TARGET_P1025RDB 171 bool "Support P1025RDB" 172 select SUPPORT_SPL 173 select SUPPORT_TPL 174 select ARCH_P1025 175 176config TARGET_P2020RDB 177 bool "Support P2020RDB-PC" 178 select SUPPORT_SPL 179 select SUPPORT_TPL 180 select ARCH_P2020 181 182config TARGET_P1_TWR 183 bool "Support p1_twr" 184 select ARCH_P1025 185 186config TARGET_P2041RDB 187 bool "Support P2041RDB" 188 select ARCH_P2041 189 select PHYS_64BIT 190 191config TARGET_QEMU_PPCE500 192 bool "Support qemu-ppce500" 193 select ARCH_QEMU_E500 194 select PHYS_64BIT 195 196config TARGET_T1024QDS 197 bool "Support T1024QDS" 198 select ARCH_T1024 199 select SUPPORT_SPL 200 select PHYS_64BIT 201 202config TARGET_T1023RDB 203 bool "Support T1023RDB" 204 select ARCH_T1023 205 select SUPPORT_SPL 206 select PHYS_64BIT 207 208config TARGET_T1024RDB 209 bool "Support T1024RDB" 210 select ARCH_T1024 211 select SUPPORT_SPL 212 select PHYS_64BIT 213 214config TARGET_T1040QDS 215 bool "Support T1040QDS" 216 select ARCH_T1040 217 select PHYS_64BIT 218 219config TARGET_T1040RDB 220 bool "Support T1040RDB" 221 select ARCH_T1040 222 select SUPPORT_SPL 223 select PHYS_64BIT 224 225config TARGET_T1040D4RDB 226 bool "Support T1040D4RDB" 227 select ARCH_T1040 228 select SUPPORT_SPL 229 select PHYS_64BIT 230 231config TARGET_T1042RDB 232 bool "Support T1042RDB" 233 select ARCH_T1042 234 select SUPPORT_SPL 235 select PHYS_64BIT 236 237config TARGET_T1042D4RDB 238 bool "Support T1042D4RDB" 239 select ARCH_T1042 240 select SUPPORT_SPL 241 select PHYS_64BIT 242 243config TARGET_T1042RDB_PI 244 bool "Support T1042RDB_PI" 245 select ARCH_T1042 246 select SUPPORT_SPL 247 select PHYS_64BIT 248 249config TARGET_T2080QDS 250 bool "Support T2080QDS" 251 select ARCH_T2080 252 select SUPPORT_SPL 253 select PHYS_64BIT 254 255config TARGET_T2080RDB 256 bool "Support T2080RDB" 257 select ARCH_T2080 258 select SUPPORT_SPL 259 select PHYS_64BIT 260 261config TARGET_T2081QDS 262 bool "Support T2081QDS" 263 select ARCH_T2081 264 select SUPPORT_SPL 265 select PHYS_64BIT 266 267config TARGET_T4160QDS 268 bool "Support T4160QDS" 269 select ARCH_T4160 270 select SUPPORT_SPL 271 select PHYS_64BIT 272 273config TARGET_T4160RDB 274 bool "Support T4160RDB" 275 select ARCH_T4160 276 select SUPPORT_SPL 277 select PHYS_64BIT 278 279config TARGET_T4240QDS 280 bool "Support T4240QDS" 281 select ARCH_T4240 282 select SUPPORT_SPL 283 select PHYS_64BIT 284 285config TARGET_T4240RDB 286 bool "Support T4240RDB" 287 select ARCH_T4240 288 select SUPPORT_SPL 289 select PHYS_64BIT 290 291config TARGET_CONTROLCENTERD 292 bool "Support controlcenterd" 293 select ARCH_P1022 294 295config TARGET_KMP204X 296 bool "Support kmp204x" 297 select ARCH_P2041 298 select PHYS_64BIT 299 300config TARGET_XPEDITE520X 301 bool "Support xpedite520x" 302 select ARCH_MPC8548 303 304config TARGET_XPEDITE537X 305 bool "Support xpedite537x" 306 select ARCH_MPC8572 307# Use DDR3 controller with DDR2 DIMMs on this board 308 select SYS_FSL_DDRC_GEN3 309 310config TARGET_XPEDITE550X 311 bool "Support xpedite550x" 312 select ARCH_P2020 313 314config TARGET_UCP1020 315 bool "Support uCP1020" 316 select ARCH_P1020 317 318config TARGET_CYRUS_P5020 319 bool "Support Varisys Cyrus P5020" 320 select ARCH_P5020 321 select PHYS_64BIT 322 323config TARGET_CYRUS_P5040 324 bool "Support Varisys Cyrus P5040" 325 select ARCH_P5040 326 select PHYS_64BIT 327 328endchoice 329 330config ARCH_B4420 331 bool 332 select E500MC 333 select E6500 334 select FSL_LAW 335 select SYS_FSL_DDR_VER_47 336 select SYS_FSL_ERRATUM_A004477 337 select SYS_FSL_ERRATUM_A005871 338 select SYS_FSL_ERRATUM_A006379 339 select SYS_FSL_ERRATUM_A006384 340 select SYS_FSL_ERRATUM_A006475 341 select SYS_FSL_ERRATUM_A006593 342 select SYS_FSL_ERRATUM_A007075 343 select SYS_FSL_ERRATUM_A007186 344 select SYS_FSL_ERRATUM_A007212 345 select SYS_FSL_ERRATUM_A009942 346 select SYS_FSL_HAS_DDR3 347 select SYS_FSL_HAS_SEC 348 select SYS_FSL_QORIQ_CHASSIS2 349 select SYS_FSL_SEC_BE 350 select SYS_FSL_SEC_COMPAT_4 351 select SYS_PPC64 352 353config ARCH_B4860 354 bool 355 select E500MC 356 select E6500 357 select FSL_LAW 358 select SYS_FSL_DDR_VER_47 359 select SYS_FSL_ERRATUM_A004477 360 select SYS_FSL_ERRATUM_A005871 361 select SYS_FSL_ERRATUM_A006379 362 select SYS_FSL_ERRATUM_A006384 363 select SYS_FSL_ERRATUM_A006475 364 select SYS_FSL_ERRATUM_A006593 365 select SYS_FSL_ERRATUM_A007075 366 select SYS_FSL_ERRATUM_A007186 367 select SYS_FSL_ERRATUM_A007212 368 select SYS_FSL_ERRATUM_A007907 369 select SYS_FSL_ERRATUM_A009942 370 select SYS_FSL_HAS_DDR3 371 select SYS_FSL_HAS_SEC 372 select SYS_FSL_QORIQ_CHASSIS2 373 select SYS_FSL_SEC_BE 374 select SYS_FSL_SEC_COMPAT_4 375 select SYS_PPC64 376 377config ARCH_BSC9131 378 bool 379 select FSL_LAW 380 select SYS_FSL_DDR_VER_44 381 select SYS_FSL_ERRATUM_A004477 382 select SYS_FSL_ERRATUM_A005125 383 select SYS_FSL_ERRATUM_ESDHC111 384 select SYS_FSL_HAS_DDR3 385 select SYS_FSL_HAS_SEC 386 select SYS_FSL_SEC_BE 387 select SYS_FSL_SEC_COMPAT_4 388 389config ARCH_BSC9132 390 bool 391 select FSL_LAW 392 select SYS_FSL_DDR_VER_46 393 select SYS_FSL_ERRATUM_A004477 394 select SYS_FSL_ERRATUM_A005125 395 select SYS_FSL_ERRATUM_A005434 396 select SYS_FSL_ERRATUM_ESDHC111 397 select SYS_FSL_ERRATUM_I2C_A004447 398 select SYS_FSL_ERRATUM_IFC_A002769 399 select SYS_FSL_HAS_DDR3 400 select SYS_FSL_HAS_SEC 401 select SYS_FSL_SEC_BE 402 select SYS_FSL_SEC_COMPAT_4 403 select SYS_PPC_E500_USE_DEBUG_TLB 404 405config ARCH_C29X 406 bool 407 select FSL_LAW 408 select SYS_FSL_DDR_VER_46 409 select SYS_FSL_ERRATUM_A005125 410 select SYS_FSL_ERRATUM_ESDHC111 411 select SYS_FSL_HAS_DDR3 412 select SYS_FSL_HAS_SEC 413 select SYS_FSL_SEC_BE 414 select SYS_FSL_SEC_COMPAT_6 415 select SYS_PPC_E500_USE_DEBUG_TLB 416 417config ARCH_MPC8536 418 bool 419 select FSL_LAW 420 select SYS_FSL_ERRATUM_A004508 421 select SYS_FSL_ERRATUM_A005125 422 select SYS_FSL_HAS_DDR2 423 select SYS_FSL_HAS_DDR3 424 select SYS_FSL_HAS_SEC 425 select SYS_FSL_SEC_BE 426 select SYS_FSL_SEC_COMPAT_2 427 select SYS_PPC_E500_USE_DEBUG_TLB 428 429config ARCH_MPC8540 430 bool 431 select FSL_LAW 432 select SYS_FSL_HAS_DDR1 433 434config ARCH_MPC8541 435 bool 436 select FSL_LAW 437 select SYS_FSL_HAS_DDR1 438 select SYS_FSL_HAS_SEC 439 select SYS_FSL_SEC_BE 440 select SYS_FSL_SEC_COMPAT_2 441 442config ARCH_MPC8544 443 bool 444 select FSL_LAW 445 select SYS_FSL_ERRATUM_A005125 446 select SYS_FSL_HAS_DDR2 447 select SYS_FSL_HAS_SEC 448 select SYS_FSL_SEC_BE 449 select SYS_FSL_SEC_COMPAT_2 450 select SYS_PPC_E500_USE_DEBUG_TLB 451 452config ARCH_MPC8548 453 bool 454 select FSL_LAW 455 select SYS_FSL_ERRATUM_A005125 456 select SYS_FSL_ERRATUM_NMG_DDR120 457 select SYS_FSL_ERRATUM_NMG_LBC103 458 select SYS_FSL_ERRATUM_NMG_ETSEC129 459 select SYS_FSL_ERRATUM_I2C_A004447 460 select SYS_FSL_HAS_DDR2 461 select SYS_FSL_HAS_DDR1 462 select SYS_FSL_HAS_SEC 463 select SYS_FSL_SEC_BE 464 select SYS_FSL_SEC_COMPAT_2 465 select SYS_PPC_E500_USE_DEBUG_TLB 466 467config ARCH_MPC8555 468 bool 469 select FSL_LAW 470 select SYS_FSL_HAS_DDR1 471 select SYS_FSL_HAS_SEC 472 select SYS_FSL_SEC_BE 473 select SYS_FSL_SEC_COMPAT_2 474 475config ARCH_MPC8560 476 bool 477 select FSL_LAW 478 select SYS_FSL_HAS_DDR1 479 480config ARCH_MPC8568 481 bool 482 select FSL_LAW 483 select SYS_FSL_HAS_DDR2 484 select SYS_FSL_HAS_SEC 485 select SYS_FSL_SEC_BE 486 select SYS_FSL_SEC_COMPAT_2 487 488config ARCH_MPC8569 489 bool 490 select FSL_LAW 491 select SYS_FSL_ERRATUM_A004508 492 select SYS_FSL_ERRATUM_A005125 493 select SYS_FSL_HAS_DDR3 494 select SYS_FSL_HAS_SEC 495 select SYS_FSL_SEC_BE 496 select SYS_FSL_SEC_COMPAT_2 497 498config ARCH_MPC8572 499 bool 500 select FSL_LAW 501 select SYS_FSL_ERRATUM_A004508 502 select SYS_FSL_ERRATUM_A005125 503 select SYS_FSL_ERRATUM_DDR_115 504 select SYS_FSL_ERRATUM_DDR111_DDR134 505 select SYS_FSL_HAS_DDR2 506 select SYS_FSL_HAS_DDR3 507 select SYS_FSL_HAS_SEC 508 select SYS_FSL_SEC_BE 509 select SYS_FSL_SEC_COMPAT_2 510 select SYS_PPC_E500_USE_DEBUG_TLB 511 512config ARCH_P1010 513 bool 514 select FSL_LAW 515 select SYS_FSL_ERRATUM_A004477 516 select SYS_FSL_ERRATUM_A004508 517 select SYS_FSL_ERRATUM_A005125 518 select SYS_FSL_ERRATUM_A006261 519 select SYS_FSL_ERRATUM_A007075 520 select SYS_FSL_ERRATUM_ESDHC111 521 select SYS_FSL_ERRATUM_I2C_A004447 522 select SYS_FSL_ERRATUM_IFC_A002769 523 select SYS_FSL_ERRATUM_P1010_A003549 524 select SYS_FSL_ERRATUM_SEC_A003571 525 select SYS_FSL_ERRATUM_IFC_A003399 526 select SYS_FSL_HAS_DDR3 527 select SYS_FSL_HAS_SEC 528 select SYS_FSL_SEC_BE 529 select SYS_FSL_SEC_COMPAT_4 530 select SYS_PPC_E500_USE_DEBUG_TLB 531 532config ARCH_P1011 533 bool 534 select FSL_LAW 535 select SYS_FSL_ERRATUM_A004508 536 select SYS_FSL_ERRATUM_A005125 537 select SYS_FSL_ERRATUM_ELBC_A001 538 select SYS_FSL_ERRATUM_ESDHC111 539 select SYS_FSL_HAS_DDR3 540 select SYS_FSL_HAS_SEC 541 select SYS_FSL_SEC_BE 542 select SYS_FSL_SEC_COMPAT_2 543 select SYS_PPC_E500_USE_DEBUG_TLB 544 545config ARCH_P1020 546 bool 547 select FSL_LAW 548 select SYS_FSL_ERRATUM_A004508 549 select SYS_FSL_ERRATUM_A005125 550 select SYS_FSL_ERRATUM_ELBC_A001 551 select SYS_FSL_ERRATUM_ESDHC111 552 select SYS_FSL_HAS_DDR3 553 select SYS_FSL_HAS_SEC 554 select SYS_FSL_SEC_BE 555 select SYS_FSL_SEC_COMPAT_2 556 select SYS_PPC_E500_USE_DEBUG_TLB 557 558config ARCH_P1021 559 bool 560 select FSL_LAW 561 select SYS_FSL_ERRATUM_A004508 562 select SYS_FSL_ERRATUM_A005125 563 select SYS_FSL_ERRATUM_ELBC_A001 564 select SYS_FSL_ERRATUM_ESDHC111 565 select SYS_FSL_HAS_DDR3 566 select SYS_FSL_HAS_SEC 567 select SYS_FSL_SEC_BE 568 select SYS_FSL_SEC_COMPAT_2 569 select SYS_PPC_E500_USE_DEBUG_TLB 570 571config ARCH_P1022 572 bool 573 select FSL_LAW 574 select SYS_FSL_ERRATUM_A004477 575 select SYS_FSL_ERRATUM_A004508 576 select SYS_FSL_ERRATUM_A005125 577 select SYS_FSL_ERRATUM_ELBC_A001 578 select SYS_FSL_ERRATUM_ESDHC111 579 select SYS_FSL_ERRATUM_SATA_A001 580 select SYS_FSL_HAS_DDR3 581 select SYS_FSL_HAS_SEC 582 select SYS_FSL_SEC_BE 583 select SYS_FSL_SEC_COMPAT_2 584 select SYS_PPC_E500_USE_DEBUG_TLB 585 586config ARCH_P1023 587 bool 588 select FSL_LAW 589 select SYS_FSL_ERRATUM_A004508 590 select SYS_FSL_ERRATUM_A005125 591 select SYS_FSL_ERRATUM_I2C_A004447 592 select SYS_FSL_HAS_DDR3 593 select SYS_FSL_HAS_SEC 594 select SYS_FSL_SEC_BE 595 select SYS_FSL_SEC_COMPAT_4 596 597config ARCH_P1024 598 bool 599 select FSL_LAW 600 select SYS_FSL_ERRATUM_A004508 601 select SYS_FSL_ERRATUM_A005125 602 select SYS_FSL_ERRATUM_ELBC_A001 603 select SYS_FSL_ERRATUM_ESDHC111 604 select SYS_FSL_HAS_DDR3 605 select SYS_FSL_HAS_SEC 606 select SYS_FSL_SEC_BE 607 select SYS_FSL_SEC_COMPAT_2 608 select SYS_PPC_E500_USE_DEBUG_TLB 609 610config ARCH_P1025 611 bool 612 select FSL_LAW 613 select SYS_FSL_ERRATUM_A004508 614 select SYS_FSL_ERRATUM_A005125 615 select SYS_FSL_ERRATUM_ELBC_A001 616 select SYS_FSL_ERRATUM_ESDHC111 617 select SYS_FSL_HAS_DDR3 618 select SYS_FSL_HAS_SEC 619 select SYS_FSL_SEC_BE 620 select SYS_FSL_SEC_COMPAT_2 621 select SYS_PPC_E500_USE_DEBUG_TLB 622 623config ARCH_P2020 624 bool 625 select FSL_LAW 626 select SYS_FSL_ERRATUM_A004477 627 select SYS_FSL_ERRATUM_A004508 628 select SYS_FSL_ERRATUM_A005125 629 select SYS_FSL_ERRATUM_ESDHC111 630 select SYS_FSL_ERRATUM_ESDHC_A001 631 select SYS_FSL_HAS_DDR3 632 select SYS_FSL_HAS_SEC 633 select SYS_FSL_SEC_BE 634 select SYS_FSL_SEC_COMPAT_2 635 select SYS_PPC_E500_USE_DEBUG_TLB 636 637config ARCH_P2041 638 bool 639 select E500MC 640 select FSL_LAW 641 select SYS_FSL_ERRATUM_A004510 642 select SYS_FSL_ERRATUM_A004849 643 select SYS_FSL_ERRATUM_A006261 644 select SYS_FSL_ERRATUM_CPU_A003999 645 select SYS_FSL_ERRATUM_DDR_A003 646 select SYS_FSL_ERRATUM_DDR_A003474 647 select SYS_FSL_ERRATUM_ESDHC111 648 select SYS_FSL_ERRATUM_I2C_A004447 649 select SYS_FSL_ERRATUM_NMG_CPU_A011 650 select SYS_FSL_ERRATUM_SRIO_A004034 651 select SYS_FSL_ERRATUM_USB14 652 select SYS_FSL_HAS_DDR3 653 select SYS_FSL_HAS_SEC 654 select SYS_FSL_QORIQ_CHASSIS1 655 select SYS_FSL_SEC_BE 656 select SYS_FSL_SEC_COMPAT_4 657 658config ARCH_P3041 659 bool 660 select E500MC 661 select FSL_LAW 662 select SYS_FSL_DDR_VER_44 663 select SYS_FSL_ERRATUM_A004510 664 select SYS_FSL_ERRATUM_A004849 665 select SYS_FSL_ERRATUM_A005812 666 select SYS_FSL_ERRATUM_A006261 667 select SYS_FSL_ERRATUM_CPU_A003999 668 select SYS_FSL_ERRATUM_DDR_A003 669 select SYS_FSL_ERRATUM_DDR_A003474 670 select SYS_FSL_ERRATUM_ESDHC111 671 select SYS_FSL_ERRATUM_I2C_A004447 672 select SYS_FSL_ERRATUM_NMG_CPU_A011 673 select SYS_FSL_ERRATUM_SRIO_A004034 674 select SYS_FSL_ERRATUM_USB14 675 select SYS_FSL_HAS_DDR3 676 select SYS_FSL_HAS_SEC 677 select SYS_FSL_QORIQ_CHASSIS1 678 select SYS_FSL_SEC_BE 679 select SYS_FSL_SEC_COMPAT_4 680 681config ARCH_P4080 682 bool 683 select E500MC 684 select FSL_LAW 685 select SYS_FSL_DDR_VER_44 686 select SYS_FSL_ERRATUM_A004510 687 select SYS_FSL_ERRATUM_A004580 688 select SYS_FSL_ERRATUM_A004849 689 select SYS_FSL_ERRATUM_A005812 690 select SYS_FSL_ERRATUM_A007075 691 select SYS_FSL_ERRATUM_CPC_A002 692 select SYS_FSL_ERRATUM_CPC_A003 693 select SYS_FSL_ERRATUM_CPU_A003999 694 select SYS_FSL_ERRATUM_DDR_A003 695 select SYS_FSL_ERRATUM_DDR_A003474 696 select SYS_FSL_ERRATUM_ELBC_A001 697 select SYS_FSL_ERRATUM_ESDHC111 698 select SYS_FSL_ERRATUM_ESDHC13 699 select SYS_FSL_ERRATUM_ESDHC135 700 select SYS_FSL_ERRATUM_I2C_A004447 701 select SYS_FSL_ERRATUM_NMG_CPU_A011 702 select SYS_FSL_ERRATUM_SRIO_A004034 703 select SYS_P4080_ERRATUM_CPU22 704 select SYS_P4080_ERRATUM_PCIE_A003 705 select SYS_P4080_ERRATUM_SERDES8 706 select SYS_P4080_ERRATUM_SERDES9 707 select SYS_P4080_ERRATUM_SERDES_A001 708 select SYS_P4080_ERRATUM_SERDES_A005 709 select SYS_FSL_HAS_DDR3 710 select SYS_FSL_HAS_SEC 711 select SYS_FSL_QORIQ_CHASSIS1 712 select SYS_FSL_SEC_BE 713 select SYS_FSL_SEC_COMPAT_4 714 715config ARCH_P5020 716 bool 717 select E500MC 718 select FSL_LAW 719 select SYS_FSL_DDR_VER_44 720 select SYS_FSL_ERRATUM_A004510 721 select SYS_FSL_ERRATUM_A006261 722 select SYS_FSL_ERRATUM_DDR_A003 723 select SYS_FSL_ERRATUM_DDR_A003474 724 select SYS_FSL_ERRATUM_ESDHC111 725 select SYS_FSL_ERRATUM_I2C_A004447 726 select SYS_FSL_ERRATUM_SRIO_A004034 727 select SYS_FSL_ERRATUM_USB14 728 select SYS_FSL_HAS_DDR3 729 select SYS_FSL_HAS_SEC 730 select SYS_FSL_QORIQ_CHASSIS1 731 select SYS_FSL_SEC_BE 732 select SYS_FSL_SEC_COMPAT_4 733 select SYS_PPC64 734 735config ARCH_P5040 736 bool 737 select E500MC 738 select FSL_LAW 739 select SYS_FSL_DDR_VER_44 740 select SYS_FSL_ERRATUM_A004510 741 select SYS_FSL_ERRATUM_A004699 742 select SYS_FSL_ERRATUM_A005812 743 select SYS_FSL_ERRATUM_A006261 744 select SYS_FSL_ERRATUM_DDR_A003 745 select SYS_FSL_ERRATUM_DDR_A003474 746 select SYS_FSL_ERRATUM_ESDHC111 747 select SYS_FSL_ERRATUM_USB14 748 select SYS_FSL_HAS_DDR3 749 select SYS_FSL_HAS_SEC 750 select SYS_FSL_QORIQ_CHASSIS1 751 select SYS_FSL_SEC_BE 752 select SYS_FSL_SEC_COMPAT_4 753 select SYS_PPC64 754 755config ARCH_QEMU_E500 756 bool 757 758config ARCH_T1023 759 bool 760 select E500MC 761 select FSL_LAW 762 select SYS_FSL_DDR_VER_50 763 select SYS_FSL_ERRATUM_A008378 764 select SYS_FSL_ERRATUM_A009663 765 select SYS_FSL_ERRATUM_A009942 766 select SYS_FSL_ERRATUM_ESDHC111 767 select SYS_FSL_HAS_DDR3 768 select SYS_FSL_HAS_DDR4 769 select SYS_FSL_HAS_SEC 770 select SYS_FSL_QORIQ_CHASSIS2 771 select SYS_FSL_SEC_BE 772 select SYS_FSL_SEC_COMPAT_5 773 774config ARCH_T1024 775 bool 776 select E500MC 777 select FSL_LAW 778 select SYS_FSL_DDR_VER_50 779 select SYS_FSL_ERRATUM_A008378 780 select SYS_FSL_ERRATUM_A009663 781 select SYS_FSL_ERRATUM_A009942 782 select SYS_FSL_ERRATUM_ESDHC111 783 select SYS_FSL_HAS_DDR3 784 select SYS_FSL_HAS_DDR4 785 select SYS_FSL_HAS_SEC 786 select SYS_FSL_QORIQ_CHASSIS2 787 select SYS_FSL_SEC_BE 788 select SYS_FSL_SEC_COMPAT_5 789 790config ARCH_T1040 791 bool 792 select E500MC 793 select FSL_LAW 794 select SYS_FSL_DDR_VER_50 795 select SYS_FSL_ERRATUM_A008044 796 select SYS_FSL_ERRATUM_A008378 797 select SYS_FSL_ERRATUM_A009663 798 select SYS_FSL_ERRATUM_A009942 799 select SYS_FSL_ERRATUM_ESDHC111 800 select SYS_FSL_HAS_DDR3 801 select SYS_FSL_HAS_DDR4 802 select SYS_FSL_HAS_SEC 803 select SYS_FSL_QORIQ_CHASSIS2 804 select SYS_FSL_SEC_BE 805 select SYS_FSL_SEC_COMPAT_5 806 807config ARCH_T1042 808 bool 809 select E500MC 810 select FSL_LAW 811 select SYS_FSL_DDR_VER_50 812 select SYS_FSL_ERRATUM_A008044 813 select SYS_FSL_ERRATUM_A008378 814 select SYS_FSL_ERRATUM_A009663 815 select SYS_FSL_ERRATUM_A009942 816 select SYS_FSL_ERRATUM_ESDHC111 817 select SYS_FSL_HAS_DDR3 818 select SYS_FSL_HAS_DDR4 819 select SYS_FSL_HAS_SEC 820 select SYS_FSL_QORIQ_CHASSIS2 821 select SYS_FSL_SEC_BE 822 select SYS_FSL_SEC_COMPAT_5 823 824config ARCH_T2080 825 bool 826 select E500MC 827 select E6500 828 select FSL_LAW 829 select SYS_FSL_DDR_VER_47 830 select SYS_FSL_ERRATUM_A006379 831 select SYS_FSL_ERRATUM_A006593 832 select SYS_FSL_ERRATUM_A007186 833 select SYS_FSL_ERRATUM_A007212 834 select SYS_FSL_ERRATUM_A007907 835 select SYS_FSL_ERRATUM_A009942 836 select SYS_FSL_ERRATUM_ESDHC111 837 select SYS_FSL_HAS_DDR3 838 select SYS_FSL_HAS_SEC 839 select SYS_FSL_QORIQ_CHASSIS2 840 select SYS_FSL_SEC_BE 841 select SYS_FSL_SEC_COMPAT_4 842 select SYS_PPC64 843 844config ARCH_T2081 845 bool 846 select E500MC 847 select E6500 848 select FSL_LAW 849 select SYS_FSL_DDR_VER_47 850 select SYS_FSL_ERRATUM_A006379 851 select SYS_FSL_ERRATUM_A006593 852 select SYS_FSL_ERRATUM_A007186 853 select SYS_FSL_ERRATUM_A007212 854 select SYS_FSL_ERRATUM_A009942 855 select SYS_FSL_ERRATUM_ESDHC111 856 select SYS_FSL_HAS_DDR3 857 select SYS_FSL_HAS_SEC 858 select SYS_FSL_QORIQ_CHASSIS2 859 select SYS_FSL_SEC_BE 860 select SYS_FSL_SEC_COMPAT_4 861 select SYS_PPC64 862 863config ARCH_T4160 864 bool 865 select E500MC 866 select E6500 867 select FSL_LAW 868 select SYS_FSL_DDR_VER_47 869 select SYS_FSL_ERRATUM_A004468 870 select SYS_FSL_ERRATUM_A005871 871 select SYS_FSL_ERRATUM_A006379 872 select SYS_FSL_ERRATUM_A006593 873 select SYS_FSL_ERRATUM_A007186 874 select SYS_FSL_ERRATUM_A007798 875 select SYS_FSL_ERRATUM_A009942 876 select SYS_FSL_HAS_DDR3 877 select SYS_FSL_HAS_SEC 878 select SYS_FSL_QORIQ_CHASSIS2 879 select SYS_FSL_SEC_BE 880 select SYS_FSL_SEC_COMPAT_4 881 select SYS_PPC64 882 883config ARCH_T4240 884 bool 885 select E500MC 886 select E6500 887 select FSL_LAW 888 select SYS_FSL_DDR_VER_47 889 select SYS_FSL_ERRATUM_A004468 890 select SYS_FSL_ERRATUM_A005871 891 select SYS_FSL_ERRATUM_A006261 892 select SYS_FSL_ERRATUM_A006379 893 select SYS_FSL_ERRATUM_A006593 894 select SYS_FSL_ERRATUM_A007186 895 select SYS_FSL_ERRATUM_A007798 896 select SYS_FSL_ERRATUM_A007907 897 select SYS_FSL_ERRATUM_A009942 898 select SYS_FSL_HAS_DDR3 899 select SYS_FSL_HAS_SEC 900 select SYS_FSL_QORIQ_CHASSIS2 901 select SYS_FSL_SEC_BE 902 select SYS_FSL_SEC_COMPAT_4 903 select SYS_PPC64 904 905config BOOKE 906 bool 907 default y 908 909config E500 910 bool 911 default y 912 help 913 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 914 915config E500MC 916 bool 917 help 918 Enble PowerPC E500MC core 919 920config E6500 921 bool 922 help 923 Enable PowerPC E6500 core 924 925config FSL_LAW 926 bool 927 help 928 Use Freescale common code for Local Access Window 929 930config SECURE_BOOT 931 bool "Secure Boot" 932 help 933 Enable Freescale Secure Boot feature. Normally selected 934 by defconfig. If unsure, do not change. 935 936config MAX_CPUS 937 int "Maximum number of CPUs permitted for MPC85xx" 938 default 12 if ARCH_T4240 939 default 8 if ARCH_P4080 || \ 940 ARCH_T4160 941 default 4 if ARCH_B4860 || \ 942 ARCH_P2041 || \ 943 ARCH_P3041 || \ 944 ARCH_P5040 || \ 945 ARCH_T1040 || \ 946 ARCH_T1042 || \ 947 ARCH_T2080 || \ 948 ARCH_T2081 949 default 2 if ARCH_B4420 || \ 950 ARCH_BSC9132 || \ 951 ARCH_MPC8572 || \ 952 ARCH_P1020 || \ 953 ARCH_P1021 || \ 954 ARCH_P1022 || \ 955 ARCH_P1023 || \ 956 ARCH_P1024 || \ 957 ARCH_P1025 || \ 958 ARCH_P2020 || \ 959 ARCH_P5020 || \ 960 ARCH_T1023 || \ 961 ARCH_T1024 962 default 1 963 help 964 Set this number to the maximum number of possible CPUs in the SoC. 965 SoCs may have multiple clusters with each cluster may have multiple 966 ports. If some ports are reserved but higher ports are used for 967 cores, count the reserved ports. This will allocate enough memory 968 in spin table to properly handle all cores. 969 970config SYS_CCSRBAR_DEFAULT 971 hex "Default CCSRBAR address" 972 default 0xff700000 if ARCH_BSC9131 || \ 973 ARCH_BSC9132 || \ 974 ARCH_C29X || \ 975 ARCH_MPC8536 || \ 976 ARCH_MPC8540 || \ 977 ARCH_MPC8541 || \ 978 ARCH_MPC8544 || \ 979 ARCH_MPC8548 || \ 980 ARCH_MPC8555 || \ 981 ARCH_MPC8560 || \ 982 ARCH_MPC8568 || \ 983 ARCH_MPC8569 || \ 984 ARCH_MPC8572 || \ 985 ARCH_P1010 || \ 986 ARCH_P1011 || \ 987 ARCH_P1020 || \ 988 ARCH_P1021 || \ 989 ARCH_P1022 || \ 990 ARCH_P1024 || \ 991 ARCH_P1025 || \ 992 ARCH_P2020 993 default 0xff600000 if ARCH_P1023 994 default 0xfe000000 if ARCH_B4420 || \ 995 ARCH_B4860 || \ 996 ARCH_P2041 || \ 997 ARCH_P3041 || \ 998 ARCH_P4080 || \ 999 ARCH_P5020 || \ 1000 ARCH_P5040 || \ 1001 ARCH_T1023 || \ 1002 ARCH_T1024 || \ 1003 ARCH_T1040 || \ 1004 ARCH_T1042 || \ 1005 ARCH_T2080 || \ 1006 ARCH_T2081 || \ 1007 ARCH_T4160 || \ 1008 ARCH_T4240 1009 default 0xe0000000 if ARCH_QEMU_E500 1010 help 1011 Default value of CCSRBAR comes from power-on-reset. It 1012 is fixed on each SoC. Some SoCs can have different value 1013 if changed by pre-boot regime. The value here must match 1014 the current value in SoC. If not sure, do not change. 1015 1016config SYS_FSL_ERRATUM_A004468 1017 bool 1018 1019config SYS_FSL_ERRATUM_A004477 1020 bool 1021 1022config SYS_FSL_ERRATUM_A004508 1023 bool 1024 1025config SYS_FSL_ERRATUM_A004580 1026 bool 1027 1028config SYS_FSL_ERRATUM_A004699 1029 bool 1030 1031config SYS_FSL_ERRATUM_A004849 1032 bool 1033 1034config SYS_FSL_ERRATUM_A004510 1035 bool 1036 1037config SYS_FSL_ERRATUM_A004510_SVR_REV 1038 hex 1039 depends on SYS_FSL_ERRATUM_A004510 1040 default 0x20 if ARCH_P4080 1041 default 0x10 1042 1043config SYS_FSL_ERRATUM_A004510_SVR_REV2 1044 hex 1045 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1046 default 0x11 1047 1048config SYS_FSL_ERRATUM_A005125 1049 bool 1050 1051config SYS_FSL_ERRATUM_A005434 1052 bool 1053 1054config SYS_FSL_ERRATUM_A005812 1055 bool 1056 1057config SYS_FSL_ERRATUM_A005871 1058 bool 1059 1060config SYS_FSL_ERRATUM_A006261 1061 bool 1062 1063config SYS_FSL_ERRATUM_A006379 1064 bool 1065 1066config SYS_FSL_ERRATUM_A006384 1067 bool 1068 1069config SYS_FSL_ERRATUM_A006475 1070 bool 1071 1072config SYS_FSL_ERRATUM_A006593 1073 bool 1074 1075config SYS_FSL_ERRATUM_A007075 1076 bool 1077 1078config SYS_FSL_ERRATUM_A007186 1079 bool 1080 1081config SYS_FSL_ERRATUM_A007212 1082 bool 1083 1084config SYS_FSL_ERRATUM_A007798 1085 bool 1086 1087config SYS_FSL_ERRATUM_A007907 1088 bool 1089 1090config SYS_FSL_ERRATUM_A008044 1091 bool 1092 1093config SYS_FSL_ERRATUM_CPC_A002 1094 bool 1095 1096config SYS_FSL_ERRATUM_CPC_A003 1097 bool 1098 1099config SYS_FSL_ERRATUM_CPU_A003999 1100 bool 1101 1102config SYS_FSL_ERRATUM_ELBC_A001 1103 bool 1104 1105config SYS_FSL_ERRATUM_I2C_A004447 1106 bool 1107 1108config SYS_FSL_A004447_SVR_REV 1109 hex 1110 depends on SYS_FSL_ERRATUM_I2C_A004447 1111 default 0x00 if ARCH_MPC8548 1112 default 0x10 if ARCH_P1010 1113 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1114 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1115 1116config SYS_FSL_ERRATUM_IFC_A002769 1117 bool 1118 1119config SYS_FSL_ERRATUM_IFC_A003399 1120 bool 1121 1122config SYS_FSL_ERRATUM_NMG_CPU_A011 1123 bool 1124 1125config SYS_FSL_ERRATUM_NMG_ETSEC129 1126 bool 1127 1128config SYS_FSL_ERRATUM_NMG_LBC103 1129 bool 1130 1131config SYS_FSL_ERRATUM_P1010_A003549 1132 bool 1133 1134config SYS_FSL_ERRATUM_SATA_A001 1135 bool 1136 1137config SYS_FSL_ERRATUM_SEC_A003571 1138 bool 1139 1140config SYS_FSL_ERRATUM_SRIO_A004034 1141 bool 1142 1143config SYS_FSL_ERRATUM_USB14 1144 bool 1145 1146config SYS_P4080_ERRATUM_CPU22 1147 bool 1148 1149config SYS_P4080_ERRATUM_PCIE_A003 1150 bool 1151 1152config SYS_P4080_ERRATUM_SERDES8 1153 bool 1154 1155config SYS_P4080_ERRATUM_SERDES9 1156 bool 1157 1158config SYS_P4080_ERRATUM_SERDES_A001 1159 bool 1160 1161config SYS_P4080_ERRATUM_SERDES_A005 1162 bool 1163 1164config SYS_FSL_QORIQ_CHASSIS1 1165 bool 1166 1167config SYS_FSL_QORIQ_CHASSIS2 1168 bool 1169 1170config SYS_FSL_NUM_LAWS 1171 int "Number of local access windows" 1172 depends on FSL_LAW 1173 default 32 if ARCH_B4420 || \ 1174 ARCH_B4860 || \ 1175 ARCH_P2041 || \ 1176 ARCH_P3041 || \ 1177 ARCH_P4080 || \ 1178 ARCH_P5020 || \ 1179 ARCH_P5040 || \ 1180 ARCH_T2080 || \ 1181 ARCH_T2081 || \ 1182 ARCH_T4160 || \ 1183 ARCH_T4240 1184 default 16 if ARCH_T1023 || \ 1185 ARCH_T1024 || \ 1186 ARCH_T1040 || \ 1187 ARCH_T1042 1188 default 12 if ARCH_BSC9131 || \ 1189 ARCH_BSC9132 || \ 1190 ARCH_C29X || \ 1191 ARCH_MPC8536 || \ 1192 ARCH_MPC8572 || \ 1193 ARCH_P1010 || \ 1194 ARCH_P1011 || \ 1195 ARCH_P1020 || \ 1196 ARCH_P1021 || \ 1197 ARCH_P1022 || \ 1198 ARCH_P1023 || \ 1199 ARCH_P1024 || \ 1200 ARCH_P1025 || \ 1201 ARCH_P2020 1202 default 10 if ARCH_MPC8544 || \ 1203 ARCH_MPC8548 || \ 1204 ARCH_MPC8568 || \ 1205 ARCH_MPC8569 1206 default 8 if ARCH_MPC8540 || \ 1207 ARCH_MPC8541 || \ 1208 ARCH_MPC8555 || \ 1209 ARCH_MPC8560 1210 help 1211 Number of local access windows. This is fixed per SoC. 1212 If not sure, do not change. 1213 1214config SYS_FSL_THREADS_PER_CORE 1215 int 1216 default 2 if E6500 1217 default 1 1218 1219config SYS_NUM_TLBCAMS 1220 int "Number of TLB CAM entries" 1221 default 64 if E500MC 1222 default 16 1223 help 1224 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1225 16 for other E500 SoCs. 1226 1227config SYS_PPC64 1228 bool 1229 1230config SYS_PPC_E500_USE_DEBUG_TLB 1231 bool 1232 1233config SYS_PPC_E500_DEBUG_TLB 1234 int "Temporary TLB entry for external debugger" 1235 depends on SYS_PPC_E500_USE_DEBUG_TLB 1236 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1237 default 1 if ARCH_MPC8536 1238 default 2 if ARCH_MPC8572 || \ 1239 ARCH_P1011 || \ 1240 ARCH_P1020 || \ 1241 ARCH_P1021 || \ 1242 ARCH_P1022 || \ 1243 ARCH_P1024 || \ 1244 ARCH_P1025 || \ 1245 ARCH_P2020 1246 default 3 if ARCH_P1010 || \ 1247 ARCH_BSC9132 || \ 1248 ARCH_C29X 1249 help 1250 Select a temporary TLB entry to be used during boot to work 1251 around limitations in e500v1 and e500v2 external debugger 1252 support. This reduces the portions of the boot code where 1253 breakpoints and single stepping do not work. The value of this 1254 symbol should be set to the TLB1 entry to be used for this 1255 purpose. If unsure, do not change. 1256 1257source "board/freescale/b4860qds/Kconfig" 1258source "board/freescale/bsc9131rdb/Kconfig" 1259source "board/freescale/bsc9132qds/Kconfig" 1260source "board/freescale/c29xpcie/Kconfig" 1261source "board/freescale/corenet_ds/Kconfig" 1262source "board/freescale/mpc8536ds/Kconfig" 1263source "board/freescale/mpc8540ads/Kconfig" 1264source "board/freescale/mpc8541cds/Kconfig" 1265source "board/freescale/mpc8544ds/Kconfig" 1266source "board/freescale/mpc8548cds/Kconfig" 1267source "board/freescale/mpc8555cds/Kconfig" 1268source "board/freescale/mpc8560ads/Kconfig" 1269source "board/freescale/mpc8568mds/Kconfig" 1270source "board/freescale/mpc8569mds/Kconfig" 1271source "board/freescale/mpc8572ds/Kconfig" 1272source "board/freescale/p1010rdb/Kconfig" 1273source "board/freescale/p1022ds/Kconfig" 1274source "board/freescale/p1023rdb/Kconfig" 1275source "board/freescale/p1_p2_rdb_pc/Kconfig" 1276source "board/freescale/p1_twr/Kconfig" 1277source "board/freescale/p2041rdb/Kconfig" 1278source "board/freescale/qemu-ppce500/Kconfig" 1279source "board/freescale/t102xqds/Kconfig" 1280source "board/freescale/t102xrdb/Kconfig" 1281source "board/freescale/t1040qds/Kconfig" 1282source "board/freescale/t104xrdb/Kconfig" 1283source "board/freescale/t208xqds/Kconfig" 1284source "board/freescale/t208xrdb/Kconfig" 1285source "board/freescale/t4qds/Kconfig" 1286source "board/freescale/t4rdb/Kconfig" 1287source "board/gdsys/p1022/Kconfig" 1288source "board/keymile/kmp204x/Kconfig" 1289source "board/sbc8548/Kconfig" 1290source "board/socrates/Kconfig" 1291source "board/varisys/cyrus/Kconfig" 1292source "board/xes/xpedite520x/Kconfig" 1293source "board/xes/xpedite537x/Kconfig" 1294source "board/xes/xpedite550x/Kconfig" 1295source "board/Arcturus/ucp1020/Kconfig" 1296 1297endmenu 1298