1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 12 */ 13 14#include <asm-offsets.h> 15#include <config.h> 16#include <mpc83xx.h> 17#include <version.h> 18 19#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 20 21#include <ppc_asm.tmpl> 22#include <ppc_defs.h> 23 24#include <asm/cache.h> 25#include <asm/mmu.h> 26#include <asm/u-boot.h> 27 28/* We don't want the MMU yet. 29 */ 30#undef MSR_KERNEL 31 32/* 33 * Floating Point enable, Machine Check and Recoverable Interr. 34 */ 35#ifdef DEBUG 36#define MSR_KERNEL (MSR_FP|MSR_RI) 37#else 38#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 39#endif 40 41#if defined(CONFIG_NAND_SPL) || \ 42 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 43#define MINIMAL_SPL 44#endif 45 46#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 47 !defined(CONFIG_SYS_RAMBOOT) 48#define CONFIG_SYS_FLASHBOOT 49#endif 50 51/* 52 * Set up GOT: Global Offset Table 53 * 54 * Use r12 to access the GOT 55 */ 56 START_GOT 57 GOT_ENTRY(_GOT2_TABLE_) 58 GOT_ENTRY(__bss_start) 59 GOT_ENTRY(__bss_end) 60 61#ifndef MINIMAL_SPL 62 GOT_ENTRY(_FIXUP_TABLE_) 63 GOT_ENTRY(_start) 64 GOT_ENTRY(_start_of_vectors) 65 GOT_ENTRY(_end_of_vectors) 66 GOT_ENTRY(transfer_to_handler) 67#endif 68 END_GOT 69 70/* 71 * The Hard Reset Configuration Word (HRCW) table is in the first 64 72 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 73 * times so the processor can fetch it out of flash whether the flash 74 * is 8, 16, 32, or 64 bits wide (hardware trickery). 75 */ 76 .text 77#define _HRCW_TABLE_ENTRY(w) \ 78 .fill 8,1,(((w)>>24)&0xff); \ 79 .fill 8,1,(((w)>>16)&0xff); \ 80 .fill 8,1,(((w)>> 8)&0xff); \ 81 .fill 8,1,(((w) )&0xff) 82 83 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 84 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 85 86/* 87 * Magic number and version string - put it after the HRCW since it 88 * cannot be first in flash like it is in many other processors. 89 */ 90 .long 0x27051956 /* U-Boot Magic Number */ 91 92 .globl version_string 93version_string: 94 .ascii U_BOOT_VERSION_STRING, "\0" 95 96 .align 2 97 98 .globl enable_addr_trans 99enable_addr_trans: 100 /* enable address translation */ 101 mfmsr r5 102 ori r5, r5, (MSR_IR | MSR_DR) 103 mtmsr r5 104 isync 105 blr 106 107 .globl disable_addr_trans 108disable_addr_trans: 109 /* disable address translation */ 110 mflr r4 111 mfmsr r3 112 andi. r0, r3, (MSR_IR | MSR_DR) 113 beqlr 114 andc r3, r3, r0 115 mtspr SRR0, r4 116 mtspr SRR1, r3 117 rfi 118 119 .globl ppcDWstore 120ppcDWstore: 121 lfd 1, 0(r4) 122 stfd 1, 0(r3) 123 blr 124 125 .globl ppcDWload 126ppcDWload: 127 lfd 1, 0(r3) 128 stfd 1, 0(r4) 129 blr 130 131#ifndef CONFIG_DEFAULT_IMMR 132#error CONFIG_DEFAULT_IMMR must be defined 133#endif /* CONFIG_DEFAULT_IMMR */ 134#ifndef CONFIG_SYS_IMMR 135#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 136#endif /* CONFIG_SYS_IMMR */ 137 138/* 139 * After configuration, a system reset exception is executed using the 140 * vector at offset 0x100 relative to the base set by MSR[IP]. If 141 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 142 * base address is 0xfff00000. In the case of a Power On Reset or Hard 143 * Reset, the value of MSR[IP] is determined by the CIP field in the 144 * HRCW. 145 * 146 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 147 * This determines the location of the boot ROM (flash or EPROM) in the 148 * processor's address space at boot time. As long as the HRCW is set up 149 * so that we eventually end up executing the code below when the 150 * processor executes the reset exception, the actual values used should 151 * not matter. 152 * 153 * Once we have got here, the address mask in OR0 is cleared so that the 154 * bottom 32K of the boot ROM is effectively repeated all throughout the 155 * processor's address space, after which we can jump to the absolute 156 * address at which the boot ROM was linked at compile time, and proceed 157 * to initialise the memory controller without worrying if the rug will 158 * be pulled out from under us, so to speak (it will be fine as long as 159 * we configure BR0 with the same boot ROM link address). 160 */ 161 . = EXC_OFF_SYS_RESET 162 163 .globl _start 164_start: /* time t 0 */ 165 lis r4, CONFIG_DEFAULT_IMMR@h 166 nop 167 168 mfmsr r5 /* save msr contents */ 169 170 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 171 bl 1f 1721: mflr r7 173 174 lis r3, CONFIG_SYS_IMMR@h 175 ori r3, r3, CONFIG_SYS_IMMR@l 176 177 lwz r6, IMMRBAR(r4) 178 isync 179 180 stw r3, IMMRBAR(r4) 181 lwz r6, 0(r7) /* Arbitrary external load */ 182 isync 183 184 lwz r6, IMMRBAR(r3) 185 isync 186 187 /* Initialise the E300 processor core */ 188 /*------------------------------------------*/ 189 190#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 191 defined(CONFIG_NAND_SPL) 192 /* The FCM begins execution after only the first page 193 * is loaded. Wait for the rest before branching 194 * to another flash page. 195 */ 1961: lwz r6, 0x50b0(r3) 197 andi. r6, r6, 1 198 beq 1b 199#endif 200 201 bl init_e300_core 202 203#ifdef CONFIG_SYS_FLASHBOOT 204 205 /* Inflate flash location so it appears everywhere, calculate */ 206 /* the absolute address in final location of the FLASH, jump */ 207 /* there and deflate the flash size back to minimal size */ 208 /*------------------------------------------------------------*/ 209 bl map_flash_by_law1 210 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 211 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 212 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 213 mtlr r5 214 blr 215in_flash: 216#if 1 /* Remapping flash with LAW0. */ 217 bl remap_flash_by_law0 218#endif 219#endif /* CONFIG_SYS_FLASHBOOT */ 220 221 /* setup the bats */ 222 bl setup_bats 223 sync 224 225 /* 226 * Cache must be enabled here for stack-in-cache trick. 227 * This means we need to enable the BATS. 228 * This means: 229 * 1) for the EVB, original gt regs need to be mapped 230 * 2) need to have an IBAT for the 0xf region, 231 * we are running there! 232 * Cache should be turned on after BATs, since by default 233 * everything is write-through. 234 * The init-mem BAT can be reused after reloc. The old 235 * gt-regs BAT can be reused after board_init_f calls 236 * board_early_init_f (EVB only). 237 */ 238 /* enable address translation */ 239 bl enable_addr_trans 240 sync 241 242 /* enable the data cache */ 243 bl dcache_enable 244 sync 245#ifdef CONFIG_SYS_INIT_RAM_LOCK 246 bl lock_ram_in_cache 247 sync 248#endif 249 250 /* set up the stack pointer in our newly created 251 * cache-ram; use r3 to keep the new SP for now to 252 * avoid overiding the SP it uselessly */ 253 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 254 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 255 256 /* r4 = end of GD area */ 257 addi r4, r3, GENERATED_GBL_DATA_SIZE 258 259 /* Zero GD area */ 260 li r0, 0 2611: 262 subi r4, r4, 1 263 stb r0, 0(r4) 264 cmplw r3, r4 265 bne 1b 266 267#if CONFIG_VAL(SYS_MALLOC_F_LEN) 268 269#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE 270#error "SYS_MALLOC_F_LEN too large to fit into initial RAM." 271#endif 272 273 /* r3 = new stack pointer / pre-reloc malloc area */ 274 subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN) 275 276 /* Set pointer to pre-reloc malloc area in GD */ 277 stw r3, GD_MALLOC_BASE(r4) 278#endif 279 li r0, 0 /* Make room for stack frame header and */ 280 stwu r0, -4(r3) /* clear final stack frame so that */ 281 stwu r0, -4(r3) /* stack backtraces terminate cleanly */ 282 283 /* Finally, actually set SP */ 284 mr r1, r3 285 286 /* let the C-code set up the rest */ 287 /* */ 288 /* Be careful to keep code relocatable & stack humble */ 289 /*------------------------------------------------------*/ 290 291 GET_GOT /* initialize GOT access */ 292 293 /* r3: IMMR */ 294 lis r3, CONFIG_SYS_IMMR@h 295 /* run low-level CPU init code (in Flash)*/ 296 bl cpu_init_f 297 298 /* run 1st part of board init code (in Flash)*/ 299 li r3, 0 /* clear boot_flag for calling board_init_f */ 300 bl board_init_f 301 302 /* NOTREACHED - board_init_f() does not return */ 303 304#ifndef MINIMAL_SPL 305/* 306 * Vector Table 307 */ 308 309 .globl _start_of_vectors 310_start_of_vectors: 311 312/* Machine check */ 313 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 314 315/* Data Storage exception. */ 316 STD_EXCEPTION(0x300, DataStorage, UnknownException) 317 318/* Instruction Storage exception. */ 319 STD_EXCEPTION(0x400, InstStorage, UnknownException) 320 321/* External Interrupt exception. */ 322#ifndef FIXME 323 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 324#endif 325 326/* Alignment exception. */ 327 . = 0x600 328Alignment: 329 EXCEPTION_PROLOG(SRR0, SRR1) 330 mfspr r4,DAR 331 stw r4,_DAR(r21) 332 mfspr r5,DSISR 333 stw r5,_DSISR(r21) 334 addi r3,r1,STACK_FRAME_OVERHEAD 335 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 336 337/* Program check exception */ 338 . = 0x700 339ProgramCheck: 340 EXCEPTION_PROLOG(SRR0, SRR1) 341 addi r3,r1,STACK_FRAME_OVERHEAD 342 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 343 MSR_KERNEL, COPY_EE) 344 345 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 346 347 /* I guess we could implement decrementer, and may have 348 * to someday for timekeeping. 349 */ 350 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 351 352 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 353 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 354 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 355 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 356 357 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 358 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 359 360 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 361 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 362 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 363#ifdef DEBUG 364 . = 0x1300 365 /* 366 * This exception occurs when the program counter matches the 367 * Instruction Address Breakpoint Register (IABR). 368 * 369 * I want the cpu to halt if this occurs so I can hunt around 370 * with the debugger and look at things. 371 * 372 * When DEBUG is defined, both machine check enable (in the MSR) 373 * and checkstop reset enable (in the reset mode register) are 374 * turned off and so a checkstop condition will result in the cpu 375 * halting. 376 * 377 * I force the cpu into a checkstop condition by putting an illegal 378 * instruction here (at least this is the theory). 379 * 380 * well - that didnt work, so just do an infinite loop! 381 */ 3821: b 1b 383#else 384 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 385#endif 386 STD_EXCEPTION(0x1400, SMI, UnknownException) 387 388 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 389 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 390 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 391 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 392 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 393 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 394 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 395 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 396 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 397 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 398 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 399 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 400 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 401 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 402 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 403 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 404 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 405 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 406 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 407 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 408 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 409 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 410 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 411 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 412 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 413 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 414 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 415 416 417 .globl _end_of_vectors 418_end_of_vectors: 419 420 . = 0x3000 421 422/* 423 * This code finishes saving the registers to the exception frame 424 * and jumps to the appropriate handler for the exception. 425 * Register r21 is pointer into trap frame, r1 has new stack pointer. 426 */ 427 .globl transfer_to_handler 428transfer_to_handler: 429 stw r22,_NIP(r21) 430 lis r22,MSR_POW@h 431 andc r23,r23,r22 432 stw r23,_MSR(r21) 433 SAVE_GPR(7, r21) 434 SAVE_4GPRS(8, r21) 435 SAVE_8GPRS(12, r21) 436 SAVE_8GPRS(24, r21) 437 mflr r23 438 andi. r24,r23,0x3f00 /* get vector offset */ 439 stw r24,TRAP(r21) 440 li r22,0 441 stw r22,RESULT(r21) 442 lwz r24,0(r23) /* virtual address of handler */ 443 lwz r23,4(r23) /* where to go when done */ 444 mtspr SRR0,r24 445 mtspr SRR1,r20 446 mtlr r23 447 SYNC 448 rfi /* jump to handler, enable MMU */ 449 450int_return: 451 mfmsr r28 /* Disable interrupts */ 452 li r4,0 453 ori r4,r4,MSR_EE 454 andc r28,r28,r4 455 SYNC /* Some chip revs need this... */ 456 mtmsr r28 457 SYNC 458 lwz r2,_CTR(r1) 459 lwz r0,_LINK(r1) 460 mtctr r2 461 mtlr r0 462 lwz r2,_XER(r1) 463 lwz r0,_CCR(r1) 464 mtspr XER,r2 465 mtcrf 0xFF,r0 466 REST_10GPRS(3, r1) 467 REST_10GPRS(13, r1) 468 REST_8GPRS(23, r1) 469 REST_GPR(31, r1) 470 lwz r2,_NIP(r1) /* Restore environment */ 471 lwz r0,_MSR(r1) 472 mtspr SRR0,r2 473 mtspr SRR1,r0 474 lwz r0,GPR0(r1) 475 lwz r2,GPR2(r1) 476 lwz r1,GPR1(r1) 477 SYNC 478 rfi 479#endif /* !MINIMAL_SPL */ 480 481/* 482 * This code initialises the E300 processor core 483 * (conforms to PowerPC 603e spec) 484 * Note: expects original MSR contents to be in r5. 485 */ 486 .globl init_e300_core 487init_e300_core: /* time t 10 */ 488 /* Initialize machine status; enable machine check interrupt */ 489 /*-----------------------------------------------------------*/ 490 491 li r3, MSR_KERNEL /* Set ME and RI flags */ 492 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 493#ifdef DEBUG 494 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 495#endif 496 SYNC /* Some chip revs need this... */ 497 mtmsr r3 498 SYNC 499 mtspr SRR1, r3 /* Make SRR1 match MSR */ 500 501 502 lis r3, CONFIG_SYS_IMMR@h 503#if defined(CONFIG_WATCHDOG) 504 /* Initialise the Watchdog values and reset it (if req) */ 505 /*------------------------------------------------------*/ 506 lis r4, CONFIG_SYS_WATCHDOG_VALUE 507 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 508 stw r4, SWCRR(r3) 509 510 /* and reset it */ 511 512 li r4, 0x556C 513 sth r4, SWSRR@l(r3) 514 li r4, -0x55C7 515 sth r4, SWSRR@l(r3) 516#else 517 /* Disable Watchdog */ 518 /*-------------------*/ 519 lwz r4, SWCRR(r3) 520 /* Check to see if its enabled for disabling 521 once disabled by SW you can't re-enable */ 522 andi. r4, r4, 0x4 523 beq 1f 524 xor r4, r4, r4 525 stw r4, SWCRR(r3) 5261: 527#endif /* CONFIG_WATCHDOG */ 528 529#if defined(CONFIG_MASK_AER_AO) 530 /* Write the Arbiter Event Enable to mask Address Only traps. */ 531 /* This prevents the dcbz instruction from being trapped when */ 532 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 533 /* COHERENCY bit is set in the WIMG bits, which is often */ 534 /* needed for PCI operation. */ 535 lwz r4, 0x0808(r3) 536 rlwinm r0, r4, 0, ~AER_AO 537 stw r0, 0x0808(r3) 538#endif /* CONFIG_MASK_AER_AO */ 539 540 /* Initialize the Hardware Implementation-dependent Registers */ 541 /* HID0 also contains cache control */ 542 /* - force invalidation of data and instruction caches */ 543 /*------------------------------------------------------*/ 544 545 lis r3, CONFIG_SYS_HID0_INIT@h 546 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 547 SYNC 548 mtspr HID0, r3 549 550 lis r3, CONFIG_SYS_HID0_FINAL@h 551 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 552 SYNC 553 mtspr HID0, r3 554 555 lis r3, CONFIG_SYS_HID2@h 556 ori r3, r3, CONFIG_SYS_HID2@l 557 SYNC 558 mtspr HID2, r3 559 560 /* Done! */ 561 /*------------------------------*/ 562 blr 563 564 /* setup_bats - set them up to some initial state */ 565 .globl setup_bats 566setup_bats: 567 addis r0, r0, 0x0000 568 569 /* IBAT 0 */ 570 addis r4, r0, CONFIG_SYS_IBAT0L@h 571 ori r4, r4, CONFIG_SYS_IBAT0L@l 572 addis r3, r0, CONFIG_SYS_IBAT0U@h 573 ori r3, r3, CONFIG_SYS_IBAT0U@l 574 mtspr IBAT0L, r4 575 mtspr IBAT0U, r3 576 577 /* DBAT 0 */ 578 addis r4, r0, CONFIG_SYS_DBAT0L@h 579 ori r4, r4, CONFIG_SYS_DBAT0L@l 580 addis r3, r0, CONFIG_SYS_DBAT0U@h 581 ori r3, r3, CONFIG_SYS_DBAT0U@l 582 mtspr DBAT0L, r4 583 mtspr DBAT0U, r3 584 585 /* IBAT 1 */ 586 addis r4, r0, CONFIG_SYS_IBAT1L@h 587 ori r4, r4, CONFIG_SYS_IBAT1L@l 588 addis r3, r0, CONFIG_SYS_IBAT1U@h 589 ori r3, r3, CONFIG_SYS_IBAT1U@l 590 mtspr IBAT1L, r4 591 mtspr IBAT1U, r3 592 593 /* DBAT 1 */ 594 addis r4, r0, CONFIG_SYS_DBAT1L@h 595 ori r4, r4, CONFIG_SYS_DBAT1L@l 596 addis r3, r0, CONFIG_SYS_DBAT1U@h 597 ori r3, r3, CONFIG_SYS_DBAT1U@l 598 mtspr DBAT1L, r4 599 mtspr DBAT1U, r3 600 601 /* IBAT 2 */ 602 addis r4, r0, CONFIG_SYS_IBAT2L@h 603 ori r4, r4, CONFIG_SYS_IBAT2L@l 604 addis r3, r0, CONFIG_SYS_IBAT2U@h 605 ori r3, r3, CONFIG_SYS_IBAT2U@l 606 mtspr IBAT2L, r4 607 mtspr IBAT2U, r3 608 609 /* DBAT 2 */ 610 addis r4, r0, CONFIG_SYS_DBAT2L@h 611 ori r4, r4, CONFIG_SYS_DBAT2L@l 612 addis r3, r0, CONFIG_SYS_DBAT2U@h 613 ori r3, r3, CONFIG_SYS_DBAT2U@l 614 mtspr DBAT2L, r4 615 mtspr DBAT2U, r3 616 617 /* IBAT 3 */ 618 addis r4, r0, CONFIG_SYS_IBAT3L@h 619 ori r4, r4, CONFIG_SYS_IBAT3L@l 620 addis r3, r0, CONFIG_SYS_IBAT3U@h 621 ori r3, r3, CONFIG_SYS_IBAT3U@l 622 mtspr IBAT3L, r4 623 mtspr IBAT3U, r3 624 625 /* DBAT 3 */ 626 addis r4, r0, CONFIG_SYS_DBAT3L@h 627 ori r4, r4, CONFIG_SYS_DBAT3L@l 628 addis r3, r0, CONFIG_SYS_DBAT3U@h 629 ori r3, r3, CONFIG_SYS_DBAT3U@l 630 mtspr DBAT3L, r4 631 mtspr DBAT3U, r3 632 633#ifdef CONFIG_HIGH_BATS 634 /* IBAT 4 */ 635 addis r4, r0, CONFIG_SYS_IBAT4L@h 636 ori r4, r4, CONFIG_SYS_IBAT4L@l 637 addis r3, r0, CONFIG_SYS_IBAT4U@h 638 ori r3, r3, CONFIG_SYS_IBAT4U@l 639 mtspr IBAT4L, r4 640 mtspr IBAT4U, r3 641 642 /* DBAT 4 */ 643 addis r4, r0, CONFIG_SYS_DBAT4L@h 644 ori r4, r4, CONFIG_SYS_DBAT4L@l 645 addis r3, r0, CONFIG_SYS_DBAT4U@h 646 ori r3, r3, CONFIG_SYS_DBAT4U@l 647 mtspr DBAT4L, r4 648 mtspr DBAT4U, r3 649 650 /* IBAT 5 */ 651 addis r4, r0, CONFIG_SYS_IBAT5L@h 652 ori r4, r4, CONFIG_SYS_IBAT5L@l 653 addis r3, r0, CONFIG_SYS_IBAT5U@h 654 ori r3, r3, CONFIG_SYS_IBAT5U@l 655 mtspr IBAT5L, r4 656 mtspr IBAT5U, r3 657 658 /* DBAT 5 */ 659 addis r4, r0, CONFIG_SYS_DBAT5L@h 660 ori r4, r4, CONFIG_SYS_DBAT5L@l 661 addis r3, r0, CONFIG_SYS_DBAT5U@h 662 ori r3, r3, CONFIG_SYS_DBAT5U@l 663 mtspr DBAT5L, r4 664 mtspr DBAT5U, r3 665 666 /* IBAT 6 */ 667 addis r4, r0, CONFIG_SYS_IBAT6L@h 668 ori r4, r4, CONFIG_SYS_IBAT6L@l 669 addis r3, r0, CONFIG_SYS_IBAT6U@h 670 ori r3, r3, CONFIG_SYS_IBAT6U@l 671 mtspr IBAT6L, r4 672 mtspr IBAT6U, r3 673 674 /* DBAT 6 */ 675 addis r4, r0, CONFIG_SYS_DBAT6L@h 676 ori r4, r4, CONFIG_SYS_DBAT6L@l 677 addis r3, r0, CONFIG_SYS_DBAT6U@h 678 ori r3, r3, CONFIG_SYS_DBAT6U@l 679 mtspr DBAT6L, r4 680 mtspr DBAT6U, r3 681 682 /* IBAT 7 */ 683 addis r4, r0, CONFIG_SYS_IBAT7L@h 684 ori r4, r4, CONFIG_SYS_IBAT7L@l 685 addis r3, r0, CONFIG_SYS_IBAT7U@h 686 ori r3, r3, CONFIG_SYS_IBAT7U@l 687 mtspr IBAT7L, r4 688 mtspr IBAT7U, r3 689 690 /* DBAT 7 */ 691 addis r4, r0, CONFIG_SYS_DBAT7L@h 692 ori r4, r4, CONFIG_SYS_DBAT7L@l 693 addis r3, r0, CONFIG_SYS_DBAT7U@h 694 ori r3, r3, CONFIG_SYS_DBAT7U@l 695 mtspr DBAT7L, r4 696 mtspr DBAT7U, r3 697#endif 698 699 isync 700 701 /* invalidate all tlb's 702 * 703 * From the 603e User Manual: "The 603e provides the ability to 704 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 705 * instruction invalidates the TLB entry indexed by the EA, and 706 * operates on both the instruction and data TLBs simultaneously 707 * invalidating four TLB entries (both sets in each TLB). The 708 * index corresponds to bits 15-19 of the EA. To invalidate all 709 * entries within both TLBs, 32 tlbie instructions should be 710 * issued, incrementing this field by one each time." 711 * 712 * "Note that the tlbia instruction is not implemented on the 713 * 603e." 714 * 715 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 716 * incrementing by 0x1000 each time. The code below is sort of 717 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 718 * 719 */ 720 lis r3, 0 721 lis r5, 2 722 7231: 724 tlbie r3 725 addi r3, r3, 0x1000 726 cmp 0, 0, r3, r5 727 blt 1b 728 729 blr 730 731/* Cache functions. 732 * 733 * Note: requires that all cache bits in 734 * HID0 are in the low half word. 735 */ 736#ifndef MINIMAL_SPL 737 .globl icache_enable 738icache_enable: 739 mfspr r3, HID0 740 ori r3, r3, HID0_ICE 741 li r4, HID0_ICFI|HID0_ILOCK 742 andc r3, r3, r4 743 ori r4, r3, HID0_ICFI 744 isync 745 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 746 isync 747 mtspr HID0, r3 /* clears invalidate */ 748 blr 749 750 .globl icache_disable 751icache_disable: 752 mfspr r3, HID0 753 lis r4, 0 754 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 755 andc r3, r3, r4 756 isync 757 mtspr HID0, r3 /* clears invalidate, enable and lock */ 758 blr 759 760 .globl icache_status 761icache_status: 762 mfspr r3, HID0 763 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 764 blr 765#endif /* !MINIMAL_SPL */ 766 767 .globl dcache_enable 768dcache_enable: 769 mfspr r3, HID0 770 li r5, HID0_DCFI|HID0_DLOCK 771 andc r3, r3, r5 772 ori r3, r3, HID0_DCE 773 sync 774 mtspr HID0, r3 /* enable, no invalidate */ 775 blr 776 777 .globl dcache_disable 778dcache_disable: 779 mflr r4 780 bl flush_dcache /* uses r3 and r5 */ 781 mfspr r3, HID0 782 li r5, HID0_DCE|HID0_DLOCK 783 andc r3, r3, r5 784 ori r5, r3, HID0_DCFI 785 sync 786 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 787 sync 788 mtspr HID0, r3 /* clears invalidate */ 789 mtlr r4 790 blr 791 792 .globl dcache_status 793dcache_status: 794 mfspr r3, HID0 795 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 796 blr 797 798 .globl flush_dcache 799flush_dcache: 800 lis r3, 0 801 lis r5, CONFIG_SYS_CACHELINE_SIZE 8021: cmp 0, 1, r3, r5 803 bge 2f 804 lwz r5, 0(r3) 805 lis r5, CONFIG_SYS_CACHELINE_SIZE 806 addi r3, r3, 0x4 807 b 1b 8082: blr 809 810/*-------------------------------------------------------------------*/ 811 812/* 813 * void relocate_code (addr_sp, gd, addr_moni) 814 * 815 * This "function" does not return, instead it continues in RAM 816 * after relocating the monitor code. 817 * 818 * r3 = dest 819 * r4 = src 820 * r5 = length in bytes 821 * r6 = cachelinesize 822 */ 823 .globl relocate_code 824relocate_code: 825 mr r1, r3 /* Set new stack pointer */ 826 mr r9, r4 /* Save copy of Global Data pointer */ 827 mr r10, r5 /* Save copy of Destination Address */ 828 829 GET_GOT 830 mr r3, r5 /* Destination Address */ 831 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 832 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 833 lwz r5, GOT(__bss_start) 834 sub r5, r5, r4 835 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 836 837 /* 838 * Fix GOT pointer: 839 * 840 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 841 * + Destination Address 842 * 843 * Offset: 844 */ 845 sub r15, r10, r4 846 847 /* First our own GOT */ 848 add r12, r12, r15 849 /* then the one used by the C code */ 850 add r30, r30, r15 851 852 /* 853 * Now relocate code 854 */ 855 856 cmplw cr1,r3,r4 857 addi r0,r5,3 858 srwi. r0,r0,2 859 beq cr1,4f /* In place copy is not necessary */ 860 beq 7f /* Protect against 0 count */ 861 mtctr r0 862 bge cr1,2f 863 la r8,-4(r4) 864 la r7,-4(r3) 865 866 /* copy */ 8671: lwzu r0,4(r8) 868 stwu r0,4(r7) 869 bdnz 1b 870 871 addi r0,r5,3 872 srwi. r0,r0,2 873 mtctr r0 874 la r8,-4(r4) 875 la r7,-4(r3) 876 877 /* and compare */ 87820: lwzu r20,4(r8) 879 lwzu r21,4(r7) 880 xor. r22, r20, r21 881 bne 30f 882 bdnz 20b 883 b 4f 884 885 /* compare failed */ 88630: li r3, 0 887 blr 888 8892: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 890 add r8,r4,r0 891 add r7,r3,r0 8923: lwzu r0,-4(r8) 893 stwu r0,-4(r7) 894 bdnz 3b 895 896/* 897 * Now flush the cache: note that we must start from a cache aligned 898 * address. Otherwise we might miss one cache line. 899 */ 9004: cmpwi r6,0 901 add r5,r3,r5 902 beq 7f /* Always flush prefetch queue in any case */ 903 subi r0,r6,1 904 andc r3,r3,r0 905 mr r4,r3 9065: dcbst 0,r4 907 add r4,r4,r6 908 cmplw r4,r5 909 blt 5b 910 sync /* Wait for all dcbst to complete on bus */ 911 mr r4,r3 9126: icbi 0,r4 913 add r4,r4,r6 914 cmplw r4,r5 915 blt 6b 9167: sync /* Wait for all icbi to complete on bus */ 917 isync 918 919/* 920 * We are done. Do not return, instead branch to second part of board 921 * initialization, now running from RAM. 922 */ 923 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 924 mtlr r0 925 blr 926 927in_ram: 928 929 /* 930 * Relocation Function, r12 point to got2+0x8000 931 * 932 * Adjust got2 pointers, no need to check for 0, this code 933 * already puts a few entries in the table. 934 */ 935 li r0,__got2_entries@sectoff@l 936 la r3,GOT(_GOT2_TABLE_) 937 lwz r11,GOT(_GOT2_TABLE_) 938 mtctr r0 939 sub r11,r3,r11 940 addi r3,r3,-4 9411: lwzu r0,4(r3) 942 cmpwi r0,0 943 beq- 2f 944 add r0,r0,r11 945 stw r0,0(r3) 9462: bdnz 1b 947 948#ifndef MINIMAL_SPL 949 /* 950 * Now adjust the fixups and the pointers to the fixups 951 * in case we need to move ourselves again. 952 */ 953 li r0,__fixup_entries@sectoff@l 954 lwz r3,GOT(_FIXUP_TABLE_) 955 cmpwi r0,0 956 mtctr r0 957 addi r3,r3,-4 958 beq 4f 9593: lwzu r4,4(r3) 960 lwzux r0,r4,r11 961 cmpwi r0,0 962 add r0,r0,r11 963 stw r4,0(r3) 964 beq- 5f 965 stw r0,0(r4) 9665: bdnz 3b 9674: 968#endif 969 970clear_bss: 971 /* 972 * Now clear BSS segment 973 */ 974 lwz r3,GOT(__bss_start) 975 lwz r4,GOT(__bss_end) 976 977 cmplw 0, r3, r4 978 beq 6f 979 980 li r0, 0 9815: 982 stw r0, 0(r3) 983 addi r3, r3, 4 984 cmplw 0, r3, r4 985 bne 5b 9866: 987 988 mr r3, r9 /* Global Data pointer */ 989 mr r4, r10 /* Destination Address */ 990 bl board_init_r 991 992#ifndef MINIMAL_SPL 993 /* 994 * Copy exception vector code to low memory 995 * 996 * r3: dest_addr 997 * r7: source address, r8: end address, r9: target address 998 */ 999 .globl trap_init 1000trap_init: 1001 mflr r4 /* save link register */ 1002 GET_GOT 1003 lwz r7, GOT(_start) 1004 lwz r8, GOT(_end_of_vectors) 1005 1006 li r9, 0x100 /* reset vector always at 0x100 */ 1007 1008 cmplw 0, r7, r8 1009 bgelr /* return if r7>=r8 - just in case */ 10101: 1011 lwz r0, 0(r7) 1012 stw r0, 0(r9) 1013 addi r7, r7, 4 1014 addi r9, r9, 4 1015 cmplw 0, r7, r8 1016 bne 1b 1017 1018 /* 1019 * relocate `hdlr' and `int_return' entries 1020 */ 1021 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1022 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10232: 1024 bl trap_reloc 1025 addi r7, r7, 0x100 /* next exception vector */ 1026 cmplw 0, r7, r8 1027 blt 2b 1028 1029 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1030 bl trap_reloc 1031 1032 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1033 bl trap_reloc 1034 1035 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1036 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10373: 1038 bl trap_reloc 1039 addi r7, r7, 0x100 /* next exception vector */ 1040 cmplw 0, r7, r8 1041 blt 3b 1042 1043 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1044 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10454: 1046 bl trap_reloc 1047 addi r7, r7, 0x100 /* next exception vector */ 1048 cmplw 0, r7, r8 1049 blt 4b 1050 1051 mfmsr r3 /* now that the vectors have */ 1052 lis r7, MSR_IP@h /* relocated into low memory */ 1053 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1054 andc r3, r3, r7 /* (if it was on) */ 1055 SYNC /* Some chip revs need this... */ 1056 mtmsr r3 1057 SYNC 1058 1059 mtlr r4 /* restore link register */ 1060 blr 1061 1062#endif /* !MINIMAL_SPL */ 1063 1064#ifdef CONFIG_SYS_INIT_RAM_LOCK 1065lock_ram_in_cache: 1066 /* Allocate Initial RAM in data cache. 1067 */ 1068 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1069 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1070 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1071 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1072 mtctr r4 10731: 1074 dcbz r0, r3 1075 addi r3, r3, 32 1076 bdnz 1b 1077 1078 /* Lock the data cache */ 1079 mfspr r0, HID0 1080 ori r0, r0, HID0_DLOCK 1081 sync 1082 mtspr HID0, r0 1083 sync 1084 blr 1085 1086#ifndef MINIMAL_SPL 1087.globl unlock_ram_in_cache 1088unlock_ram_in_cache: 1089 /* invalidate the INIT_RAM section */ 1090 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1091 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1092 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1093 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1094 mtctr r4 10951: icbi r0, r3 1096 dcbi r0, r3 1097 addi r3, r3, 32 1098 bdnz 1b 1099 sync /* Wait for all icbi to complete on bus */ 1100 isync 1101 1102 /* Unlock the data cache and invalidate it */ 1103 mfspr r3, HID0 1104 li r5, HID0_DLOCK|HID0_DCFI 1105 andc r3, r3, r5 /* no invalidate, unlock */ 1106 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1107 sync 1108 mtspr HID0, r5 /* invalidate, unlock */ 1109 sync 1110 mtspr HID0, r3 /* no invalidate, unlock */ 1111 blr 1112#endif /* !MINIMAL_SPL */ 1113#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1114 1115#ifdef CONFIG_SYS_FLASHBOOT 1116map_flash_by_law1: 1117 /* When booting from ROM (Flash or EPROM), clear the */ 1118 /* Address Mask in OR0 so ROM appears everywhere */ 1119 /*----------------------------------------------------*/ 1120 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1121 lwz r4, OR0@l(r3) 1122 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1123 and r4, r4, r5 1124 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1125 1126 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1127 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1128 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1129 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1130 * 0xFF800. From the hard resetting to here, the processor fetched and 1131 * executed the instructions one by one. There is not absolutely 1132 * jumping happened. Laterly, the u-boot code has to do an absolutely 1133 * jumping to tell the CPU instruction fetching component what the 1134 * u-boot TEXT base address is. Because the TEXT base resides in the 1135 * boot ROM memory space, to garantee the code can run smoothly after 1136 * that jumping, we must map in the entire boot ROM by Local Access 1137 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1138 * address for boot ROM, such as 0xFE000000. In this case, the default 1139 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1140 * need another window to map in it. 1141 */ 1142 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1143 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1144 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1145 1146 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1147 lis r4, (0x80000012)@h 1148 ori r4, r4, (0x80000012)@l 1149 li r5, CONFIG_SYS_FLASH_SIZE 11501: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1151 addi r4, r4, 1 1152 bne 1b 1153 1154 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1155 /* Wait for HW to catch up */ 1156 lwz r4, LBLAWAR1(r3) 1157 twi 0,r4,0 1158 isync 1159 blr 1160 1161 /* Though all the LBIU Local Access Windows and LBC Banks will be 1162 * initialized in the C code, we'd better configure boot ROM's 1163 * window 0 and bank 0 correctly at here. 1164 */ 1165remap_flash_by_law0: 1166 /* Initialize the BR0 with the boot ROM starting address. */ 1167 lwz r4, BR0(r3) 1168 li r5, 0x7FFF 1169 and r4, r4, r5 1170 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1171 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1172 or r5, r5, r4 1173 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1174 1175 lwz r4, OR0(r3) 1176 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1177 or r4, r4, r5 1178 stw r4, OR0(r3) 1179 1180 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1181 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1182 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1183 1184 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1185 lis r4, (0x80000012)@h 1186 ori r4, r4, (0x80000012)@l 1187 li r5, CONFIG_SYS_FLASH_SIZE 11881: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1189 addi r4, r4, 1 1190 bne 1b 1191 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1192 1193 1194 xor r4, r4, r4 1195 stw r4, LBLAWBAR1(r3) 1196 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1197 /* Wait for HW to catch up */ 1198 lwz r4, LBLAWAR1(r3) 1199 twi 0,r4,0 1200 isync 1201 blr 1202#endif /* CONFIG_SYS_FLASHBOOT */ 1203