1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 12 */ 13 14#include <asm-offsets.h> 15#include <config.h> 16#include <mpc83xx.h> 17#ifndef CONFIG_IDENT_STRING 18#define CONFIG_IDENT_STRING "MPC83XX" 19#endif 20#include <version.h> 21 22#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 23 24#include <ppc_asm.tmpl> 25#include <ppc_defs.h> 26 27#include <asm/cache.h> 28#include <asm/mmu.h> 29#include <asm/u-boot.h> 30 31/* We don't want the MMU yet. 32 */ 33#undef MSR_KERNEL 34 35/* 36 * Floating Point enable, Machine Check and Recoverable Interr. 37 */ 38#ifdef DEBUG 39#define MSR_KERNEL (MSR_FP|MSR_RI) 40#else 41#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 42#endif 43 44#if defined(CONFIG_NAND_SPL) || \ 45 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 46#define MINIMAL_SPL 47#endif 48 49#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 50 !defined(CONFIG_SYS_RAMBOOT) 51#define CONFIG_SYS_FLASHBOOT 52#endif 53 54/* 55 * Set up GOT: Global Offset Table 56 * 57 * Use r12 to access the GOT 58 */ 59 START_GOT 60 GOT_ENTRY(_GOT2_TABLE_) 61 GOT_ENTRY(__bss_start) 62 GOT_ENTRY(__bss_end) 63 64#ifndef MINIMAL_SPL 65 GOT_ENTRY(_FIXUP_TABLE_) 66 GOT_ENTRY(_start) 67 GOT_ENTRY(_start_of_vectors) 68 GOT_ENTRY(_end_of_vectors) 69 GOT_ENTRY(transfer_to_handler) 70#endif 71 END_GOT 72 73/* 74 * The Hard Reset Configuration Word (HRCW) table is in the first 64 75 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 76 * times so the processor can fetch it out of flash whether the flash 77 * is 8, 16, 32, or 64 bits wide (hardware trickery). 78 */ 79 .text 80#define _HRCW_TABLE_ENTRY(w) \ 81 .fill 8,1,(((w)>>24)&0xff); \ 82 .fill 8,1,(((w)>>16)&0xff); \ 83 .fill 8,1,(((w)>> 8)&0xff); \ 84 .fill 8,1,(((w) )&0xff) 85 86 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 87 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 88 89/* 90 * Magic number and version string - put it after the HRCW since it 91 * cannot be first in flash like it is in many other processors. 92 */ 93 .long 0x27051956 /* U-Boot Magic Number */ 94 95 .globl version_string 96version_string: 97 .ascii U_BOOT_VERSION_STRING, "\0" 98 99 .align 2 100 101 .globl enable_addr_trans 102enable_addr_trans: 103 /* enable address translation */ 104 mfmsr r5 105 ori r5, r5, (MSR_IR | MSR_DR) 106 mtmsr r5 107 isync 108 blr 109 110 .globl disable_addr_trans 111disable_addr_trans: 112 /* disable address translation */ 113 mflr r4 114 mfmsr r3 115 andi. r0, r3, (MSR_IR | MSR_DR) 116 beqlr 117 andc r3, r3, r0 118 mtspr SRR0, r4 119 mtspr SRR1, r3 120 rfi 121 122 .globl get_svr 123get_svr: 124 mfspr r3, SVR 125 blr 126 127 .globl get_pvr 128get_pvr: 129 mfspr r3, PVR 130 blr 131 132 .globl ppcDWstore 133ppcDWstore: 134 lfd 1, 0(r4) 135 stfd 1, 0(r3) 136 blr 137 138 .globl ppcDWload 139ppcDWload: 140 lfd 1, 0(r3) 141 stfd 1, 0(r4) 142 blr 143 144#ifndef CONFIG_DEFAULT_IMMR 145#error CONFIG_DEFAULT_IMMR must be defined 146#endif /* CONFIG_SYS_DEFAULT_IMMR */ 147#ifndef CONFIG_SYS_IMMR 148#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 149#endif /* CONFIG_SYS_IMMR */ 150 151/* 152 * After configuration, a system reset exception is executed using the 153 * vector at offset 0x100 relative to the base set by MSR[IP]. If 154 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 155 * base address is 0xfff00000. In the case of a Power On Reset or Hard 156 * Reset, the value of MSR[IP] is determined by the CIP field in the 157 * HRCW. 158 * 159 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 160 * This determines the location of the boot ROM (flash or EPROM) in the 161 * processor's address space at boot time. As long as the HRCW is set up 162 * so that we eventually end up executing the code below when the 163 * processor executes the reset exception, the actual values used should 164 * not matter. 165 * 166 * Once we have got here, the address mask in OR0 is cleared so that the 167 * bottom 32K of the boot ROM is effectively repeated all throughout the 168 * processor's address space, after which we can jump to the absolute 169 * address at which the boot ROM was linked at compile time, and proceed 170 * to initialise the memory controller without worrying if the rug will 171 * be pulled out from under us, so to speak (it will be fine as long as 172 * we configure BR0 with the same boot ROM link address). 173 */ 174 . = EXC_OFF_SYS_RESET 175 176 .globl _start 177_start: /* time t 0 */ 178 lis r4, CONFIG_DEFAULT_IMMR@h 179 nop 180 181 mfmsr r5 /* save msr contents */ 182 183 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 184 bl 1f 1851: mflr r7 186 187 lis r3, CONFIG_SYS_IMMR@h 188 ori r3, r3, CONFIG_SYS_IMMR@l 189 190 lwz r6, IMMRBAR(r4) 191 isync 192 193 stw r3, IMMRBAR(r4) 194 lwz r6, 0(r7) /* Arbitrary external load */ 195 isync 196 197 lwz r6, IMMRBAR(r3) 198 isync 199 200 /* Initialise the E300 processor core */ 201 /*------------------------------------------*/ 202 203#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 204 defined(CONFIG_NAND_SPL) 205 /* The FCM begins execution after only the first page 206 * is loaded. Wait for the rest before branching 207 * to another flash page. 208 */ 2091: lwz r6, 0x50b0(r3) 210 andi. r6, r6, 1 211 beq 1b 212#endif 213 214 bl init_e300_core 215 216#ifdef CONFIG_SYS_FLASHBOOT 217 218 /* Inflate flash location so it appears everywhere, calculate */ 219 /* the absolute address in final location of the FLASH, jump */ 220 /* there and deflate the flash size back to minimal size */ 221 /*------------------------------------------------------------*/ 222 bl map_flash_by_law1 223 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 224 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 225 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 226 mtlr r5 227 blr 228in_flash: 229#if 1 /* Remapping flash with LAW0. */ 230 bl remap_flash_by_law0 231#endif 232#endif /* CONFIG_SYS_FLASHBOOT */ 233 234 /* setup the bats */ 235 bl setup_bats 236 sync 237 238 /* 239 * Cache must be enabled here for stack-in-cache trick. 240 * This means we need to enable the BATS. 241 * This means: 242 * 1) for the EVB, original gt regs need to be mapped 243 * 2) need to have an IBAT for the 0xf region, 244 * we are running there! 245 * Cache should be turned on after BATs, since by default 246 * everything is write-through. 247 * The init-mem BAT can be reused after reloc. The old 248 * gt-regs BAT can be reused after board_init_f calls 249 * board_early_init_f (EVB only). 250 */ 251 /* enable address translation */ 252 bl enable_addr_trans 253 sync 254 255 /* enable the data cache */ 256 bl dcache_enable 257 sync 258#ifdef CONFIG_SYS_INIT_RAM_LOCK 259 bl lock_ram_in_cache 260 sync 261#endif 262 263 /* set up the stack pointer in our newly created 264 * cache-ram (r1) */ 265 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 266 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 267 268 li r0, 0 /* Make room for stack frame header and */ 269 stwu r0, -4(r1) /* clear final stack frame so that */ 270 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 271 272 273 /* let the C-code set up the rest */ 274 /* */ 275 /* Be careful to keep code relocatable & stack humble */ 276 /*------------------------------------------------------*/ 277 278 GET_GOT /* initialize GOT access */ 279 280 /* r3: IMMR */ 281 lis r3, CONFIG_SYS_IMMR@h 282 /* run low-level CPU init code (in Flash)*/ 283 bl cpu_init_f 284 285 /* run 1st part of board init code (in Flash)*/ 286 li r3, 0 /* clear boot_flag for calling board_init_f */ 287 bl board_init_f 288 289 /* NOTREACHED - board_init_f() does not return */ 290 291#ifndef MINIMAL_SPL 292/* 293 * Vector Table 294 */ 295 296 .globl _start_of_vectors 297_start_of_vectors: 298 299/* Machine check */ 300 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 301 302/* Data Storage exception. */ 303 STD_EXCEPTION(0x300, DataStorage, UnknownException) 304 305/* Instruction Storage exception. */ 306 STD_EXCEPTION(0x400, InstStorage, UnknownException) 307 308/* External Interrupt exception. */ 309#ifndef FIXME 310 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 311#endif 312 313/* Alignment exception. */ 314 . = 0x600 315Alignment: 316 EXCEPTION_PROLOG(SRR0, SRR1) 317 mfspr r4,DAR 318 stw r4,_DAR(r21) 319 mfspr r5,DSISR 320 stw r5,_DSISR(r21) 321 addi r3,r1,STACK_FRAME_OVERHEAD 322 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 323 324/* Program check exception */ 325 . = 0x700 326ProgramCheck: 327 EXCEPTION_PROLOG(SRR0, SRR1) 328 addi r3,r1,STACK_FRAME_OVERHEAD 329 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 330 MSR_KERNEL, COPY_EE) 331 332 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 333 334 /* I guess we could implement decrementer, and may have 335 * to someday for timekeeping. 336 */ 337 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 338 339 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 340 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 341 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 342 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 343 344 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 345 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 346 347 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 348 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 349 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 350#ifdef DEBUG 351 . = 0x1300 352 /* 353 * This exception occurs when the program counter matches the 354 * Instruction Address Breakpoint Register (IABR). 355 * 356 * I want the cpu to halt if this occurs so I can hunt around 357 * with the debugger and look at things. 358 * 359 * When DEBUG is defined, both machine check enable (in the MSR) 360 * and checkstop reset enable (in the reset mode register) are 361 * turned off and so a checkstop condition will result in the cpu 362 * halting. 363 * 364 * I force the cpu into a checkstop condition by putting an illegal 365 * instruction here (at least this is the theory). 366 * 367 * well - that didnt work, so just do an infinite loop! 368 */ 3691: b 1b 370#else 371 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 372#endif 373 STD_EXCEPTION(0x1400, SMI, UnknownException) 374 375 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 376 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 377 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 378 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 379 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 380 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 381 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 382 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 383 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 384 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 385 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 386 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 387 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 388 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 389 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 390 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 391 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 392 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 393 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 394 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 395 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 396 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 397 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 398 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 399 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 400 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 401 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 402 403 404 .globl _end_of_vectors 405_end_of_vectors: 406 407 . = 0x3000 408 409/* 410 * This code finishes saving the registers to the exception frame 411 * and jumps to the appropriate handler for the exception. 412 * Register r21 is pointer into trap frame, r1 has new stack pointer. 413 */ 414 .globl transfer_to_handler 415transfer_to_handler: 416 stw r22,_NIP(r21) 417 lis r22,MSR_POW@h 418 andc r23,r23,r22 419 stw r23,_MSR(r21) 420 SAVE_GPR(7, r21) 421 SAVE_4GPRS(8, r21) 422 SAVE_8GPRS(12, r21) 423 SAVE_8GPRS(24, r21) 424 mflr r23 425 andi. r24,r23,0x3f00 /* get vector offset */ 426 stw r24,TRAP(r21) 427 li r22,0 428 stw r22,RESULT(r21) 429 lwz r24,0(r23) /* virtual address of handler */ 430 lwz r23,4(r23) /* where to go when done */ 431 mtspr SRR0,r24 432 mtspr SRR1,r20 433 mtlr r23 434 SYNC 435 rfi /* jump to handler, enable MMU */ 436 437int_return: 438 mfmsr r28 /* Disable interrupts */ 439 li r4,0 440 ori r4,r4,MSR_EE 441 andc r28,r28,r4 442 SYNC /* Some chip revs need this... */ 443 mtmsr r28 444 SYNC 445 lwz r2,_CTR(r1) 446 lwz r0,_LINK(r1) 447 mtctr r2 448 mtlr r0 449 lwz r2,_XER(r1) 450 lwz r0,_CCR(r1) 451 mtspr XER,r2 452 mtcrf 0xFF,r0 453 REST_10GPRS(3, r1) 454 REST_10GPRS(13, r1) 455 REST_8GPRS(23, r1) 456 REST_GPR(31, r1) 457 lwz r2,_NIP(r1) /* Restore environment */ 458 lwz r0,_MSR(r1) 459 mtspr SRR0,r2 460 mtspr SRR1,r0 461 lwz r0,GPR0(r1) 462 lwz r2,GPR2(r1) 463 lwz r1,GPR1(r1) 464 SYNC 465 rfi 466#endif /* !MINIMAL_SPL */ 467 468/* 469 * This code initialises the E300 processor core 470 * (conforms to PowerPC 603e spec) 471 * Note: expects original MSR contents to be in r5. 472 */ 473 .globl init_e300_core 474init_e300_core: /* time t 10 */ 475 /* Initialize machine status; enable machine check interrupt */ 476 /*-----------------------------------------------------------*/ 477 478 li r3, MSR_KERNEL /* Set ME and RI flags */ 479 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 480#ifdef DEBUG 481 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 482#endif 483 SYNC /* Some chip revs need this... */ 484 mtmsr r3 485 SYNC 486 mtspr SRR1, r3 /* Make SRR1 match MSR */ 487 488 489 lis r3, CONFIG_SYS_IMMR@h 490#if defined(CONFIG_WATCHDOG) 491 /* Initialise the Watchdog values and reset it (if req) */ 492 /*------------------------------------------------------*/ 493 lis r4, CONFIG_SYS_WATCHDOG_VALUE 494 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 495 stw r4, SWCRR(r3) 496 497 /* and reset it */ 498 499 li r4, 0x556C 500 sth r4, SWSRR@l(r3) 501 li r4, -0x55C7 502 sth r4, SWSRR@l(r3) 503#else 504 /* Disable Watchdog */ 505 /*-------------------*/ 506 lwz r4, SWCRR(r3) 507 /* Check to see if its enabled for disabling 508 once disabled by SW you can't re-enable */ 509 andi. r4, r4, 0x4 510 beq 1f 511 xor r4, r4, r4 512 stw r4, SWCRR(r3) 5131: 514#endif /* CONFIG_WATCHDOG */ 515 516#if defined(CONFIG_MASK_AER_AO) 517 /* Write the Arbiter Event Enable to mask Address Only traps. */ 518 /* This prevents the dcbz instruction from being trapped when */ 519 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 520 /* COHERENCY bit is set in the WIMG bits, which is often */ 521 /* needed for PCI operation. */ 522 lwz r4, 0x0808(r3) 523 rlwinm r0, r4, 0, ~AER_AO 524 stw r0, 0x0808(r3) 525#endif /* CONFIG_MASK_AER_AO */ 526 527 /* Initialize the Hardware Implementation-dependent Registers */ 528 /* HID0 also contains cache control */ 529 /* - force invalidation of data and instruction caches */ 530 /*------------------------------------------------------*/ 531 532 lis r3, CONFIG_SYS_HID0_INIT@h 533 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 534 SYNC 535 mtspr HID0, r3 536 537 lis r3, CONFIG_SYS_HID0_FINAL@h 538 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 539 SYNC 540 mtspr HID0, r3 541 542 lis r3, CONFIG_SYS_HID2@h 543 ori r3, r3, CONFIG_SYS_HID2@l 544 SYNC 545 mtspr HID2, r3 546 547 /* Done! */ 548 /*------------------------------*/ 549 blr 550 551 /* setup_bats - set them up to some initial state */ 552 .globl setup_bats 553setup_bats: 554 addis r0, r0, 0x0000 555 556 /* IBAT 0 */ 557 addis r4, r0, CONFIG_SYS_IBAT0L@h 558 ori r4, r4, CONFIG_SYS_IBAT0L@l 559 addis r3, r0, CONFIG_SYS_IBAT0U@h 560 ori r3, r3, CONFIG_SYS_IBAT0U@l 561 mtspr IBAT0L, r4 562 mtspr IBAT0U, r3 563 564 /* DBAT 0 */ 565 addis r4, r0, CONFIG_SYS_DBAT0L@h 566 ori r4, r4, CONFIG_SYS_DBAT0L@l 567 addis r3, r0, CONFIG_SYS_DBAT0U@h 568 ori r3, r3, CONFIG_SYS_DBAT0U@l 569 mtspr DBAT0L, r4 570 mtspr DBAT0U, r3 571 572 /* IBAT 1 */ 573 addis r4, r0, CONFIG_SYS_IBAT1L@h 574 ori r4, r4, CONFIG_SYS_IBAT1L@l 575 addis r3, r0, CONFIG_SYS_IBAT1U@h 576 ori r3, r3, CONFIG_SYS_IBAT1U@l 577 mtspr IBAT1L, r4 578 mtspr IBAT1U, r3 579 580 /* DBAT 1 */ 581 addis r4, r0, CONFIG_SYS_DBAT1L@h 582 ori r4, r4, CONFIG_SYS_DBAT1L@l 583 addis r3, r0, CONFIG_SYS_DBAT1U@h 584 ori r3, r3, CONFIG_SYS_DBAT1U@l 585 mtspr DBAT1L, r4 586 mtspr DBAT1U, r3 587 588 /* IBAT 2 */ 589 addis r4, r0, CONFIG_SYS_IBAT2L@h 590 ori r4, r4, CONFIG_SYS_IBAT2L@l 591 addis r3, r0, CONFIG_SYS_IBAT2U@h 592 ori r3, r3, CONFIG_SYS_IBAT2U@l 593 mtspr IBAT2L, r4 594 mtspr IBAT2U, r3 595 596 /* DBAT 2 */ 597 addis r4, r0, CONFIG_SYS_DBAT2L@h 598 ori r4, r4, CONFIG_SYS_DBAT2L@l 599 addis r3, r0, CONFIG_SYS_DBAT2U@h 600 ori r3, r3, CONFIG_SYS_DBAT2U@l 601 mtspr DBAT2L, r4 602 mtspr DBAT2U, r3 603 604 /* IBAT 3 */ 605 addis r4, r0, CONFIG_SYS_IBAT3L@h 606 ori r4, r4, CONFIG_SYS_IBAT3L@l 607 addis r3, r0, CONFIG_SYS_IBAT3U@h 608 ori r3, r3, CONFIG_SYS_IBAT3U@l 609 mtspr IBAT3L, r4 610 mtspr IBAT3U, r3 611 612 /* DBAT 3 */ 613 addis r4, r0, CONFIG_SYS_DBAT3L@h 614 ori r4, r4, CONFIG_SYS_DBAT3L@l 615 addis r3, r0, CONFIG_SYS_DBAT3U@h 616 ori r3, r3, CONFIG_SYS_DBAT3U@l 617 mtspr DBAT3L, r4 618 mtspr DBAT3U, r3 619 620#ifdef CONFIG_HIGH_BATS 621 /* IBAT 4 */ 622 addis r4, r0, CONFIG_SYS_IBAT4L@h 623 ori r4, r4, CONFIG_SYS_IBAT4L@l 624 addis r3, r0, CONFIG_SYS_IBAT4U@h 625 ori r3, r3, CONFIG_SYS_IBAT4U@l 626 mtspr IBAT4L, r4 627 mtspr IBAT4U, r3 628 629 /* DBAT 4 */ 630 addis r4, r0, CONFIG_SYS_DBAT4L@h 631 ori r4, r4, CONFIG_SYS_DBAT4L@l 632 addis r3, r0, CONFIG_SYS_DBAT4U@h 633 ori r3, r3, CONFIG_SYS_DBAT4U@l 634 mtspr DBAT4L, r4 635 mtspr DBAT4U, r3 636 637 /* IBAT 5 */ 638 addis r4, r0, CONFIG_SYS_IBAT5L@h 639 ori r4, r4, CONFIG_SYS_IBAT5L@l 640 addis r3, r0, CONFIG_SYS_IBAT5U@h 641 ori r3, r3, CONFIG_SYS_IBAT5U@l 642 mtspr IBAT5L, r4 643 mtspr IBAT5U, r3 644 645 /* DBAT 5 */ 646 addis r4, r0, CONFIG_SYS_DBAT5L@h 647 ori r4, r4, CONFIG_SYS_DBAT5L@l 648 addis r3, r0, CONFIG_SYS_DBAT5U@h 649 ori r3, r3, CONFIG_SYS_DBAT5U@l 650 mtspr DBAT5L, r4 651 mtspr DBAT5U, r3 652 653 /* IBAT 6 */ 654 addis r4, r0, CONFIG_SYS_IBAT6L@h 655 ori r4, r4, CONFIG_SYS_IBAT6L@l 656 addis r3, r0, CONFIG_SYS_IBAT6U@h 657 ori r3, r3, CONFIG_SYS_IBAT6U@l 658 mtspr IBAT6L, r4 659 mtspr IBAT6U, r3 660 661 /* DBAT 6 */ 662 addis r4, r0, CONFIG_SYS_DBAT6L@h 663 ori r4, r4, CONFIG_SYS_DBAT6L@l 664 addis r3, r0, CONFIG_SYS_DBAT6U@h 665 ori r3, r3, CONFIG_SYS_DBAT6U@l 666 mtspr DBAT6L, r4 667 mtspr DBAT6U, r3 668 669 /* IBAT 7 */ 670 addis r4, r0, CONFIG_SYS_IBAT7L@h 671 ori r4, r4, CONFIG_SYS_IBAT7L@l 672 addis r3, r0, CONFIG_SYS_IBAT7U@h 673 ori r3, r3, CONFIG_SYS_IBAT7U@l 674 mtspr IBAT7L, r4 675 mtspr IBAT7U, r3 676 677 /* DBAT 7 */ 678 addis r4, r0, CONFIG_SYS_DBAT7L@h 679 ori r4, r4, CONFIG_SYS_DBAT7L@l 680 addis r3, r0, CONFIG_SYS_DBAT7U@h 681 ori r3, r3, CONFIG_SYS_DBAT7U@l 682 mtspr DBAT7L, r4 683 mtspr DBAT7U, r3 684#endif 685 686 isync 687 688 /* invalidate all tlb's 689 * 690 * From the 603e User Manual: "The 603e provides the ability to 691 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 692 * instruction invalidates the TLB entry indexed by the EA, and 693 * operates on both the instruction and data TLBs simultaneously 694 * invalidating four TLB entries (both sets in each TLB). The 695 * index corresponds to bits 15-19 of the EA. To invalidate all 696 * entries within both TLBs, 32 tlbie instructions should be 697 * issued, incrementing this field by one each time." 698 * 699 * "Note that the tlbia instruction is not implemented on the 700 * 603e." 701 * 702 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 703 * incrementing by 0x1000 each time. The code below is sort of 704 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 705 * 706 */ 707 lis r3, 0 708 lis r5, 2 709 7101: 711 tlbie r3 712 addi r3, r3, 0x1000 713 cmp 0, 0, r3, r5 714 blt 1b 715 716 blr 717 718/* Cache functions. 719 * 720 * Note: requires that all cache bits in 721 * HID0 are in the low half word. 722 */ 723#ifndef MINIMAL_SPL 724 .globl icache_enable 725icache_enable: 726 mfspr r3, HID0 727 ori r3, r3, HID0_ICE 728 li r4, HID0_ICFI|HID0_ILOCK 729 andc r3, r3, r4 730 ori r4, r3, HID0_ICFI 731 isync 732 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 733 isync 734 mtspr HID0, r3 /* clears invalidate */ 735 blr 736 737 .globl icache_disable 738icache_disable: 739 mfspr r3, HID0 740 lis r4, 0 741 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 742 andc r3, r3, r4 743 isync 744 mtspr HID0, r3 /* clears invalidate, enable and lock */ 745 blr 746 747 .globl icache_status 748icache_status: 749 mfspr r3, HID0 750 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 751 blr 752#endif /* !MINIMAL_SPL */ 753 754 .globl dcache_enable 755dcache_enable: 756 mfspr r3, HID0 757 li r5, HID0_DCFI|HID0_DLOCK 758 andc r3, r3, r5 759 ori r3, r3, HID0_DCE 760 sync 761 mtspr HID0, r3 /* enable, no invalidate */ 762 blr 763 764 .globl dcache_disable 765dcache_disable: 766 mflr r4 767 bl flush_dcache /* uses r3 and r5 */ 768 mfspr r3, HID0 769 li r5, HID0_DCE|HID0_DLOCK 770 andc r3, r3, r5 771 ori r5, r3, HID0_DCFI 772 sync 773 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 774 sync 775 mtspr HID0, r3 /* clears invalidate */ 776 mtlr r4 777 blr 778 779 .globl dcache_status 780dcache_status: 781 mfspr r3, HID0 782 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 783 blr 784 785 .globl flush_dcache 786flush_dcache: 787 lis r3, 0 788 lis r5, CONFIG_SYS_CACHELINE_SIZE 7891: cmp 0, 1, r3, r5 790 bge 2f 791 lwz r5, 0(r3) 792 lis r5, CONFIG_SYS_CACHELINE_SIZE 793 addi r3, r3, 0x4 794 b 1b 7952: blr 796 797/*-------------------------------------------------------------------*/ 798 799/* 800 * void relocate_code (addr_sp, gd, addr_moni) 801 * 802 * This "function" does not return, instead it continues in RAM 803 * after relocating the monitor code. 804 * 805 * r3 = dest 806 * r4 = src 807 * r5 = length in bytes 808 * r6 = cachelinesize 809 */ 810 .globl relocate_code 811relocate_code: 812 mr r1, r3 /* Set new stack pointer */ 813 mr r9, r4 /* Save copy of Global Data pointer */ 814 mr r10, r5 /* Save copy of Destination Address */ 815 816 GET_GOT 817 mr r3, r5 /* Destination Address */ 818 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 819 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 820 lwz r5, GOT(__bss_start) 821 sub r5, r5, r4 822 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 823 824 /* 825 * Fix GOT pointer: 826 * 827 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 828 * + Destination Address 829 * 830 * Offset: 831 */ 832 sub r15, r10, r4 833 834 /* First our own GOT */ 835 add r12, r12, r15 836 /* then the one used by the C code */ 837 add r30, r30, r15 838 839 /* 840 * Now relocate code 841 */ 842 843 cmplw cr1,r3,r4 844 addi r0,r5,3 845 srwi. r0,r0,2 846 beq cr1,4f /* In place copy is not necessary */ 847 beq 7f /* Protect against 0 count */ 848 mtctr r0 849 bge cr1,2f 850 la r8,-4(r4) 851 la r7,-4(r3) 852 853 /* copy */ 8541: lwzu r0,4(r8) 855 stwu r0,4(r7) 856 bdnz 1b 857 858 addi r0,r5,3 859 srwi. r0,r0,2 860 mtctr r0 861 la r8,-4(r4) 862 la r7,-4(r3) 863 864 /* and compare */ 86520: lwzu r20,4(r8) 866 lwzu r21,4(r7) 867 xor. r22, r20, r21 868 bne 30f 869 bdnz 20b 870 b 4f 871 872 /* compare failed */ 87330: li r3, 0 874 blr 875 8762: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 877 add r8,r4,r0 878 add r7,r3,r0 8793: lwzu r0,-4(r8) 880 stwu r0,-4(r7) 881 bdnz 3b 882 883/* 884 * Now flush the cache: note that we must start from a cache aligned 885 * address. Otherwise we might miss one cache line. 886 */ 8874: cmpwi r6,0 888 add r5,r3,r5 889 beq 7f /* Always flush prefetch queue in any case */ 890 subi r0,r6,1 891 andc r3,r3,r0 892 mr r4,r3 8935: dcbst 0,r4 894 add r4,r4,r6 895 cmplw r4,r5 896 blt 5b 897 sync /* Wait for all dcbst to complete on bus */ 898 mr r4,r3 8996: icbi 0,r4 900 add r4,r4,r6 901 cmplw r4,r5 902 blt 6b 9037: sync /* Wait for all icbi to complete on bus */ 904 isync 905 906/* 907 * We are done. Do not return, instead branch to second part of board 908 * initialization, now running from RAM. 909 */ 910 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 911 mtlr r0 912 blr 913 914in_ram: 915 916 /* 917 * Relocation Function, r12 point to got2+0x8000 918 * 919 * Adjust got2 pointers, no need to check for 0, this code 920 * already puts a few entries in the table. 921 */ 922 li r0,__got2_entries@sectoff@l 923 la r3,GOT(_GOT2_TABLE_) 924 lwz r11,GOT(_GOT2_TABLE_) 925 mtctr r0 926 sub r11,r3,r11 927 addi r3,r3,-4 9281: lwzu r0,4(r3) 929 cmpwi r0,0 930 beq- 2f 931 add r0,r0,r11 932 stw r0,0(r3) 9332: bdnz 1b 934 935#ifndef MINIMAL_SPL 936 /* 937 * Now adjust the fixups and the pointers to the fixups 938 * in case we need to move ourselves again. 939 */ 940 li r0,__fixup_entries@sectoff@l 941 lwz r3,GOT(_FIXUP_TABLE_) 942 cmpwi r0,0 943 mtctr r0 944 addi r3,r3,-4 945 beq 4f 9463: lwzu r4,4(r3) 947 lwzux r0,r4,r11 948 cmpwi r0,0 949 add r0,r0,r11 950 stw r4,0(r3) 951 beq- 5f 952 stw r0,0(r4) 9535: bdnz 3b 9544: 955#endif 956 957clear_bss: 958 /* 959 * Now clear BSS segment 960 */ 961 lwz r3,GOT(__bss_start) 962 lwz r4,GOT(__bss_end) 963 964 cmplw 0, r3, r4 965 beq 6f 966 967 li r0, 0 9685: 969 stw r0, 0(r3) 970 addi r3, r3, 4 971 cmplw 0, r3, r4 972 bne 5b 9736: 974 975 mr r3, r9 /* Global Data pointer */ 976 mr r4, r10 /* Destination Address */ 977 bl board_init_r 978 979#ifndef MINIMAL_SPL 980 /* 981 * Copy exception vector code to low memory 982 * 983 * r3: dest_addr 984 * r7: source address, r8: end address, r9: target address 985 */ 986 .globl trap_init 987trap_init: 988 mflr r4 /* save link register */ 989 GET_GOT 990 lwz r7, GOT(_start) 991 lwz r8, GOT(_end_of_vectors) 992 993 li r9, 0x100 /* reset vector always at 0x100 */ 994 995 cmplw 0, r7, r8 996 bgelr /* return if r7>=r8 - just in case */ 9971: 998 lwz r0, 0(r7) 999 stw r0, 0(r9) 1000 addi r7, r7, 4 1001 addi r9, r9, 4 1002 cmplw 0, r7, r8 1003 bne 1b 1004 1005 /* 1006 * relocate `hdlr' and `int_return' entries 1007 */ 1008 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1009 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10102: 1011 bl trap_reloc 1012 addi r7, r7, 0x100 /* next exception vector */ 1013 cmplw 0, r7, r8 1014 blt 2b 1015 1016 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1017 bl trap_reloc 1018 1019 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1020 bl trap_reloc 1021 1022 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1023 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10243: 1025 bl trap_reloc 1026 addi r7, r7, 0x100 /* next exception vector */ 1027 cmplw 0, r7, r8 1028 blt 3b 1029 1030 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1031 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10324: 1033 bl trap_reloc 1034 addi r7, r7, 0x100 /* next exception vector */ 1035 cmplw 0, r7, r8 1036 blt 4b 1037 1038 mfmsr r3 /* now that the vectors have */ 1039 lis r7, MSR_IP@h /* relocated into low memory */ 1040 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1041 andc r3, r3, r7 /* (if it was on) */ 1042 SYNC /* Some chip revs need this... */ 1043 mtmsr r3 1044 SYNC 1045 1046 mtlr r4 /* restore link register */ 1047 blr 1048 1049#endif /* !MINIMAL_SPL */ 1050 1051#ifdef CONFIG_SYS_INIT_RAM_LOCK 1052lock_ram_in_cache: 1053 /* Allocate Initial RAM in data cache. 1054 */ 1055 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1056 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1057 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1058 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1059 mtctr r4 10601: 1061 dcbz r0, r3 1062 addi r3, r3, 32 1063 bdnz 1b 1064 1065 /* Lock the data cache */ 1066 mfspr r0, HID0 1067 ori r0, r0, HID0_DLOCK 1068 sync 1069 mtspr HID0, r0 1070 sync 1071 blr 1072 1073#ifndef MINIMAL_SPL 1074.globl unlock_ram_in_cache 1075unlock_ram_in_cache: 1076 /* invalidate the INIT_RAM section */ 1077 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1078 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1079 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1080 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1081 mtctr r4 10821: icbi r0, r3 1083 dcbi r0, r3 1084 addi r3, r3, 32 1085 bdnz 1b 1086 sync /* Wait for all icbi to complete on bus */ 1087 isync 1088 1089 /* Unlock the data cache and invalidate it */ 1090 mfspr r3, HID0 1091 li r5, HID0_DLOCK|HID0_DCFI 1092 andc r3, r3, r5 /* no invalidate, unlock */ 1093 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1094 sync 1095 mtspr HID0, r5 /* invalidate, unlock */ 1096 sync 1097 mtspr HID0, r3 /* no invalidate, unlock */ 1098 blr 1099#endif /* !MINIMAL_SPL */ 1100#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1101 1102#ifdef CONFIG_SYS_FLASHBOOT 1103map_flash_by_law1: 1104 /* When booting from ROM (Flash or EPROM), clear the */ 1105 /* Address Mask in OR0 so ROM appears everywhere */ 1106 /*----------------------------------------------------*/ 1107 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1108 lwz r4, OR0@l(r3) 1109 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1110 and r4, r4, r5 1111 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1112 1113 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1114 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1115 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1116 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1117 * 0xFF800. From the hard resetting to here, the processor fetched and 1118 * executed the instructions one by one. There is not absolutely 1119 * jumping happened. Laterly, the u-boot code has to do an absolutely 1120 * jumping to tell the CPU instruction fetching component what the 1121 * u-boot TEXT base address is. Because the TEXT base resides in the 1122 * boot ROM memory space, to garantee the code can run smoothly after 1123 * that jumping, we must map in the entire boot ROM by Local Access 1124 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1125 * address for boot ROM, such as 0xFE000000. In this case, the default 1126 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1127 * need another window to map in it. 1128 */ 1129 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1130 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1131 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1132 1133 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1134 lis r4, (0x80000012)@h 1135 ori r4, r4, (0x80000012)@l 1136 li r5, CONFIG_SYS_FLASH_SIZE 11371: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1138 addi r4, r4, 1 1139 bne 1b 1140 1141 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1142 /* Wait for HW to catch up */ 1143 lwz r4, LBLAWAR1(r3) 1144 twi 0,r4,0 1145 isync 1146 blr 1147 1148 /* Though all the LBIU Local Access Windows and LBC Banks will be 1149 * initialized in the C code, we'd better configure boot ROM's 1150 * window 0 and bank 0 correctly at here. 1151 */ 1152remap_flash_by_law0: 1153 /* Initialize the BR0 with the boot ROM starting address. */ 1154 lwz r4, BR0(r3) 1155 li r5, 0x7FFF 1156 and r4, r4, r5 1157 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1158 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1159 or r5, r5, r4 1160 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1161 1162 lwz r4, OR0(r3) 1163 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1164 or r4, r4, r5 1165 stw r4, OR0(r3) 1166 1167 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1168 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1169 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1170 1171 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1172 lis r4, (0x80000012)@h 1173 ori r4, r4, (0x80000012)@l 1174 li r5, CONFIG_SYS_FLASH_SIZE 11751: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1176 addi r4, r4, 1 1177 bne 1b 1178 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1179 1180 1181 xor r4, r4, r4 1182 stw r4, LBLAWBAR1(r3) 1183 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1184 /* Wait for HW to catch up */ 1185 lwz r4, LBLAWAR1(r3) 1186 twi 0,r4,0 1187 isync 1188 blr 1189#endif /* CONFIG_SYS_FLASHBOOT */ 1190