1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 28 */ 29 30#include <asm-offsets.h> 31#include <config.h> 32#include <mpc83xx.h> 33#include <timestamp.h> 34#include <version.h> 35 36#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 37#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 38 39#include <ppc_asm.tmpl> 40#include <ppc_defs.h> 41 42#include <asm/cache.h> 43#include <asm/mmu.h> 44#include <asm/u-boot.h> 45 46#ifndef CONFIG_IDENT_STRING 47#define CONFIG_IDENT_STRING "MPC83XX" 48#endif 49 50/* We don't want the MMU yet. 51 */ 52#undef MSR_KERNEL 53 54/* 55 * Floating Point enable, Machine Check and Recoverable Interr. 56 */ 57#ifdef DEBUG 58#define MSR_KERNEL (MSR_FP|MSR_RI) 59#else 60#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 61#endif 62 63#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) 64#define CONFIG_SYS_FLASHBOOT 65#endif 66 67/* 68 * Set up GOT: Global Offset Table 69 * 70 * Use r12 to access the GOT 71 */ 72 START_GOT 73 GOT_ENTRY(_GOT2_TABLE_) 74 GOT_ENTRY(__bss_start) 75 GOT_ENTRY(__bss_end__) 76 77#ifndef CONFIG_NAND_SPL 78 GOT_ENTRY(_FIXUP_TABLE_) 79 GOT_ENTRY(_start) 80 GOT_ENTRY(_start_of_vectors) 81 GOT_ENTRY(_end_of_vectors) 82 GOT_ENTRY(transfer_to_handler) 83#endif 84 END_GOT 85 86/* 87 * The Hard Reset Configuration Word (HRCW) table is in the first 64 88 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 89 * times so the processor can fetch it out of flash whether the flash 90 * is 8, 16, 32, or 64 bits wide (hardware trickery). 91 */ 92 .text 93#define _HRCW_TABLE_ENTRY(w) \ 94 .fill 8,1,(((w)>>24)&0xff); \ 95 .fill 8,1,(((w)>>16)&0xff); \ 96 .fill 8,1,(((w)>> 8)&0xff); \ 97 .fill 8,1,(((w) )&0xff) 98 99 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 100 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 101 102/* 103 * Magic number and version string - put it after the HRCW since it 104 * cannot be first in flash like it is in many other processors. 105 */ 106 .long 0x27051956 /* U-Boot Magic Number */ 107 108 .globl version_string 109version_string: 110 .ascii U_BOOT_VERSION 111 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 112 .ascii " ", CONFIG_IDENT_STRING, "\0" 113 114 .align 2 115 116 .globl enable_addr_trans 117enable_addr_trans: 118 /* enable address translation */ 119 mfmsr r5 120 ori r5, r5, (MSR_IR | MSR_DR) 121 mtmsr r5 122 isync 123 blr 124 125 .globl disable_addr_trans 126disable_addr_trans: 127 /* disable address translation */ 128 mflr r4 129 mfmsr r3 130 andi. r0, r3, (MSR_IR | MSR_DR) 131 beqlr 132 andc r3, r3, r0 133 mtspr SRR0, r4 134 mtspr SRR1, r3 135 rfi 136 137 .globl get_pvr 138get_pvr: 139 mfspr r3, PVR 140 blr 141 142 .globl ppcDWstore 143ppcDWstore: 144 lfd 1, 0(r4) 145 stfd 1, 0(r3) 146 blr 147 148 .globl ppcDWload 149ppcDWload: 150 lfd 1, 0(r3) 151 stfd 1, 0(r4) 152 blr 153 154#ifndef CONFIG_DEFAULT_IMMR 155#error CONFIG_DEFAULT_IMMR must be defined 156#endif /* CONFIG_SYS_DEFAULT_IMMR */ 157#ifndef CONFIG_SYS_IMMR 158#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 159#endif /* CONFIG_SYS_IMMR */ 160 161/* 162 * After configuration, a system reset exception is executed using the 163 * vector at offset 0x100 relative to the base set by MSR[IP]. If 164 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 165 * base address is 0xfff00000. In the case of a Power On Reset or Hard 166 * Reset, the value of MSR[IP] is determined by the CIP field in the 167 * HRCW. 168 * 169 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 170 * This determines the location of the boot ROM (flash or EPROM) in the 171 * processor's address space at boot time. As long as the HRCW is set up 172 * so that we eventually end up executing the code below when the 173 * processor executes the reset exception, the actual values used should 174 * not matter. 175 * 176 * Once we have got here, the address mask in OR0 is cleared so that the 177 * bottom 32K of the boot ROM is effectively repeated all throughout the 178 * processor's address space, after which we can jump to the absolute 179 * address at which the boot ROM was linked at compile time, and proceed 180 * to initialise the memory controller without worrying if the rug will 181 * be pulled out from under us, so to speak (it will be fine as long as 182 * we configure BR0 with the same boot ROM link address). 183 */ 184 . = EXC_OFF_SYS_RESET 185 186 .globl _start 187_start: /* time t 0 */ 188 lis r4, CONFIG_DEFAULT_IMMR@h 189 nop 190 191 mfmsr r5 /* save msr contents */ 192 193 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 194 bl 1f 1951: mflr r7 196 197 lis r3, CONFIG_SYS_IMMR@h 198 ori r3, r3, CONFIG_SYS_IMMR@l 199 200 lwz r6, IMMRBAR(r4) 201 isync 202 203 stw r3, IMMRBAR(r4) 204 lwz r6, 0(r7) /* Arbitrary external load */ 205 isync 206 207 lwz r6, IMMRBAR(r3) 208 isync 209 210 /* Initialise the E300 processor core */ 211 /*------------------------------------------*/ 212 213#ifdef CONFIG_NAND_SPL 214 /* The FCM begins execution after only the first page 215 * is loaded. Wait for the rest before branching 216 * to another flash page. 217 */ 2181: lwz r6, 0x50b0(r3) 219 andi. r6, r6, 1 220 beq 1b 221#endif 222 223 bl init_e300_core 224 225#ifdef CONFIG_SYS_FLASHBOOT 226 227 /* Inflate flash location so it appears everywhere, calculate */ 228 /* the absolute address in final location of the FLASH, jump */ 229 /* there and deflate the flash size back to minimal size */ 230 /*------------------------------------------------------------*/ 231 bl map_flash_by_law1 232 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 233 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 234 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 235 mtlr r5 236 blr 237in_flash: 238#if 1 /* Remapping flash with LAW0. */ 239 bl remap_flash_by_law0 240#endif 241#endif /* CONFIG_SYS_FLASHBOOT */ 242 243 /* setup the bats */ 244 bl setup_bats 245 sync 246 247 /* 248 * Cache must be enabled here for stack-in-cache trick. 249 * This means we need to enable the BATS. 250 * This means: 251 * 1) for the EVB, original gt regs need to be mapped 252 * 2) need to have an IBAT for the 0xf region, 253 * we are running there! 254 * Cache should be turned on after BATs, since by default 255 * everything is write-through. 256 * The init-mem BAT can be reused after reloc. The old 257 * gt-regs BAT can be reused after board_init_f calls 258 * board_early_init_f (EVB only). 259 */ 260 /* enable address translation */ 261 bl enable_addr_trans 262 sync 263 264 /* enable the data cache */ 265 bl dcache_enable 266 sync 267#ifdef CONFIG_SYS_INIT_RAM_LOCK 268 bl lock_ram_in_cache 269 sync 270#endif 271 272 /* set up the stack pointer in our newly created 273 * cache-ram (r1) */ 274 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 275 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 276 277 li r0, 0 /* Make room for stack frame header and */ 278 stwu r0, -4(r1) /* clear final stack frame so that */ 279 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 280 281 282 /* let the C-code set up the rest */ 283 /* */ 284 /* Be careful to keep code relocatable & stack humble */ 285 /*------------------------------------------------------*/ 286 287 GET_GOT /* initialize GOT access */ 288#if defined(__pic__) && __pic__ == 1 289 /* Needed for upcoming -msingle-pic-base */ 290 bl _GLOBAL_OFFSET_TABLE_@local-4 291 mflr r30 292#endif 293 /* r3: IMMR */ 294 lis r3, CONFIG_SYS_IMMR@h 295 /* run low-level CPU init code (in Flash)*/ 296 bl cpu_init_f 297 298 /* run 1st part of board init code (in Flash)*/ 299 bl board_init_f 300 301 /* NOTREACHED - board_init_f() does not return */ 302 303#ifndef CONFIG_NAND_SPL 304/* 305 * Vector Table 306 */ 307 308 .globl _start_of_vectors 309_start_of_vectors: 310 311/* Machine check */ 312 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 313 314/* Data Storage exception. */ 315 STD_EXCEPTION(0x300, DataStorage, UnknownException) 316 317/* Instruction Storage exception. */ 318 STD_EXCEPTION(0x400, InstStorage, UnknownException) 319 320/* External Interrupt exception. */ 321#ifndef FIXME 322 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 323#endif 324 325/* Alignment exception. */ 326 . = 0x600 327Alignment: 328 EXCEPTION_PROLOG(SRR0, SRR1) 329 mfspr r4,DAR 330 stw r4,_DAR(r21) 331 mfspr r5,DSISR 332 stw r5,_DSISR(r21) 333 addi r3,r1,STACK_FRAME_OVERHEAD 334 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 335 336/* Program check exception */ 337 . = 0x700 338ProgramCheck: 339 EXCEPTION_PROLOG(SRR0, SRR1) 340 addi r3,r1,STACK_FRAME_OVERHEAD 341 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 342 MSR_KERNEL, COPY_EE) 343 344 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 345 346 /* I guess we could implement decrementer, and may have 347 * to someday for timekeeping. 348 */ 349 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 350 351 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 352 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 353 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 354 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 355 356 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 357 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 358 359 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 360 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 361 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 362#ifdef DEBUG 363 . = 0x1300 364 /* 365 * This exception occurs when the program counter matches the 366 * Instruction Address Breakpoint Register (IABR). 367 * 368 * I want the cpu to halt if this occurs so I can hunt around 369 * with the debugger and look at things. 370 * 371 * When DEBUG is defined, both machine check enable (in the MSR) 372 * and checkstop reset enable (in the reset mode register) are 373 * turned off and so a checkstop condition will result in the cpu 374 * halting. 375 * 376 * I force the cpu into a checkstop condition by putting an illegal 377 * instruction here (at least this is the theory). 378 * 379 * well - that didnt work, so just do an infinite loop! 380 */ 3811: b 1b 382#else 383 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 384#endif 385 STD_EXCEPTION(0x1400, SMI, UnknownException) 386 387 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 388 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 389 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 390 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 391 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 392 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 393 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 394 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 395 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 396 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 397 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 398 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 399 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 400 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 401 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 402 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 403 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 404 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 405 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 406 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 407 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 408 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 409 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 410 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 411 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 412 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 413 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 414 415 416 .globl _end_of_vectors 417_end_of_vectors: 418 419 . = 0x3000 420 421/* 422 * This code finishes saving the registers to the exception frame 423 * and jumps to the appropriate handler for the exception. 424 * Register r21 is pointer into trap frame, r1 has new stack pointer. 425 */ 426 .globl transfer_to_handler 427transfer_to_handler: 428 stw r22,_NIP(r21) 429 lis r22,MSR_POW@h 430 andc r23,r23,r22 431 stw r23,_MSR(r21) 432 SAVE_GPR(7, r21) 433 SAVE_4GPRS(8, r21) 434 SAVE_8GPRS(12, r21) 435 SAVE_8GPRS(24, r21) 436 mflr r23 437 andi. r24,r23,0x3f00 /* get vector offset */ 438 stw r24,TRAP(r21) 439 li r22,0 440 stw r22,RESULT(r21) 441 lwz r24,0(r23) /* virtual address of handler */ 442 lwz r23,4(r23) /* where to go when done */ 443 mtspr SRR0,r24 444 mtspr SRR1,r20 445 mtlr r23 446 SYNC 447 rfi /* jump to handler, enable MMU */ 448 449int_return: 450 mfmsr r28 /* Disable interrupts */ 451 li r4,0 452 ori r4,r4,MSR_EE 453 andc r28,r28,r4 454 SYNC /* Some chip revs need this... */ 455 mtmsr r28 456 SYNC 457 lwz r2,_CTR(r1) 458 lwz r0,_LINK(r1) 459 mtctr r2 460 mtlr r0 461 lwz r2,_XER(r1) 462 lwz r0,_CCR(r1) 463 mtspr XER,r2 464 mtcrf 0xFF,r0 465 REST_10GPRS(3, r1) 466 REST_10GPRS(13, r1) 467 REST_8GPRS(23, r1) 468 REST_GPR(31, r1) 469 lwz r2,_NIP(r1) /* Restore environment */ 470 lwz r0,_MSR(r1) 471 mtspr SRR0,r2 472 mtspr SRR1,r0 473 lwz r0,GPR0(r1) 474 lwz r2,GPR2(r1) 475 lwz r1,GPR1(r1) 476 SYNC 477 rfi 478#endif /* !CONFIG_NAND_SPL */ 479 480/* 481 * This code initialises the E300 processor core 482 * (conforms to PowerPC 603e spec) 483 * Note: expects original MSR contents to be in r5. 484 */ 485 .globl init_e300_core 486init_e300_core: /* time t 10 */ 487 /* Initialize machine status; enable machine check interrupt */ 488 /*-----------------------------------------------------------*/ 489 490 li r3, MSR_KERNEL /* Set ME and RI flags */ 491 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 492#ifdef DEBUG 493 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 494#endif 495 SYNC /* Some chip revs need this... */ 496 mtmsr r3 497 SYNC 498 mtspr SRR1, r3 /* Make SRR1 match MSR */ 499 500 501 lis r3, CONFIG_SYS_IMMR@h 502#if defined(CONFIG_WATCHDOG) 503 /* Initialise the Watchdog values and reset it (if req) */ 504 /*------------------------------------------------------*/ 505 lis r4, CONFIG_SYS_WATCHDOG_VALUE 506 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 507 stw r4, SWCRR(r3) 508 509 /* and reset it */ 510 511 li r4, 0x556C 512 sth r4, SWSRR@l(r3) 513 li r4, -0x55C7 514 sth r4, SWSRR@l(r3) 515#else 516 /* Disable Watchdog */ 517 /*-------------------*/ 518 lwz r4, SWCRR(r3) 519 /* Check to see if its enabled for disabling 520 once disabled by SW you can't re-enable */ 521 andi. r4, r4, 0x4 522 beq 1f 523 xor r4, r4, r4 524 stw r4, SWCRR(r3) 5251: 526#endif /* CONFIG_WATCHDOG */ 527 528#if defined(CONFIG_MASK_AER_AO) 529 /* Write the Arbiter Event Enable to mask Address Only traps. */ 530 /* This prevents the dcbz instruction from being trapped when */ 531 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 532 /* COHERENCY bit is set in the WIMG bits, which is often */ 533 /* needed for PCI operation. */ 534 lwz r4, 0x0808(r3) 535 rlwinm r0, r4, 0, ~AER_AO 536 stw r0, 0x0808(r3) 537#endif /* CONFIG_MASK_AER_AO */ 538 539 /* Initialize the Hardware Implementation-dependent Registers */ 540 /* HID0 also contains cache control */ 541 /* - force invalidation of data and instruction caches */ 542 /*------------------------------------------------------*/ 543 544 lis r3, CONFIG_SYS_HID0_INIT@h 545 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 546 SYNC 547 mtspr HID0, r3 548 549 lis r3, CONFIG_SYS_HID0_FINAL@h 550 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 551 SYNC 552 mtspr HID0, r3 553 554 lis r3, CONFIG_SYS_HID2@h 555 ori r3, r3, CONFIG_SYS_HID2@l 556 SYNC 557 mtspr HID2, r3 558 559 /* Done! */ 560 /*------------------------------*/ 561 blr 562 563 /* setup_bats - set them up to some initial state */ 564 .globl setup_bats 565setup_bats: 566 addis r0, r0, 0x0000 567 568 /* IBAT 0 */ 569 addis r4, r0, CONFIG_SYS_IBAT0L@h 570 ori r4, r4, CONFIG_SYS_IBAT0L@l 571 addis r3, r0, CONFIG_SYS_IBAT0U@h 572 ori r3, r3, CONFIG_SYS_IBAT0U@l 573 mtspr IBAT0L, r4 574 mtspr IBAT0U, r3 575 576 /* DBAT 0 */ 577 addis r4, r0, CONFIG_SYS_DBAT0L@h 578 ori r4, r4, CONFIG_SYS_DBAT0L@l 579 addis r3, r0, CONFIG_SYS_DBAT0U@h 580 ori r3, r3, CONFIG_SYS_DBAT0U@l 581 mtspr DBAT0L, r4 582 mtspr DBAT0U, r3 583 584 /* IBAT 1 */ 585 addis r4, r0, CONFIG_SYS_IBAT1L@h 586 ori r4, r4, CONFIG_SYS_IBAT1L@l 587 addis r3, r0, CONFIG_SYS_IBAT1U@h 588 ori r3, r3, CONFIG_SYS_IBAT1U@l 589 mtspr IBAT1L, r4 590 mtspr IBAT1U, r3 591 592 /* DBAT 1 */ 593 addis r4, r0, CONFIG_SYS_DBAT1L@h 594 ori r4, r4, CONFIG_SYS_DBAT1L@l 595 addis r3, r0, CONFIG_SYS_DBAT1U@h 596 ori r3, r3, CONFIG_SYS_DBAT1U@l 597 mtspr DBAT1L, r4 598 mtspr DBAT1U, r3 599 600 /* IBAT 2 */ 601 addis r4, r0, CONFIG_SYS_IBAT2L@h 602 ori r4, r4, CONFIG_SYS_IBAT2L@l 603 addis r3, r0, CONFIG_SYS_IBAT2U@h 604 ori r3, r3, CONFIG_SYS_IBAT2U@l 605 mtspr IBAT2L, r4 606 mtspr IBAT2U, r3 607 608 /* DBAT 2 */ 609 addis r4, r0, CONFIG_SYS_DBAT2L@h 610 ori r4, r4, CONFIG_SYS_DBAT2L@l 611 addis r3, r0, CONFIG_SYS_DBAT2U@h 612 ori r3, r3, CONFIG_SYS_DBAT2U@l 613 mtspr DBAT2L, r4 614 mtspr DBAT2U, r3 615 616 /* IBAT 3 */ 617 addis r4, r0, CONFIG_SYS_IBAT3L@h 618 ori r4, r4, CONFIG_SYS_IBAT3L@l 619 addis r3, r0, CONFIG_SYS_IBAT3U@h 620 ori r3, r3, CONFIG_SYS_IBAT3U@l 621 mtspr IBAT3L, r4 622 mtspr IBAT3U, r3 623 624 /* DBAT 3 */ 625 addis r4, r0, CONFIG_SYS_DBAT3L@h 626 ori r4, r4, CONFIG_SYS_DBAT3L@l 627 addis r3, r0, CONFIG_SYS_DBAT3U@h 628 ori r3, r3, CONFIG_SYS_DBAT3U@l 629 mtspr DBAT3L, r4 630 mtspr DBAT3U, r3 631 632#ifdef CONFIG_HIGH_BATS 633 /* IBAT 4 */ 634 addis r4, r0, CONFIG_SYS_IBAT4L@h 635 ori r4, r4, CONFIG_SYS_IBAT4L@l 636 addis r3, r0, CONFIG_SYS_IBAT4U@h 637 ori r3, r3, CONFIG_SYS_IBAT4U@l 638 mtspr IBAT4L, r4 639 mtspr IBAT4U, r3 640 641 /* DBAT 4 */ 642 addis r4, r0, CONFIG_SYS_DBAT4L@h 643 ori r4, r4, CONFIG_SYS_DBAT4L@l 644 addis r3, r0, CONFIG_SYS_DBAT4U@h 645 ori r3, r3, CONFIG_SYS_DBAT4U@l 646 mtspr DBAT4L, r4 647 mtspr DBAT4U, r3 648 649 /* IBAT 5 */ 650 addis r4, r0, CONFIG_SYS_IBAT5L@h 651 ori r4, r4, CONFIG_SYS_IBAT5L@l 652 addis r3, r0, CONFIG_SYS_IBAT5U@h 653 ori r3, r3, CONFIG_SYS_IBAT5U@l 654 mtspr IBAT5L, r4 655 mtspr IBAT5U, r3 656 657 /* DBAT 5 */ 658 addis r4, r0, CONFIG_SYS_DBAT5L@h 659 ori r4, r4, CONFIG_SYS_DBAT5L@l 660 addis r3, r0, CONFIG_SYS_DBAT5U@h 661 ori r3, r3, CONFIG_SYS_DBAT5U@l 662 mtspr DBAT5L, r4 663 mtspr DBAT5U, r3 664 665 /* IBAT 6 */ 666 addis r4, r0, CONFIG_SYS_IBAT6L@h 667 ori r4, r4, CONFIG_SYS_IBAT6L@l 668 addis r3, r0, CONFIG_SYS_IBAT6U@h 669 ori r3, r3, CONFIG_SYS_IBAT6U@l 670 mtspr IBAT6L, r4 671 mtspr IBAT6U, r3 672 673 /* DBAT 6 */ 674 addis r4, r0, CONFIG_SYS_DBAT6L@h 675 ori r4, r4, CONFIG_SYS_DBAT6L@l 676 addis r3, r0, CONFIG_SYS_DBAT6U@h 677 ori r3, r3, CONFIG_SYS_DBAT6U@l 678 mtspr DBAT6L, r4 679 mtspr DBAT6U, r3 680 681 /* IBAT 7 */ 682 addis r4, r0, CONFIG_SYS_IBAT7L@h 683 ori r4, r4, CONFIG_SYS_IBAT7L@l 684 addis r3, r0, CONFIG_SYS_IBAT7U@h 685 ori r3, r3, CONFIG_SYS_IBAT7U@l 686 mtspr IBAT7L, r4 687 mtspr IBAT7U, r3 688 689 /* DBAT 7 */ 690 addis r4, r0, CONFIG_SYS_DBAT7L@h 691 ori r4, r4, CONFIG_SYS_DBAT7L@l 692 addis r3, r0, CONFIG_SYS_DBAT7U@h 693 ori r3, r3, CONFIG_SYS_DBAT7U@l 694 mtspr DBAT7L, r4 695 mtspr DBAT7U, r3 696#endif 697 698 isync 699 700 /* invalidate all tlb's 701 * 702 * From the 603e User Manual: "The 603e provides the ability to 703 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 704 * instruction invalidates the TLB entry indexed by the EA, and 705 * operates on both the instruction and data TLBs simultaneously 706 * invalidating four TLB entries (both sets in each TLB). The 707 * index corresponds to bits 15-19 of the EA. To invalidate all 708 * entries within both TLBs, 32 tlbie instructions should be 709 * issued, incrementing this field by one each time." 710 * 711 * "Note that the tlbia instruction is not implemented on the 712 * 603e." 713 * 714 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 715 * incrementing by 0x1000 each time. The code below is sort of 716 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 717 * 718 */ 719 lis r3, 0 720 lis r5, 2 721 7221: 723 tlbie r3 724 addi r3, r3, 0x1000 725 cmp 0, 0, r3, r5 726 blt 1b 727 728 blr 729 730/* Cache functions. 731 * 732 * Note: requires that all cache bits in 733 * HID0 are in the low half word. 734 */ 735#ifndef CONFIG_NAND_SPL 736 .globl icache_enable 737icache_enable: 738 mfspr r3, HID0 739 ori r3, r3, HID0_ICE 740 li r4, HID0_ICFI|HID0_ILOCK 741 andc r3, r3, r4 742 ori r4, r3, HID0_ICFI 743 isync 744 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 745 isync 746 mtspr HID0, r3 /* clears invalidate */ 747 blr 748 749 .globl icache_disable 750icache_disable: 751 mfspr r3, HID0 752 lis r4, 0 753 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 754 andc r3, r3, r4 755 isync 756 mtspr HID0, r3 /* clears invalidate, enable and lock */ 757 blr 758 759 .globl icache_status 760icache_status: 761 mfspr r3, HID0 762 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 763 blr 764#endif /* !CONFIG_NAND_SPL */ 765 766 .globl dcache_enable 767dcache_enable: 768 mfspr r3, HID0 769 li r5, HID0_DCFI|HID0_DLOCK 770 andc r3, r3, r5 771 ori r3, r3, HID0_DCE 772 sync 773 mtspr HID0, r3 /* enable, no invalidate */ 774 blr 775 776 .globl dcache_disable 777dcache_disable: 778 mflr r4 779 bl flush_dcache /* uses r3 and r5 */ 780 mfspr r3, HID0 781 li r5, HID0_DCE|HID0_DLOCK 782 andc r3, r3, r5 783 ori r5, r3, HID0_DCFI 784 sync 785 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 786 sync 787 mtspr HID0, r3 /* clears invalidate */ 788 mtlr r4 789 blr 790 791 .globl dcache_status 792dcache_status: 793 mfspr r3, HID0 794 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 795 blr 796 797 .globl flush_dcache 798flush_dcache: 799 lis r3, 0 800 lis r5, CONFIG_SYS_CACHELINE_SIZE 8011: cmp 0, 1, r3, r5 802 bge 2f 803 lwz r5, 0(r3) 804 lis r5, CONFIG_SYS_CACHELINE_SIZE 805 addi r3, r3, 0x4 806 b 1b 8072: blr 808 809/*-------------------------------------------------------------------*/ 810 811/* 812 * void relocate_code (addr_sp, gd, addr_moni) 813 * 814 * This "function" does not return, instead it continues in RAM 815 * after relocating the monitor code. 816 * 817 * r3 = dest 818 * r4 = src 819 * r5 = length in bytes 820 * r6 = cachelinesize 821 */ 822 .globl relocate_code 823relocate_code: 824 mr r1, r3 /* Set new stack pointer */ 825 mr r9, r4 /* Save copy of Global Data pointer */ 826 mr r10, r5 /* Save copy of Destination Address */ 827 828 GET_GOT 829#if defined(__pic__) && __pic__ == 1 830 /* Needed for upcoming -msingle-pic-base */ 831 bl _GLOBAL_OFFSET_TABLE_@local-4 832 mflr r30 833#endif 834 mr r3, r5 /* Destination Address */ 835 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 836 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 837 lwz r5, GOT(__bss_start) 838 sub r5, r5, r4 839 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 840 841 /* 842 * Fix GOT pointer: 843 * 844 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 845 * + Destination Address 846 * 847 * Offset: 848 */ 849 sub r15, r10, r4 850 851 /* First our own GOT */ 852 add r12, r12, r15 853 /* then the one used by the C code */ 854 add r30, r30, r15 855 856 /* 857 * Now relocate code 858 */ 859 860 cmplw cr1,r3,r4 861 addi r0,r5,3 862 srwi. r0,r0,2 863 beq cr1,4f /* In place copy is not necessary */ 864 beq 7f /* Protect against 0 count */ 865 mtctr r0 866 bge cr1,2f 867 la r8,-4(r4) 868 la r7,-4(r3) 869 870 /* copy */ 8711: lwzu r0,4(r8) 872 stwu r0,4(r7) 873 bdnz 1b 874 875 addi r0,r5,3 876 srwi. r0,r0,2 877 mtctr r0 878 la r8,-4(r4) 879 la r7,-4(r3) 880 881 /* and compare */ 88220: lwzu r20,4(r8) 883 lwzu r21,4(r7) 884 xor. r22, r20, r21 885 bne 30f 886 bdnz 20b 887 b 4f 888 889 /* compare failed */ 89030: li r3, 0 891 blr 892 8932: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 894 add r8,r4,r0 895 add r7,r3,r0 8963: lwzu r0,-4(r8) 897 stwu r0,-4(r7) 898 bdnz 3b 899 900/* 901 * Now flush the cache: note that we must start from a cache aligned 902 * address. Otherwise we might miss one cache line. 903 */ 9044: cmpwi r6,0 905 add r5,r3,r5 906 beq 7f /* Always flush prefetch queue in any case */ 907 subi r0,r6,1 908 andc r3,r3,r0 909 mr r4,r3 9105: dcbst 0,r4 911 add r4,r4,r6 912 cmplw r4,r5 913 blt 5b 914 sync /* Wait for all dcbst to complete on bus */ 915 mr r4,r3 9166: icbi 0,r4 917 add r4,r4,r6 918 cmplw r4,r5 919 blt 6b 9207: sync /* Wait for all icbi to complete on bus */ 921 isync 922 923/* 924 * We are done. Do not return, instead branch to second part of board 925 * initialization, now running from RAM. 926 */ 927 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 928 mtlr r0 929 blr 930 931in_ram: 932 933 /* 934 * Relocation Function, r12 point to got2+0x8000 935 * 936 * Adjust got2 pointers, no need to check for 0, this code 937 * already puts a few entries in the table. 938 */ 939 li r0,__got2_entries@sectoff@l 940 la r3,GOT(_GOT2_TABLE_) 941 lwz r11,GOT(_GOT2_TABLE_) 942 mtctr r0 943 sub r11,r3,r11 944 addi r3,r3,-4 9451: lwzu r0,4(r3) 946 cmpwi r0,0 947 beq- 2f 948 add r0,r0,r11 949 stw r0,0(r3) 9502: bdnz 1b 951 952#ifndef CONFIG_NAND_SPL 953 /* 954 * Now adjust the fixups and the pointers to the fixups 955 * in case we need to move ourselves again. 956 */ 957 li r0,__fixup_entries@sectoff@l 958 lwz r3,GOT(_FIXUP_TABLE_) 959 cmpwi r0,0 960 mtctr r0 961 addi r3,r3,-4 962 beq 4f 9633: lwzu r4,4(r3) 964 lwzux r0,r4,r11 965 cmpwi r0,0 966 add r0,r0,r11 967 stw r4,0(r3) 968 beq- 5f 969 stw r0,0(r4) 9705: bdnz 3b 9714: 972#endif 973 974clear_bss: 975 /* 976 * Now clear BSS segment 977 */ 978 lwz r3,GOT(__bss_start) 979#if defined(CONFIG_HYMOD) 980 /* 981 * For HYMOD - the environment is the very last item in flash. 982 * The real .bss stops just before environment starts, so only 983 * clear up to that point. 984 * 985 * taken from mods for FADS board 986 */ 987 lwz r4,GOT(environment) 988#else 989 lwz r4,GOT(__bss_end__) 990#endif 991 992 cmplw 0, r3, r4 993 beq 6f 994 995 li r0, 0 9965: 997 stw r0, 0(r3) 998 addi r3, r3, 4 999 cmplw 0, r3, r4 1000 bne 5b 10016: 1002 1003 mr r3, r9 /* Global Data pointer */ 1004 mr r4, r10 /* Destination Address */ 1005 bl board_init_r 1006 1007#ifndef CONFIG_NAND_SPL 1008 /* 1009 * Copy exception vector code to low memory 1010 * 1011 * r3: dest_addr 1012 * r7: source address, r8: end address, r9: target address 1013 */ 1014 .globl trap_init 1015trap_init: 1016 mflr r4 /* save link register */ 1017 GET_GOT 1018 lwz r7, GOT(_start) 1019 lwz r8, GOT(_end_of_vectors) 1020 1021 li r9, 0x100 /* reset vector always at 0x100 */ 1022 1023 cmplw 0, r7, r8 1024 bgelr /* return if r7>=r8 - just in case */ 10251: 1026 lwz r0, 0(r7) 1027 stw r0, 0(r9) 1028 addi r7, r7, 4 1029 addi r9, r9, 4 1030 cmplw 0, r7, r8 1031 bne 1b 1032 1033 /* 1034 * relocate `hdlr' and `int_return' entries 1035 */ 1036 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1037 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10382: 1039 bl trap_reloc 1040 addi r7, r7, 0x100 /* next exception vector */ 1041 cmplw 0, r7, r8 1042 blt 2b 1043 1044 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1045 bl trap_reloc 1046 1047 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1048 bl trap_reloc 1049 1050 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1051 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10523: 1053 bl trap_reloc 1054 addi r7, r7, 0x100 /* next exception vector */ 1055 cmplw 0, r7, r8 1056 blt 3b 1057 1058 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1059 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10604: 1061 bl trap_reloc 1062 addi r7, r7, 0x100 /* next exception vector */ 1063 cmplw 0, r7, r8 1064 blt 4b 1065 1066 mfmsr r3 /* now that the vectors have */ 1067 lis r7, MSR_IP@h /* relocated into low memory */ 1068 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1069 andc r3, r3, r7 /* (if it was on) */ 1070 SYNC /* Some chip revs need this... */ 1071 mtmsr r3 1072 SYNC 1073 1074 mtlr r4 /* restore link register */ 1075 blr 1076 1077#endif /* !CONFIG_NAND_SPL */ 1078 1079#ifdef CONFIG_SYS_INIT_RAM_LOCK 1080lock_ram_in_cache: 1081 /* Allocate Initial RAM in data cache. 1082 */ 1083 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1084 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1085 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1086 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1087 mtctr r4 10881: 1089 dcbz r0, r3 1090 addi r3, r3, 32 1091 bdnz 1b 1092 1093 /* Lock the data cache */ 1094 mfspr r0, HID0 1095 ori r0, r0, HID0_DLOCK 1096 sync 1097 mtspr HID0, r0 1098 sync 1099 blr 1100 1101#ifndef CONFIG_NAND_SPL 1102.globl unlock_ram_in_cache 1103unlock_ram_in_cache: 1104 /* invalidate the INIT_RAM section */ 1105 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1106 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1107 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1108 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1109 mtctr r4 11101: icbi r0, r3 1111 dcbi r0, r3 1112 addi r3, r3, 32 1113 bdnz 1b 1114 sync /* Wait for all icbi to complete on bus */ 1115 isync 1116 1117 /* Unlock the data cache and invalidate it */ 1118 mfspr r3, HID0 1119 li r5, HID0_DLOCK|HID0_DCFI 1120 andc r3, r3, r5 /* no invalidate, unlock */ 1121 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1122 sync 1123 mtspr HID0, r5 /* invalidate, unlock */ 1124 sync 1125 mtspr HID0, r3 /* no invalidate, unlock */ 1126 blr 1127#endif /* !CONFIG_NAND_SPL */ 1128#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1129 1130#ifdef CONFIG_SYS_FLASHBOOT 1131map_flash_by_law1: 1132 /* When booting from ROM (Flash or EPROM), clear the */ 1133 /* Address Mask in OR0 so ROM appears everywhere */ 1134 /*----------------------------------------------------*/ 1135 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1136 lwz r4, OR0@l(r3) 1137 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1138 and r4, r4, r5 1139 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1140 1141 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1142 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1143 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1144 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1145 * 0xFF800. From the hard resetting to here, the processor fetched and 1146 * executed the instructions one by one. There is not absolutely 1147 * jumping happened. Laterly, the u-boot code has to do an absolutely 1148 * jumping to tell the CPU instruction fetching component what the 1149 * u-boot TEXT base address is. Because the TEXT base resides in the 1150 * boot ROM memory space, to garantee the code can run smoothly after 1151 * that jumping, we must map in the entire boot ROM by Local Access 1152 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1153 * address for boot ROM, such as 0xFE000000. In this case, the default 1154 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1155 * need another window to map in it. 1156 */ 1157 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1158 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1159 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1160 1161 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1162 lis r4, (0x80000012)@h 1163 ori r4, r4, (0x80000012)@l 1164 li r5, CONFIG_SYS_FLASH_SIZE 11651: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1166 addi r4, r4, 1 1167 bne 1b 1168 1169 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1170 /* Wait for HW to catch up */ 1171 lwz r4, LBLAWAR1(r3) 1172 twi 0,r4,0 1173 isync 1174 blr 1175 1176 /* Though all the LBIU Local Access Windows and LBC Banks will be 1177 * initialized in the C code, we'd better configure boot ROM's 1178 * window 0 and bank 0 correctly at here. 1179 */ 1180remap_flash_by_law0: 1181 /* Initialize the BR0 with the boot ROM starting address. */ 1182 lwz r4, BR0(r3) 1183 li r5, 0x7FFF 1184 and r4, r4, r5 1185 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1186 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1187 or r5, r5, r4 1188 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1189 1190 lwz r4, OR0(r3) 1191 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1192 or r4, r4, r5 1193 stw r4, OR0(r3) 1194 1195 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1196 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1197 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1198 1199 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1200 lis r4, (0x80000012)@h 1201 ori r4, r4, (0x80000012)@l 1202 li r5, CONFIG_SYS_FLASH_SIZE 12031: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1204 addi r4, r4, 1 1205 bne 1b 1206 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1207 1208 1209 xor r4, r4, r4 1210 stw r4, LBLAWBAR1(r3) 1211 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1212 /* Wait for HW to catch up */ 1213 lwz r4, LBLAWAR1(r3) 1214 twi 0,r4,0 1215 isync 1216 blr 1217#endif /* CONFIG_SYS_FLASHBOOT */ 1218