1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 28 */ 29 30#include <config.h> 31#include <mpc83xx.h> 32#include <timestamp.h> 33#include <version.h> 34 35#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43#include <asm/u-boot.h> 44 45#ifndef CONFIG_IDENT_STRING 46#define CONFIG_IDENT_STRING "MPC83XX" 47#endif 48 49/* We don't want the MMU yet. 50 */ 51#undef MSR_KERNEL 52 53/* 54 * Floating Point enable, Machine Check and Recoverable Interr. 55 */ 56#ifdef DEBUG 57#define MSR_KERNEL (MSR_FP|MSR_RI) 58#else 59#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 60#endif 61 62#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) 63#define CONFIG_SYS_FLASHBOOT 64#endif 65 66/* 67 * Set up GOT: Global Offset Table 68 * 69 * Use r12 to access the GOT 70 */ 71 START_GOT 72 GOT_ENTRY(_GOT2_TABLE_) 73 GOT_ENTRY(__bss_start) 74 GOT_ENTRY(_end) 75 76#ifndef CONFIG_NAND_SPL 77 GOT_ENTRY(_FIXUP_TABLE_) 78 GOT_ENTRY(_start) 79 GOT_ENTRY(_start_of_vectors) 80 GOT_ENTRY(_end_of_vectors) 81 GOT_ENTRY(transfer_to_handler) 82#endif 83 END_GOT 84 85/* 86 * The Hard Reset Configuration Word (HRCW) table is in the first 64 87 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 88 * times so the processor can fetch it out of flash whether the flash 89 * is 8, 16, 32, or 64 bits wide (hardware trickery). 90 */ 91 .text 92#define _HRCW_TABLE_ENTRY(w) \ 93 .fill 8,1,(((w)>>24)&0xff); \ 94 .fill 8,1,(((w)>>16)&0xff); \ 95 .fill 8,1,(((w)>> 8)&0xff); \ 96 .fill 8,1,(((w) )&0xff) 97 98 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 99 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 100 101/* 102 * Magic number and version string - put it after the HRCW since it 103 * cannot be first in flash like it is in many other processors. 104 */ 105 .long 0x27051956 /* U-Boot Magic Number */ 106 107 .globl version_string 108version_string: 109 .ascii U_BOOT_VERSION 110 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 111 .ascii " ", CONFIG_IDENT_STRING, "\0" 112 113 .align 2 114 115 .globl enable_addr_trans 116enable_addr_trans: 117 /* enable address translation */ 118 mfmsr r5 119 ori r5, r5, (MSR_IR | MSR_DR) 120 mtmsr r5 121 isync 122 blr 123 124 .globl disable_addr_trans 125disable_addr_trans: 126 /* disable address translation */ 127 mflr r4 128 mfmsr r3 129 andi. r0, r3, (MSR_IR | MSR_DR) 130 beqlr 131 andc r3, r3, r0 132 mtspr SRR0, r4 133 mtspr SRR1, r3 134 rfi 135 136 .globl get_pvr 137get_pvr: 138 mfspr r3, PVR 139 blr 140 141 .globl ppcDWstore 142ppcDWstore: 143 lfd 1, 0(r4) 144 stfd 1, 0(r3) 145 blr 146 147 .globl ppcDWload 148ppcDWload: 149 lfd 1, 0(r3) 150 stfd 1, 0(r4) 151 blr 152 153#ifndef CONFIG_DEFAULT_IMMR 154#error CONFIG_DEFAULT_IMMR must be defined 155#endif /* CONFIG_SYS_DEFAULT_IMMR */ 156#ifndef CONFIG_SYS_IMMR 157#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 158#endif /* CONFIG_SYS_IMMR */ 159 160/* 161 * After configuration, a system reset exception is executed using the 162 * vector at offset 0x100 relative to the base set by MSR[IP]. If 163 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 164 * base address is 0xfff00000. In the case of a Power On Reset or Hard 165 * Reset, the value of MSR[IP] is determined by the CIP field in the 166 * HRCW. 167 * 168 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 169 * This determines the location of the boot ROM (flash or EPROM) in the 170 * processor's address space at boot time. As long as the HRCW is set up 171 * so that we eventually end up executing the code below when the 172 * processor executes the reset exception, the actual values used should 173 * not matter. 174 * 175 * Once we have got here, the address mask in OR0 is cleared so that the 176 * bottom 32K of the boot ROM is effectively repeated all throughout the 177 * processor's address space, after which we can jump to the absolute 178 * address at which the boot ROM was linked at compile time, and proceed 179 * to initialise the memory controller without worrying if the rug will 180 * be pulled out from under us, so to speak (it will be fine as long as 181 * we configure BR0 with the same boot ROM link address). 182 */ 183 . = EXC_OFF_SYS_RESET 184 185 .globl _start 186_start: /* time t 0 */ 187 lis r4, CONFIG_DEFAULT_IMMR@h 188 nop 189 190 mfmsr r5 /* save msr contents */ 191 192 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 193 bl 1f 1941: mflr r7 195 196 lis r3, CONFIG_SYS_IMMR@h 197 ori r3, r3, CONFIG_SYS_IMMR@l 198 199 lwz r6, IMMRBAR(r4) 200 isync 201 202 stw r3, IMMRBAR(r4) 203 lwz r6, 0(r7) /* Arbitrary external load */ 204 isync 205 206 lwz r6, IMMRBAR(r3) 207 isync 208 209 /* Initialise the E300 processor core */ 210 /*------------------------------------------*/ 211 212#ifdef CONFIG_NAND_SPL 213 /* The FCM begins execution after only the first page 214 * is loaded. Wait for the rest before branching 215 * to another flash page. 216 */ 2171: lwz r6, 0x50b0(r3) 218 andi. r6, r6, 1 219 beq 1b 220#endif 221 222 bl init_e300_core 223 224#ifdef CONFIG_SYS_FLASHBOOT 225 226 /* Inflate flash location so it appears everywhere, calculate */ 227 /* the absolute address in final location of the FLASH, jump */ 228 /* there and deflate the flash size back to minimal size */ 229 /*------------------------------------------------------------*/ 230 bl map_flash_by_law1 231 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 232 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 233 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 234 mtlr r5 235 blr 236in_flash: 237#if 1 /* Remapping flash with LAW0. */ 238 bl remap_flash_by_law0 239#endif 240#endif /* CONFIG_SYS_FLASHBOOT */ 241 242 /* setup the bats */ 243 bl setup_bats 244 sync 245 246 /* 247 * Cache must be enabled here for stack-in-cache trick. 248 * This means we need to enable the BATS. 249 * This means: 250 * 1) for the EVB, original gt regs need to be mapped 251 * 2) need to have an IBAT for the 0xf region, 252 * we are running there! 253 * Cache should be turned on after BATs, since by default 254 * everything is write-through. 255 * The init-mem BAT can be reused after reloc. The old 256 * gt-regs BAT can be reused after board_init_f calls 257 * board_early_init_f (EVB only). 258 */ 259 /* enable address translation */ 260 bl enable_addr_trans 261 sync 262 263 /* enable the data cache */ 264 bl dcache_enable 265 sync 266#ifdef CONFIG_SYS_INIT_RAM_LOCK 267 bl lock_ram_in_cache 268 sync 269#endif 270 271 /* set up the stack pointer in our newly created 272 * cache-ram (r1) */ 273 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 274 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 275 276 li r0, 0 /* Make room for stack frame header and */ 277 stwu r0, -4(r1) /* clear final stack frame so that */ 278 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 279 280 281 /* let the C-code set up the rest */ 282 /* */ 283 /* Be careful to keep code relocatable & stack humble */ 284 /*------------------------------------------------------*/ 285 286 GET_GOT /* initialize GOT access */ 287 288 /* r3: IMMR */ 289 lis r3, CONFIG_SYS_IMMR@h 290 /* run low-level CPU init code (in Flash)*/ 291 bl cpu_init_f 292 293 /* run 1st part of board init code (in Flash)*/ 294 bl board_init_f 295 296 /* NOTREACHED - board_init_f() does not return */ 297 298#ifndef CONFIG_NAND_SPL 299/* 300 * Vector Table 301 */ 302 303 .globl _start_of_vectors 304_start_of_vectors: 305 306/* Machine check */ 307 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 308 309/* Data Storage exception. */ 310 STD_EXCEPTION(0x300, DataStorage, UnknownException) 311 312/* Instruction Storage exception. */ 313 STD_EXCEPTION(0x400, InstStorage, UnknownException) 314 315/* External Interrupt exception. */ 316#ifndef FIXME 317 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 318#endif 319 320/* Alignment exception. */ 321 . = 0x600 322Alignment: 323 EXCEPTION_PROLOG(SRR0, SRR1) 324 mfspr r4,DAR 325 stw r4,_DAR(r21) 326 mfspr r5,DSISR 327 stw r5,_DSISR(r21) 328 addi r3,r1,STACK_FRAME_OVERHEAD 329 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 330 331/* Program check exception */ 332 . = 0x700 333ProgramCheck: 334 EXCEPTION_PROLOG(SRR0, SRR1) 335 addi r3,r1,STACK_FRAME_OVERHEAD 336 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 337 MSR_KERNEL, COPY_EE) 338 339 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 340 341 /* I guess we could implement decrementer, and may have 342 * to someday for timekeeping. 343 */ 344 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 345 346 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 347 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 348 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 349 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 350 351 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 352 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 353 354 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 355 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 356 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 357#ifdef DEBUG 358 . = 0x1300 359 /* 360 * This exception occurs when the program counter matches the 361 * Instruction Address Breakpoint Register (IABR). 362 * 363 * I want the cpu to halt if this occurs so I can hunt around 364 * with the debugger and look at things. 365 * 366 * When DEBUG is defined, both machine check enable (in the MSR) 367 * and checkstop reset enable (in the reset mode register) are 368 * turned off and so a checkstop condition will result in the cpu 369 * halting. 370 * 371 * I force the cpu into a checkstop condition by putting an illegal 372 * instruction here (at least this is the theory). 373 * 374 * well - that didnt work, so just do an infinite loop! 375 */ 3761: b 1b 377#else 378 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 379#endif 380 STD_EXCEPTION(0x1400, SMI, UnknownException) 381 382 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 383 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 384 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 385 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 386 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 387 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 388 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 389 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 390 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 391 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 392 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 393 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 394 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 395 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 396 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 397 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 398 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 399 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 400 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 401 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 402 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 403 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 404 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 405 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 406 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 407 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 408 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 409 410 411 .globl _end_of_vectors 412_end_of_vectors: 413 414 . = 0x3000 415 416/* 417 * This code finishes saving the registers to the exception frame 418 * and jumps to the appropriate handler for the exception. 419 * Register r21 is pointer into trap frame, r1 has new stack pointer. 420 */ 421 .globl transfer_to_handler 422transfer_to_handler: 423 stw r22,_NIP(r21) 424 lis r22,MSR_POW@h 425 andc r23,r23,r22 426 stw r23,_MSR(r21) 427 SAVE_GPR(7, r21) 428 SAVE_4GPRS(8, r21) 429 SAVE_8GPRS(12, r21) 430 SAVE_8GPRS(24, r21) 431 mflr r23 432 andi. r24,r23,0x3f00 /* get vector offset */ 433 stw r24,TRAP(r21) 434 li r22,0 435 stw r22,RESULT(r21) 436 lwz r24,0(r23) /* virtual address of handler */ 437 lwz r23,4(r23) /* where to go when done */ 438 mtspr SRR0,r24 439 mtspr SRR1,r20 440 mtlr r23 441 SYNC 442 rfi /* jump to handler, enable MMU */ 443 444int_return: 445 mfmsr r28 /* Disable interrupts */ 446 li r4,0 447 ori r4,r4,MSR_EE 448 andc r28,r28,r4 449 SYNC /* Some chip revs need this... */ 450 mtmsr r28 451 SYNC 452 lwz r2,_CTR(r1) 453 lwz r0,_LINK(r1) 454 mtctr r2 455 mtlr r0 456 lwz r2,_XER(r1) 457 lwz r0,_CCR(r1) 458 mtspr XER,r2 459 mtcrf 0xFF,r0 460 REST_10GPRS(3, r1) 461 REST_10GPRS(13, r1) 462 REST_8GPRS(23, r1) 463 REST_GPR(31, r1) 464 lwz r2,_NIP(r1) /* Restore environment */ 465 lwz r0,_MSR(r1) 466 mtspr SRR0,r2 467 mtspr SRR1,r0 468 lwz r0,GPR0(r1) 469 lwz r2,GPR2(r1) 470 lwz r1,GPR1(r1) 471 SYNC 472 rfi 473#endif /* !CONFIG_NAND_SPL */ 474 475/* 476 * This code initialises the E300 processor core 477 * (conforms to PowerPC 603e spec) 478 * Note: expects original MSR contents to be in r5. 479 */ 480 .globl init_e300_core 481init_e300_core: /* time t 10 */ 482 /* Initialize machine status; enable machine check interrupt */ 483 /*-----------------------------------------------------------*/ 484 485 li r3, MSR_KERNEL /* Set ME and RI flags */ 486 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 487#ifdef DEBUG 488 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 489#endif 490 SYNC /* Some chip revs need this... */ 491 mtmsr r3 492 SYNC 493 mtspr SRR1, r3 /* Make SRR1 match MSR */ 494 495 496 lis r3, CONFIG_SYS_IMMR@h 497#if defined(CONFIG_WATCHDOG) 498 /* Initialise the Watchdog values and reset it (if req) */ 499 /*------------------------------------------------------*/ 500 lis r4, CONFIG_SYS_WATCHDOG_VALUE 501 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 502 stw r4, SWCRR(r3) 503 504 /* and reset it */ 505 506 li r4, 0x556C 507 sth r4, SWSRR@l(r3) 508 li r4, -0x55C7 509 sth r4, SWSRR@l(r3) 510#else 511 /* Disable Watchdog */ 512 /*-------------------*/ 513 lwz r4, SWCRR(r3) 514 /* Check to see if its enabled for disabling 515 once disabled by SW you can't re-enable */ 516 andi. r4, r4, 0x4 517 beq 1f 518 xor r4, r4, r4 519 stw r4, SWCRR(r3) 5201: 521#endif /* CONFIG_WATCHDOG */ 522 523#if defined(CONFIG_MASK_AER_AO) 524 /* Write the Arbiter Event Enable to mask Address Only traps. */ 525 /* This prevents the dcbz instruction from being trapped when */ 526 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 527 /* COHERENCY bit is set in the WIMG bits, which is often */ 528 /* needed for PCI operation. */ 529 lwz r4, 0x0808(r3) 530 rlwinm r0, r4, 0, ~AER_AO 531 stw r0, 0x0808(r3) 532#endif /* CONFIG_MASK_AER_AO */ 533 534 /* Initialize the Hardware Implementation-dependent Registers */ 535 /* HID0 also contains cache control */ 536 /* - force invalidation of data and instruction caches */ 537 /*------------------------------------------------------*/ 538 539 lis r3, CONFIG_SYS_HID0_INIT@h 540 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 541 SYNC 542 mtspr HID0, r3 543 544 lis r3, CONFIG_SYS_HID0_FINAL@h 545 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 546 SYNC 547 mtspr HID0, r3 548 549 lis r3, CONFIG_SYS_HID2@h 550 ori r3, r3, CONFIG_SYS_HID2@l 551 SYNC 552 mtspr HID2, r3 553 554 /* Done! */ 555 /*------------------------------*/ 556 blr 557 558 /* setup_bats - set them up to some initial state */ 559 .globl setup_bats 560setup_bats: 561 addis r0, r0, 0x0000 562 563 /* IBAT 0 */ 564 addis r4, r0, CONFIG_SYS_IBAT0L@h 565 ori r4, r4, CONFIG_SYS_IBAT0L@l 566 addis r3, r0, CONFIG_SYS_IBAT0U@h 567 ori r3, r3, CONFIG_SYS_IBAT0U@l 568 mtspr IBAT0L, r4 569 mtspr IBAT0U, r3 570 571 /* DBAT 0 */ 572 addis r4, r0, CONFIG_SYS_DBAT0L@h 573 ori r4, r4, CONFIG_SYS_DBAT0L@l 574 addis r3, r0, CONFIG_SYS_DBAT0U@h 575 ori r3, r3, CONFIG_SYS_DBAT0U@l 576 mtspr DBAT0L, r4 577 mtspr DBAT0U, r3 578 579 /* IBAT 1 */ 580 addis r4, r0, CONFIG_SYS_IBAT1L@h 581 ori r4, r4, CONFIG_SYS_IBAT1L@l 582 addis r3, r0, CONFIG_SYS_IBAT1U@h 583 ori r3, r3, CONFIG_SYS_IBAT1U@l 584 mtspr IBAT1L, r4 585 mtspr IBAT1U, r3 586 587 /* DBAT 1 */ 588 addis r4, r0, CONFIG_SYS_DBAT1L@h 589 ori r4, r4, CONFIG_SYS_DBAT1L@l 590 addis r3, r0, CONFIG_SYS_DBAT1U@h 591 ori r3, r3, CONFIG_SYS_DBAT1U@l 592 mtspr DBAT1L, r4 593 mtspr DBAT1U, r3 594 595 /* IBAT 2 */ 596 addis r4, r0, CONFIG_SYS_IBAT2L@h 597 ori r4, r4, CONFIG_SYS_IBAT2L@l 598 addis r3, r0, CONFIG_SYS_IBAT2U@h 599 ori r3, r3, CONFIG_SYS_IBAT2U@l 600 mtspr IBAT2L, r4 601 mtspr IBAT2U, r3 602 603 /* DBAT 2 */ 604 addis r4, r0, CONFIG_SYS_DBAT2L@h 605 ori r4, r4, CONFIG_SYS_DBAT2L@l 606 addis r3, r0, CONFIG_SYS_DBAT2U@h 607 ori r3, r3, CONFIG_SYS_DBAT2U@l 608 mtspr DBAT2L, r4 609 mtspr DBAT2U, r3 610 611 /* IBAT 3 */ 612 addis r4, r0, CONFIG_SYS_IBAT3L@h 613 ori r4, r4, CONFIG_SYS_IBAT3L@l 614 addis r3, r0, CONFIG_SYS_IBAT3U@h 615 ori r3, r3, CONFIG_SYS_IBAT3U@l 616 mtspr IBAT3L, r4 617 mtspr IBAT3U, r3 618 619 /* DBAT 3 */ 620 addis r4, r0, CONFIG_SYS_DBAT3L@h 621 ori r4, r4, CONFIG_SYS_DBAT3L@l 622 addis r3, r0, CONFIG_SYS_DBAT3U@h 623 ori r3, r3, CONFIG_SYS_DBAT3U@l 624 mtspr DBAT3L, r4 625 mtspr DBAT3U, r3 626 627#ifdef CONFIG_HIGH_BATS 628 /* IBAT 4 */ 629 addis r4, r0, CONFIG_SYS_IBAT4L@h 630 ori r4, r4, CONFIG_SYS_IBAT4L@l 631 addis r3, r0, CONFIG_SYS_IBAT4U@h 632 ori r3, r3, CONFIG_SYS_IBAT4U@l 633 mtspr IBAT4L, r4 634 mtspr IBAT4U, r3 635 636 /* DBAT 4 */ 637 addis r4, r0, CONFIG_SYS_DBAT4L@h 638 ori r4, r4, CONFIG_SYS_DBAT4L@l 639 addis r3, r0, CONFIG_SYS_DBAT4U@h 640 ori r3, r3, CONFIG_SYS_DBAT4U@l 641 mtspr DBAT4L, r4 642 mtspr DBAT4U, r3 643 644 /* IBAT 5 */ 645 addis r4, r0, CONFIG_SYS_IBAT5L@h 646 ori r4, r4, CONFIG_SYS_IBAT5L@l 647 addis r3, r0, CONFIG_SYS_IBAT5U@h 648 ori r3, r3, CONFIG_SYS_IBAT5U@l 649 mtspr IBAT5L, r4 650 mtspr IBAT5U, r3 651 652 /* DBAT 5 */ 653 addis r4, r0, CONFIG_SYS_DBAT5L@h 654 ori r4, r4, CONFIG_SYS_DBAT5L@l 655 addis r3, r0, CONFIG_SYS_DBAT5U@h 656 ori r3, r3, CONFIG_SYS_DBAT5U@l 657 mtspr DBAT5L, r4 658 mtspr DBAT5U, r3 659 660 /* IBAT 6 */ 661 addis r4, r0, CONFIG_SYS_IBAT6L@h 662 ori r4, r4, CONFIG_SYS_IBAT6L@l 663 addis r3, r0, CONFIG_SYS_IBAT6U@h 664 ori r3, r3, CONFIG_SYS_IBAT6U@l 665 mtspr IBAT6L, r4 666 mtspr IBAT6U, r3 667 668 /* DBAT 6 */ 669 addis r4, r0, CONFIG_SYS_DBAT6L@h 670 ori r4, r4, CONFIG_SYS_DBAT6L@l 671 addis r3, r0, CONFIG_SYS_DBAT6U@h 672 ori r3, r3, CONFIG_SYS_DBAT6U@l 673 mtspr DBAT6L, r4 674 mtspr DBAT6U, r3 675 676 /* IBAT 7 */ 677 addis r4, r0, CONFIG_SYS_IBAT7L@h 678 ori r4, r4, CONFIG_SYS_IBAT7L@l 679 addis r3, r0, CONFIG_SYS_IBAT7U@h 680 ori r3, r3, CONFIG_SYS_IBAT7U@l 681 mtspr IBAT7L, r4 682 mtspr IBAT7U, r3 683 684 /* DBAT 7 */ 685 addis r4, r0, CONFIG_SYS_DBAT7L@h 686 ori r4, r4, CONFIG_SYS_DBAT7L@l 687 addis r3, r0, CONFIG_SYS_DBAT7U@h 688 ori r3, r3, CONFIG_SYS_DBAT7U@l 689 mtspr DBAT7L, r4 690 mtspr DBAT7U, r3 691#endif 692 693 isync 694 695 /* invalidate all tlb's 696 * 697 * From the 603e User Manual: "The 603e provides the ability to 698 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 699 * instruction invalidates the TLB entry indexed by the EA, and 700 * operates on both the instruction and data TLBs simultaneously 701 * invalidating four TLB entries (both sets in each TLB). The 702 * index corresponds to bits 15-19 of the EA. To invalidate all 703 * entries within both TLBs, 32 tlbie instructions should be 704 * issued, incrementing this field by one each time." 705 * 706 * "Note that the tlbia instruction is not implemented on the 707 * 603e." 708 * 709 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 710 * incrementing by 0x1000 each time. The code below is sort of 711 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 712 * 713 */ 714 lis r3, 0 715 lis r5, 2 716 7171: 718 tlbie r3 719 addi r3, r3, 0x1000 720 cmp 0, 0, r3, r5 721 blt 1b 722 723 blr 724 725/* Cache functions. 726 * 727 * Note: requires that all cache bits in 728 * HID0 are in the low half word. 729 */ 730#ifndef CONFIG_NAND_SPL 731 .globl icache_enable 732icache_enable: 733 mfspr r3, HID0 734 ori r3, r3, HID0_ICE 735 li r4, HID0_ICFI|HID0_ILOCK 736 andc r3, r3, r4 737 ori r4, r3, HID0_ICFI 738 isync 739 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 740 isync 741 mtspr HID0, r3 /* clears invalidate */ 742 blr 743 744 .globl icache_disable 745icache_disable: 746 mfspr r3, HID0 747 lis r4, 0 748 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 749 andc r3, r3, r4 750 isync 751 mtspr HID0, r3 /* clears invalidate, enable and lock */ 752 blr 753 754 .globl icache_status 755icache_status: 756 mfspr r3, HID0 757 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 758 blr 759#endif /* !CONFIG_NAND_SPL */ 760 761 .globl dcache_enable 762dcache_enable: 763 mfspr r3, HID0 764 li r5, HID0_DCFI|HID0_DLOCK 765 andc r3, r3, r5 766 ori r3, r3, HID0_DCE 767 sync 768 mtspr HID0, r3 /* enable, no invalidate */ 769 blr 770 771 .globl dcache_disable 772dcache_disable: 773 mflr r4 774 bl flush_dcache /* uses r3 and r5 */ 775 mfspr r3, HID0 776 li r5, HID0_DCE|HID0_DLOCK 777 andc r3, r3, r5 778 ori r5, r3, HID0_DCFI 779 sync 780 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 781 sync 782 mtspr HID0, r3 /* clears invalidate */ 783 mtlr r4 784 blr 785 786 .globl dcache_status 787dcache_status: 788 mfspr r3, HID0 789 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 790 blr 791 792 .globl flush_dcache 793flush_dcache: 794 lis r3, 0 795 lis r5, CONFIG_SYS_CACHELINE_SIZE 7961: cmp 0, 1, r3, r5 797 bge 2f 798 lwz r5, 0(r3) 799 lis r5, CONFIG_SYS_CACHELINE_SIZE 800 addi r3, r3, 0x4 801 b 1b 8022: blr 803 804/*-------------------------------------------------------------------*/ 805 806/* 807 * void relocate_code (addr_sp, gd, addr_moni) 808 * 809 * This "function" does not return, instead it continues in RAM 810 * after relocating the monitor code. 811 * 812 * r3 = dest 813 * r4 = src 814 * r5 = length in bytes 815 * r6 = cachelinesize 816 */ 817 .globl relocate_code 818relocate_code: 819 mr r1, r3 /* Set new stack pointer */ 820 mr r9, r4 /* Save copy of Global Data pointer */ 821 mr r10, r5 /* Save copy of Destination Address */ 822 823 GET_GOT 824 mr r3, r5 /* Destination Address */ 825 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 826 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 827 lwz r5, GOT(__bss_start) 828 sub r5, r5, r4 829 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 830 831 /* 832 * Fix GOT pointer: 833 * 834 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 835 * + Destination Address 836 * 837 * Offset: 838 */ 839 sub r15, r10, r4 840 841 /* First our own GOT */ 842 add r12, r12, r15 843 /* then the one used by the C code */ 844 add r30, r30, r15 845 846 /* 847 * Now relocate code 848 */ 849 850 cmplw cr1,r3,r4 851 addi r0,r5,3 852 srwi. r0,r0,2 853 beq cr1,4f /* In place copy is not necessary */ 854 beq 7f /* Protect against 0 count */ 855 mtctr r0 856 bge cr1,2f 857 la r8,-4(r4) 858 la r7,-4(r3) 859 860 /* copy */ 8611: lwzu r0,4(r8) 862 stwu r0,4(r7) 863 bdnz 1b 864 865 addi r0,r5,3 866 srwi. r0,r0,2 867 mtctr r0 868 la r8,-4(r4) 869 la r7,-4(r3) 870 871 /* and compare */ 87220: lwzu r20,4(r8) 873 lwzu r21,4(r7) 874 xor. r22, r20, r21 875 bne 30f 876 bdnz 20b 877 b 4f 878 879 /* compare failed */ 88030: li r3, 0 881 blr 882 8832: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 884 add r8,r4,r0 885 add r7,r3,r0 8863: lwzu r0,-4(r8) 887 stwu r0,-4(r7) 888 bdnz 3b 889 890/* 891 * Now flush the cache: note that we must start from a cache aligned 892 * address. Otherwise we might miss one cache line. 893 */ 8944: cmpwi r6,0 895 add r5,r3,r5 896 beq 7f /* Always flush prefetch queue in any case */ 897 subi r0,r6,1 898 andc r3,r3,r0 899 mr r4,r3 9005: dcbst 0,r4 901 add r4,r4,r6 902 cmplw r4,r5 903 blt 5b 904 sync /* Wait for all dcbst to complete on bus */ 905 mr r4,r3 9066: icbi 0,r4 907 add r4,r4,r6 908 cmplw r4,r5 909 blt 6b 9107: sync /* Wait for all icbi to complete on bus */ 911 isync 912 913/* 914 * We are done. Do not return, instead branch to second part of board 915 * initialization, now running from RAM. 916 */ 917 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 918 mtlr r0 919 blr 920 921in_ram: 922 923 /* 924 * Relocation Function, r12 point to got2+0x8000 925 * 926 * Adjust got2 pointers, no need to check for 0, this code 927 * already puts a few entries in the table. 928 */ 929 li r0,__got2_entries@sectoff@l 930 la r3,GOT(_GOT2_TABLE_) 931 lwz r11,GOT(_GOT2_TABLE_) 932 mtctr r0 933 sub r11,r3,r11 934 addi r3,r3,-4 9351: lwzu r0,4(r3) 936 cmpwi r0,0 937 beq- 2f 938 add r0,r0,r11 939 stw r0,0(r3) 9402: bdnz 1b 941 942#ifndef CONFIG_NAND_SPL 943 /* 944 * Now adjust the fixups and the pointers to the fixups 945 * in case we need to move ourselves again. 946 */ 947 li r0,__fixup_entries@sectoff@l 948 lwz r3,GOT(_FIXUP_TABLE_) 949 cmpwi r0,0 950 mtctr r0 951 addi r3,r3,-4 952 beq 4f 9533: lwzu r4,4(r3) 954 lwzux r0,r4,r11 955 cmpwi r0,0 956 add r0,r0,r11 957 stw r10,0(r3) 958 beq- 5f 959 stw r0,0(r4) 9605: bdnz 3b 9614: 962#endif 963 964clear_bss: 965 /* 966 * Now clear BSS segment 967 */ 968 lwz r3,GOT(__bss_start) 969#if defined(CONFIG_HYMOD) 970 /* 971 * For HYMOD - the environment is the very last item in flash. 972 * The real .bss stops just before environment starts, so only 973 * clear up to that point. 974 * 975 * taken from mods for FADS board 976 */ 977 lwz r4,GOT(environment) 978#else 979 lwz r4,GOT(_end) 980#endif 981 982 cmplw 0, r3, r4 983 beq 6f 984 985 li r0, 0 9865: 987 stw r0, 0(r3) 988 addi r3, r3, 4 989 cmplw 0, r3, r4 990 bne 5b 9916: 992 993 mr r3, r9 /* Global Data pointer */ 994 mr r4, r10 /* Destination Address */ 995 bl board_init_r 996 997#ifndef CONFIG_NAND_SPL 998 /* 999 * Copy exception vector code to low memory 1000 * 1001 * r3: dest_addr 1002 * r7: source address, r8: end address, r9: target address 1003 */ 1004 .globl trap_init 1005trap_init: 1006 mflr r4 /* save link register */ 1007 GET_GOT 1008 lwz r7, GOT(_start) 1009 lwz r8, GOT(_end_of_vectors) 1010 1011 li r9, 0x100 /* reset vector always at 0x100 */ 1012 1013 cmplw 0, r7, r8 1014 bgelr /* return if r7>=r8 - just in case */ 10151: 1016 lwz r0, 0(r7) 1017 stw r0, 0(r9) 1018 addi r7, r7, 4 1019 addi r9, r9, 4 1020 cmplw 0, r7, r8 1021 bne 1b 1022 1023 /* 1024 * relocate `hdlr' and `int_return' entries 1025 */ 1026 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1027 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10282: 1029 bl trap_reloc 1030 addi r7, r7, 0x100 /* next exception vector */ 1031 cmplw 0, r7, r8 1032 blt 2b 1033 1034 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1035 bl trap_reloc 1036 1037 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1038 bl trap_reloc 1039 1040 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1041 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10423: 1043 bl trap_reloc 1044 addi r7, r7, 0x100 /* next exception vector */ 1045 cmplw 0, r7, r8 1046 blt 3b 1047 1048 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1049 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10504: 1051 bl trap_reloc 1052 addi r7, r7, 0x100 /* next exception vector */ 1053 cmplw 0, r7, r8 1054 blt 4b 1055 1056 mfmsr r3 /* now that the vectors have */ 1057 lis r7, MSR_IP@h /* relocated into low memory */ 1058 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1059 andc r3, r3, r7 /* (if it was on) */ 1060 SYNC /* Some chip revs need this... */ 1061 mtmsr r3 1062 SYNC 1063 1064 mtlr r4 /* restore link register */ 1065 blr 1066 1067#endif /* !CONFIG_NAND_SPL */ 1068 1069#ifdef CONFIG_SYS_INIT_RAM_LOCK 1070lock_ram_in_cache: 1071 /* Allocate Initial RAM in data cache. 1072 */ 1073 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1074 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1075 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 1076 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1077 mtctr r4 10781: 1079 dcbz r0, r3 1080 addi r3, r3, 32 1081 bdnz 1b 1082 1083 /* Lock the data cache */ 1084 mfspr r0, HID0 1085 ori r0, r0, HID0_DLOCK 1086 sync 1087 mtspr HID0, r0 1088 sync 1089 blr 1090 1091#ifndef CONFIG_NAND_SPL 1092.globl unlock_ram_in_cache 1093unlock_ram_in_cache: 1094 /* invalidate the INIT_RAM section */ 1095 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1096 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1097 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 1098 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1099 mtctr r4 11001: icbi r0, r3 1101 dcbi r0, r3 1102 addi r3, r3, 32 1103 bdnz 1b 1104 sync /* Wait for all icbi to complete on bus */ 1105 isync 1106 1107 /* Unlock the data cache and invalidate it */ 1108 mfspr r3, HID0 1109 li r5, HID0_DLOCK|HID0_DCFI 1110 andc r3, r3, r5 /* no invalidate, unlock */ 1111 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1112 sync 1113 mtspr HID0, r5 /* invalidate, unlock */ 1114 sync 1115 mtspr HID0, r3 /* no invalidate, unlock */ 1116 blr 1117#endif /* !CONFIG_NAND_SPL */ 1118#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1119 1120#ifdef CONFIG_SYS_FLASHBOOT 1121map_flash_by_law1: 1122 /* When booting from ROM (Flash or EPROM), clear the */ 1123 /* Address Mask in OR0 so ROM appears everywhere */ 1124 /*----------------------------------------------------*/ 1125 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1126 lwz r4, OR0@l(r3) 1127 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1128 and r4, r4, r5 1129 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1130 1131 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1132 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1133 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1134 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1135 * 0xFF800. From the hard resetting to here, the processor fetched and 1136 * executed the instructions one by one. There is not absolutely 1137 * jumping happened. Laterly, the u-boot code has to do an absolutely 1138 * jumping to tell the CPU instruction fetching component what the 1139 * u-boot TEXT base address is. Because the TEXT base resides in the 1140 * boot ROM memory space, to garantee the code can run smoothly after 1141 * that jumping, we must map in the entire boot ROM by Local Access 1142 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1143 * address for boot ROM, such as 0xFE000000. In this case, the default 1144 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1145 * need another window to map in it. 1146 */ 1147 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1148 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1149 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1150 1151 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1152 lis r4, (0x80000012)@h 1153 ori r4, r4, (0x80000012)@l 1154 li r5, CONFIG_SYS_FLASH_SIZE 11551: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1156 addi r4, r4, 1 1157 bne 1b 1158 1159 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1160 blr 1161 1162 /* Though all the LBIU Local Access Windows and LBC Banks will be 1163 * initialized in the C code, we'd better configure boot ROM's 1164 * window 0 and bank 0 correctly at here. 1165 */ 1166remap_flash_by_law0: 1167 /* Initialize the BR0 with the boot ROM starting address. */ 1168 lwz r4, BR0(r3) 1169 li r5, 0x7FFF 1170 and r4, r4, r5 1171 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1172 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1173 or r5, r5, r4 1174 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1175 1176 lwz r4, OR0(r3) 1177 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1178 or r4, r4, r5 1179 stw r4, OR0(r3) 1180 1181 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1182 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1183 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1184 1185 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1186 lis r4, (0x80000012)@h 1187 ori r4, r4, (0x80000012)@l 1188 li r5, CONFIG_SYS_FLASH_SIZE 11891: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1190 addi r4, r4, 1 1191 bne 1b 1192 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1193 1194 1195 xor r4, r4, r4 1196 stw r4, LBLAWBAR1(r3) 1197 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1198 blr 1199#endif /* CONFIG_SYS_FLASHBOOT */ 1200