1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 28 */ 29 30#include <asm-offsets.h> 31#include <config.h> 32#include <mpc83xx.h> 33#ifndef CONFIG_IDENT_STRING 34#define CONFIG_IDENT_STRING "MPC83XX" 35#endif 36#include <version.h> 37 38#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 39#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 40 41#include <ppc_asm.tmpl> 42#include <ppc_defs.h> 43 44#include <asm/cache.h> 45#include <asm/mmu.h> 46#include <asm/u-boot.h> 47 48/* We don't want the MMU yet. 49 */ 50#undef MSR_KERNEL 51 52/* 53 * Floating Point enable, Machine Check and Recoverable Interr. 54 */ 55#ifdef DEBUG 56#define MSR_KERNEL (MSR_FP|MSR_RI) 57#else 58#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 59#endif 60 61#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) 62#define CONFIG_SYS_FLASHBOOT 63#endif 64 65/* 66 * Set up GOT: Global Offset Table 67 * 68 * Use r12 to access the GOT 69 */ 70 START_GOT 71 GOT_ENTRY(_GOT2_TABLE_) 72 GOT_ENTRY(__bss_start) 73 GOT_ENTRY(__bss_end__) 74 75#ifndef CONFIG_NAND_SPL 76 GOT_ENTRY(_FIXUP_TABLE_) 77 GOT_ENTRY(_start) 78 GOT_ENTRY(_start_of_vectors) 79 GOT_ENTRY(_end_of_vectors) 80 GOT_ENTRY(transfer_to_handler) 81#endif 82 END_GOT 83 84/* 85 * The Hard Reset Configuration Word (HRCW) table is in the first 64 86 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 87 * times so the processor can fetch it out of flash whether the flash 88 * is 8, 16, 32, or 64 bits wide (hardware trickery). 89 */ 90 .text 91#define _HRCW_TABLE_ENTRY(w) \ 92 .fill 8,1,(((w)>>24)&0xff); \ 93 .fill 8,1,(((w)>>16)&0xff); \ 94 .fill 8,1,(((w)>> 8)&0xff); \ 95 .fill 8,1,(((w) )&0xff) 96 97 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 98 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 99 100/* 101 * Magic number and version string - put it after the HRCW since it 102 * cannot be first in flash like it is in many other processors. 103 */ 104 .long 0x27051956 /* U-Boot Magic Number */ 105 106 .globl version_string 107version_string: 108 .ascii U_BOOT_VERSION_STRING, "\0" 109 110 .align 2 111 112 .globl enable_addr_trans 113enable_addr_trans: 114 /* enable address translation */ 115 mfmsr r5 116 ori r5, r5, (MSR_IR | MSR_DR) 117 mtmsr r5 118 isync 119 blr 120 121 .globl disable_addr_trans 122disable_addr_trans: 123 /* disable address translation */ 124 mflr r4 125 mfmsr r3 126 andi. r0, r3, (MSR_IR | MSR_DR) 127 beqlr 128 andc r3, r3, r0 129 mtspr SRR0, r4 130 mtspr SRR1, r3 131 rfi 132 133 .globl get_pvr 134get_pvr: 135 mfspr r3, PVR 136 blr 137 138 .globl ppcDWstore 139ppcDWstore: 140 lfd 1, 0(r4) 141 stfd 1, 0(r3) 142 blr 143 144 .globl ppcDWload 145ppcDWload: 146 lfd 1, 0(r3) 147 stfd 1, 0(r4) 148 blr 149 150#ifndef CONFIG_DEFAULT_IMMR 151#error CONFIG_DEFAULT_IMMR must be defined 152#endif /* CONFIG_SYS_DEFAULT_IMMR */ 153#ifndef CONFIG_SYS_IMMR 154#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 155#endif /* CONFIG_SYS_IMMR */ 156 157/* 158 * After configuration, a system reset exception is executed using the 159 * vector at offset 0x100 relative to the base set by MSR[IP]. If 160 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 161 * base address is 0xfff00000. In the case of a Power On Reset or Hard 162 * Reset, the value of MSR[IP] is determined by the CIP field in the 163 * HRCW. 164 * 165 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 166 * This determines the location of the boot ROM (flash or EPROM) in the 167 * processor's address space at boot time. As long as the HRCW is set up 168 * so that we eventually end up executing the code below when the 169 * processor executes the reset exception, the actual values used should 170 * not matter. 171 * 172 * Once we have got here, the address mask in OR0 is cleared so that the 173 * bottom 32K of the boot ROM is effectively repeated all throughout the 174 * processor's address space, after which we can jump to the absolute 175 * address at which the boot ROM was linked at compile time, and proceed 176 * to initialise the memory controller without worrying if the rug will 177 * be pulled out from under us, so to speak (it will be fine as long as 178 * we configure BR0 with the same boot ROM link address). 179 */ 180 . = EXC_OFF_SYS_RESET 181 182 .globl _start 183_start: /* time t 0 */ 184 lis r4, CONFIG_DEFAULT_IMMR@h 185 nop 186 187 mfmsr r5 /* save msr contents */ 188 189 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 190 bl 1f 1911: mflr r7 192 193 lis r3, CONFIG_SYS_IMMR@h 194 ori r3, r3, CONFIG_SYS_IMMR@l 195 196 lwz r6, IMMRBAR(r4) 197 isync 198 199 stw r3, IMMRBAR(r4) 200 lwz r6, 0(r7) /* Arbitrary external load */ 201 isync 202 203 lwz r6, IMMRBAR(r3) 204 isync 205 206 /* Initialise the E300 processor core */ 207 /*------------------------------------------*/ 208 209#ifdef CONFIG_NAND_SPL 210 /* The FCM begins execution after only the first page 211 * is loaded. Wait for the rest before branching 212 * to another flash page. 213 */ 2141: lwz r6, 0x50b0(r3) 215 andi. r6, r6, 1 216 beq 1b 217#endif 218 219 bl init_e300_core 220 221#ifdef CONFIG_SYS_FLASHBOOT 222 223 /* Inflate flash location so it appears everywhere, calculate */ 224 /* the absolute address in final location of the FLASH, jump */ 225 /* there and deflate the flash size back to minimal size */ 226 /*------------------------------------------------------------*/ 227 bl map_flash_by_law1 228 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 229 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 230 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 231 mtlr r5 232 blr 233in_flash: 234#if 1 /* Remapping flash with LAW0. */ 235 bl remap_flash_by_law0 236#endif 237#endif /* CONFIG_SYS_FLASHBOOT */ 238 239 /* setup the bats */ 240 bl setup_bats 241 sync 242 243 /* 244 * Cache must be enabled here for stack-in-cache trick. 245 * This means we need to enable the BATS. 246 * This means: 247 * 1) for the EVB, original gt regs need to be mapped 248 * 2) need to have an IBAT for the 0xf region, 249 * we are running there! 250 * Cache should be turned on after BATs, since by default 251 * everything is write-through. 252 * The init-mem BAT can be reused after reloc. The old 253 * gt-regs BAT can be reused after board_init_f calls 254 * board_early_init_f (EVB only). 255 */ 256 /* enable address translation */ 257 bl enable_addr_trans 258 sync 259 260 /* enable the data cache */ 261 bl dcache_enable 262 sync 263#ifdef CONFIG_SYS_INIT_RAM_LOCK 264 bl lock_ram_in_cache 265 sync 266#endif 267 268 /* set up the stack pointer in our newly created 269 * cache-ram (r1) */ 270 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 271 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 272 273 li r0, 0 /* Make room for stack frame header and */ 274 stwu r0, -4(r1) /* clear final stack frame so that */ 275 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 276 277 278 /* let the C-code set up the rest */ 279 /* */ 280 /* Be careful to keep code relocatable & stack humble */ 281 /*------------------------------------------------------*/ 282 283 GET_GOT /* initialize GOT access */ 284 285 /* r3: IMMR */ 286 lis r3, CONFIG_SYS_IMMR@h 287 /* run low-level CPU init code (in Flash)*/ 288 bl cpu_init_f 289 290 /* run 1st part of board init code (in Flash)*/ 291 bl board_init_f 292 293 /* NOTREACHED - board_init_f() does not return */ 294 295#ifndef CONFIG_NAND_SPL 296/* 297 * Vector Table 298 */ 299 300 .globl _start_of_vectors 301_start_of_vectors: 302 303/* Machine check */ 304 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 305 306/* Data Storage exception. */ 307 STD_EXCEPTION(0x300, DataStorage, UnknownException) 308 309/* Instruction Storage exception. */ 310 STD_EXCEPTION(0x400, InstStorage, UnknownException) 311 312/* External Interrupt exception. */ 313#ifndef FIXME 314 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 315#endif 316 317/* Alignment exception. */ 318 . = 0x600 319Alignment: 320 EXCEPTION_PROLOG(SRR0, SRR1) 321 mfspr r4,DAR 322 stw r4,_DAR(r21) 323 mfspr r5,DSISR 324 stw r5,_DSISR(r21) 325 addi r3,r1,STACK_FRAME_OVERHEAD 326 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 327 328/* Program check exception */ 329 . = 0x700 330ProgramCheck: 331 EXCEPTION_PROLOG(SRR0, SRR1) 332 addi r3,r1,STACK_FRAME_OVERHEAD 333 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 334 MSR_KERNEL, COPY_EE) 335 336 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 337 338 /* I guess we could implement decrementer, and may have 339 * to someday for timekeeping. 340 */ 341 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 342 343 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 344 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 345 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 346 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 347 348 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 349 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 350 351 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 352 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 353 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 354#ifdef DEBUG 355 . = 0x1300 356 /* 357 * This exception occurs when the program counter matches the 358 * Instruction Address Breakpoint Register (IABR). 359 * 360 * I want the cpu to halt if this occurs so I can hunt around 361 * with the debugger and look at things. 362 * 363 * When DEBUG is defined, both machine check enable (in the MSR) 364 * and checkstop reset enable (in the reset mode register) are 365 * turned off and so a checkstop condition will result in the cpu 366 * halting. 367 * 368 * I force the cpu into a checkstop condition by putting an illegal 369 * instruction here (at least this is the theory). 370 * 371 * well - that didnt work, so just do an infinite loop! 372 */ 3731: b 1b 374#else 375 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 376#endif 377 STD_EXCEPTION(0x1400, SMI, UnknownException) 378 379 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 380 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 381 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 382 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 383 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 384 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 385 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 386 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 387 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 388 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 389 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 390 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 391 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 392 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 393 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 394 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 395 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 396 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 397 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 398 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 399 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 400 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 401 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 402 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 403 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 404 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 405 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 406 407 408 .globl _end_of_vectors 409_end_of_vectors: 410 411 . = 0x3000 412 413/* 414 * This code finishes saving the registers to the exception frame 415 * and jumps to the appropriate handler for the exception. 416 * Register r21 is pointer into trap frame, r1 has new stack pointer. 417 */ 418 .globl transfer_to_handler 419transfer_to_handler: 420 stw r22,_NIP(r21) 421 lis r22,MSR_POW@h 422 andc r23,r23,r22 423 stw r23,_MSR(r21) 424 SAVE_GPR(7, r21) 425 SAVE_4GPRS(8, r21) 426 SAVE_8GPRS(12, r21) 427 SAVE_8GPRS(24, r21) 428 mflr r23 429 andi. r24,r23,0x3f00 /* get vector offset */ 430 stw r24,TRAP(r21) 431 li r22,0 432 stw r22,RESULT(r21) 433 lwz r24,0(r23) /* virtual address of handler */ 434 lwz r23,4(r23) /* where to go when done */ 435 mtspr SRR0,r24 436 mtspr SRR1,r20 437 mtlr r23 438 SYNC 439 rfi /* jump to handler, enable MMU */ 440 441int_return: 442 mfmsr r28 /* Disable interrupts */ 443 li r4,0 444 ori r4,r4,MSR_EE 445 andc r28,r28,r4 446 SYNC /* Some chip revs need this... */ 447 mtmsr r28 448 SYNC 449 lwz r2,_CTR(r1) 450 lwz r0,_LINK(r1) 451 mtctr r2 452 mtlr r0 453 lwz r2,_XER(r1) 454 lwz r0,_CCR(r1) 455 mtspr XER,r2 456 mtcrf 0xFF,r0 457 REST_10GPRS(3, r1) 458 REST_10GPRS(13, r1) 459 REST_8GPRS(23, r1) 460 REST_GPR(31, r1) 461 lwz r2,_NIP(r1) /* Restore environment */ 462 lwz r0,_MSR(r1) 463 mtspr SRR0,r2 464 mtspr SRR1,r0 465 lwz r0,GPR0(r1) 466 lwz r2,GPR2(r1) 467 lwz r1,GPR1(r1) 468 SYNC 469 rfi 470#endif /* !CONFIG_NAND_SPL */ 471 472/* 473 * This code initialises the E300 processor core 474 * (conforms to PowerPC 603e spec) 475 * Note: expects original MSR contents to be in r5. 476 */ 477 .globl init_e300_core 478init_e300_core: /* time t 10 */ 479 /* Initialize machine status; enable machine check interrupt */ 480 /*-----------------------------------------------------------*/ 481 482 li r3, MSR_KERNEL /* Set ME and RI flags */ 483 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 484#ifdef DEBUG 485 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 486#endif 487 SYNC /* Some chip revs need this... */ 488 mtmsr r3 489 SYNC 490 mtspr SRR1, r3 /* Make SRR1 match MSR */ 491 492 493 lis r3, CONFIG_SYS_IMMR@h 494#if defined(CONFIG_WATCHDOG) 495 /* Initialise the Watchdog values and reset it (if req) */ 496 /*------------------------------------------------------*/ 497 lis r4, CONFIG_SYS_WATCHDOG_VALUE 498 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 499 stw r4, SWCRR(r3) 500 501 /* and reset it */ 502 503 li r4, 0x556C 504 sth r4, SWSRR@l(r3) 505 li r4, -0x55C7 506 sth r4, SWSRR@l(r3) 507#else 508 /* Disable Watchdog */ 509 /*-------------------*/ 510 lwz r4, SWCRR(r3) 511 /* Check to see if its enabled for disabling 512 once disabled by SW you can't re-enable */ 513 andi. r4, r4, 0x4 514 beq 1f 515 xor r4, r4, r4 516 stw r4, SWCRR(r3) 5171: 518#endif /* CONFIG_WATCHDOG */ 519 520#if defined(CONFIG_MASK_AER_AO) 521 /* Write the Arbiter Event Enable to mask Address Only traps. */ 522 /* This prevents the dcbz instruction from being trapped when */ 523 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 524 /* COHERENCY bit is set in the WIMG bits, which is often */ 525 /* needed for PCI operation. */ 526 lwz r4, 0x0808(r3) 527 rlwinm r0, r4, 0, ~AER_AO 528 stw r0, 0x0808(r3) 529#endif /* CONFIG_MASK_AER_AO */ 530 531 /* Initialize the Hardware Implementation-dependent Registers */ 532 /* HID0 also contains cache control */ 533 /* - force invalidation of data and instruction caches */ 534 /*------------------------------------------------------*/ 535 536 lis r3, CONFIG_SYS_HID0_INIT@h 537 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 538 SYNC 539 mtspr HID0, r3 540 541 lis r3, CONFIG_SYS_HID0_FINAL@h 542 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 543 SYNC 544 mtspr HID0, r3 545 546 lis r3, CONFIG_SYS_HID2@h 547 ori r3, r3, CONFIG_SYS_HID2@l 548 SYNC 549 mtspr HID2, r3 550 551 /* Done! */ 552 /*------------------------------*/ 553 blr 554 555 /* setup_bats - set them up to some initial state */ 556 .globl setup_bats 557setup_bats: 558 addis r0, r0, 0x0000 559 560 /* IBAT 0 */ 561 addis r4, r0, CONFIG_SYS_IBAT0L@h 562 ori r4, r4, CONFIG_SYS_IBAT0L@l 563 addis r3, r0, CONFIG_SYS_IBAT0U@h 564 ori r3, r3, CONFIG_SYS_IBAT0U@l 565 mtspr IBAT0L, r4 566 mtspr IBAT0U, r3 567 568 /* DBAT 0 */ 569 addis r4, r0, CONFIG_SYS_DBAT0L@h 570 ori r4, r4, CONFIG_SYS_DBAT0L@l 571 addis r3, r0, CONFIG_SYS_DBAT0U@h 572 ori r3, r3, CONFIG_SYS_DBAT0U@l 573 mtspr DBAT0L, r4 574 mtspr DBAT0U, r3 575 576 /* IBAT 1 */ 577 addis r4, r0, CONFIG_SYS_IBAT1L@h 578 ori r4, r4, CONFIG_SYS_IBAT1L@l 579 addis r3, r0, CONFIG_SYS_IBAT1U@h 580 ori r3, r3, CONFIG_SYS_IBAT1U@l 581 mtspr IBAT1L, r4 582 mtspr IBAT1U, r3 583 584 /* DBAT 1 */ 585 addis r4, r0, CONFIG_SYS_DBAT1L@h 586 ori r4, r4, CONFIG_SYS_DBAT1L@l 587 addis r3, r0, CONFIG_SYS_DBAT1U@h 588 ori r3, r3, CONFIG_SYS_DBAT1U@l 589 mtspr DBAT1L, r4 590 mtspr DBAT1U, r3 591 592 /* IBAT 2 */ 593 addis r4, r0, CONFIG_SYS_IBAT2L@h 594 ori r4, r4, CONFIG_SYS_IBAT2L@l 595 addis r3, r0, CONFIG_SYS_IBAT2U@h 596 ori r3, r3, CONFIG_SYS_IBAT2U@l 597 mtspr IBAT2L, r4 598 mtspr IBAT2U, r3 599 600 /* DBAT 2 */ 601 addis r4, r0, CONFIG_SYS_DBAT2L@h 602 ori r4, r4, CONFIG_SYS_DBAT2L@l 603 addis r3, r0, CONFIG_SYS_DBAT2U@h 604 ori r3, r3, CONFIG_SYS_DBAT2U@l 605 mtspr DBAT2L, r4 606 mtspr DBAT2U, r3 607 608 /* IBAT 3 */ 609 addis r4, r0, CONFIG_SYS_IBAT3L@h 610 ori r4, r4, CONFIG_SYS_IBAT3L@l 611 addis r3, r0, CONFIG_SYS_IBAT3U@h 612 ori r3, r3, CONFIG_SYS_IBAT3U@l 613 mtspr IBAT3L, r4 614 mtspr IBAT3U, r3 615 616 /* DBAT 3 */ 617 addis r4, r0, CONFIG_SYS_DBAT3L@h 618 ori r4, r4, CONFIG_SYS_DBAT3L@l 619 addis r3, r0, CONFIG_SYS_DBAT3U@h 620 ori r3, r3, CONFIG_SYS_DBAT3U@l 621 mtspr DBAT3L, r4 622 mtspr DBAT3U, r3 623 624#ifdef CONFIG_HIGH_BATS 625 /* IBAT 4 */ 626 addis r4, r0, CONFIG_SYS_IBAT4L@h 627 ori r4, r4, CONFIG_SYS_IBAT4L@l 628 addis r3, r0, CONFIG_SYS_IBAT4U@h 629 ori r3, r3, CONFIG_SYS_IBAT4U@l 630 mtspr IBAT4L, r4 631 mtspr IBAT4U, r3 632 633 /* DBAT 4 */ 634 addis r4, r0, CONFIG_SYS_DBAT4L@h 635 ori r4, r4, CONFIG_SYS_DBAT4L@l 636 addis r3, r0, CONFIG_SYS_DBAT4U@h 637 ori r3, r3, CONFIG_SYS_DBAT4U@l 638 mtspr DBAT4L, r4 639 mtspr DBAT4U, r3 640 641 /* IBAT 5 */ 642 addis r4, r0, CONFIG_SYS_IBAT5L@h 643 ori r4, r4, CONFIG_SYS_IBAT5L@l 644 addis r3, r0, CONFIG_SYS_IBAT5U@h 645 ori r3, r3, CONFIG_SYS_IBAT5U@l 646 mtspr IBAT5L, r4 647 mtspr IBAT5U, r3 648 649 /* DBAT 5 */ 650 addis r4, r0, CONFIG_SYS_DBAT5L@h 651 ori r4, r4, CONFIG_SYS_DBAT5L@l 652 addis r3, r0, CONFIG_SYS_DBAT5U@h 653 ori r3, r3, CONFIG_SYS_DBAT5U@l 654 mtspr DBAT5L, r4 655 mtspr DBAT5U, r3 656 657 /* IBAT 6 */ 658 addis r4, r0, CONFIG_SYS_IBAT6L@h 659 ori r4, r4, CONFIG_SYS_IBAT6L@l 660 addis r3, r0, CONFIG_SYS_IBAT6U@h 661 ori r3, r3, CONFIG_SYS_IBAT6U@l 662 mtspr IBAT6L, r4 663 mtspr IBAT6U, r3 664 665 /* DBAT 6 */ 666 addis r4, r0, CONFIG_SYS_DBAT6L@h 667 ori r4, r4, CONFIG_SYS_DBAT6L@l 668 addis r3, r0, CONFIG_SYS_DBAT6U@h 669 ori r3, r3, CONFIG_SYS_DBAT6U@l 670 mtspr DBAT6L, r4 671 mtspr DBAT6U, r3 672 673 /* IBAT 7 */ 674 addis r4, r0, CONFIG_SYS_IBAT7L@h 675 ori r4, r4, CONFIG_SYS_IBAT7L@l 676 addis r3, r0, CONFIG_SYS_IBAT7U@h 677 ori r3, r3, CONFIG_SYS_IBAT7U@l 678 mtspr IBAT7L, r4 679 mtspr IBAT7U, r3 680 681 /* DBAT 7 */ 682 addis r4, r0, CONFIG_SYS_DBAT7L@h 683 ori r4, r4, CONFIG_SYS_DBAT7L@l 684 addis r3, r0, CONFIG_SYS_DBAT7U@h 685 ori r3, r3, CONFIG_SYS_DBAT7U@l 686 mtspr DBAT7L, r4 687 mtspr DBAT7U, r3 688#endif 689 690 isync 691 692 /* invalidate all tlb's 693 * 694 * From the 603e User Manual: "The 603e provides the ability to 695 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 696 * instruction invalidates the TLB entry indexed by the EA, and 697 * operates on both the instruction and data TLBs simultaneously 698 * invalidating four TLB entries (both sets in each TLB). The 699 * index corresponds to bits 15-19 of the EA. To invalidate all 700 * entries within both TLBs, 32 tlbie instructions should be 701 * issued, incrementing this field by one each time." 702 * 703 * "Note that the tlbia instruction is not implemented on the 704 * 603e." 705 * 706 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 707 * incrementing by 0x1000 each time. The code below is sort of 708 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 709 * 710 */ 711 lis r3, 0 712 lis r5, 2 713 7141: 715 tlbie r3 716 addi r3, r3, 0x1000 717 cmp 0, 0, r3, r5 718 blt 1b 719 720 blr 721 722/* Cache functions. 723 * 724 * Note: requires that all cache bits in 725 * HID0 are in the low half word. 726 */ 727#ifndef CONFIG_NAND_SPL 728 .globl icache_enable 729icache_enable: 730 mfspr r3, HID0 731 ori r3, r3, HID0_ICE 732 li r4, HID0_ICFI|HID0_ILOCK 733 andc r3, r3, r4 734 ori r4, r3, HID0_ICFI 735 isync 736 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 737 isync 738 mtspr HID0, r3 /* clears invalidate */ 739 blr 740 741 .globl icache_disable 742icache_disable: 743 mfspr r3, HID0 744 lis r4, 0 745 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 746 andc r3, r3, r4 747 isync 748 mtspr HID0, r3 /* clears invalidate, enable and lock */ 749 blr 750 751 .globl icache_status 752icache_status: 753 mfspr r3, HID0 754 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 755 blr 756#endif /* !CONFIG_NAND_SPL */ 757 758 .globl dcache_enable 759dcache_enable: 760 mfspr r3, HID0 761 li r5, HID0_DCFI|HID0_DLOCK 762 andc r3, r3, r5 763 ori r3, r3, HID0_DCE 764 sync 765 mtspr HID0, r3 /* enable, no invalidate */ 766 blr 767 768 .globl dcache_disable 769dcache_disable: 770 mflr r4 771 bl flush_dcache /* uses r3 and r5 */ 772 mfspr r3, HID0 773 li r5, HID0_DCE|HID0_DLOCK 774 andc r3, r3, r5 775 ori r5, r3, HID0_DCFI 776 sync 777 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 778 sync 779 mtspr HID0, r3 /* clears invalidate */ 780 mtlr r4 781 blr 782 783 .globl dcache_status 784dcache_status: 785 mfspr r3, HID0 786 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 787 blr 788 789 .globl flush_dcache 790flush_dcache: 791 lis r3, 0 792 lis r5, CONFIG_SYS_CACHELINE_SIZE 7931: cmp 0, 1, r3, r5 794 bge 2f 795 lwz r5, 0(r3) 796 lis r5, CONFIG_SYS_CACHELINE_SIZE 797 addi r3, r3, 0x4 798 b 1b 7992: blr 800 801/*-------------------------------------------------------------------*/ 802 803/* 804 * void relocate_code (addr_sp, gd, addr_moni) 805 * 806 * This "function" does not return, instead it continues in RAM 807 * after relocating the monitor code. 808 * 809 * r3 = dest 810 * r4 = src 811 * r5 = length in bytes 812 * r6 = cachelinesize 813 */ 814 .globl relocate_code 815relocate_code: 816 mr r1, r3 /* Set new stack pointer */ 817 mr r9, r4 /* Save copy of Global Data pointer */ 818 mr r10, r5 /* Save copy of Destination Address */ 819 820 GET_GOT 821 mr r3, r5 /* Destination Address */ 822 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 823 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 824 lwz r5, GOT(__bss_start) 825 sub r5, r5, r4 826 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 827 828 /* 829 * Fix GOT pointer: 830 * 831 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 832 * + Destination Address 833 * 834 * Offset: 835 */ 836 sub r15, r10, r4 837 838 /* First our own GOT */ 839 add r12, r12, r15 840 /* then the one used by the C code */ 841 add r30, r30, r15 842 843 /* 844 * Now relocate code 845 */ 846 847 cmplw cr1,r3,r4 848 addi r0,r5,3 849 srwi. r0,r0,2 850 beq cr1,4f /* In place copy is not necessary */ 851 beq 7f /* Protect against 0 count */ 852 mtctr r0 853 bge cr1,2f 854 la r8,-4(r4) 855 la r7,-4(r3) 856 857 /* copy */ 8581: lwzu r0,4(r8) 859 stwu r0,4(r7) 860 bdnz 1b 861 862 addi r0,r5,3 863 srwi. r0,r0,2 864 mtctr r0 865 la r8,-4(r4) 866 la r7,-4(r3) 867 868 /* and compare */ 86920: lwzu r20,4(r8) 870 lwzu r21,4(r7) 871 xor. r22, r20, r21 872 bne 30f 873 bdnz 20b 874 b 4f 875 876 /* compare failed */ 87730: li r3, 0 878 blr 879 8802: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 881 add r8,r4,r0 882 add r7,r3,r0 8833: lwzu r0,-4(r8) 884 stwu r0,-4(r7) 885 bdnz 3b 886 887/* 888 * Now flush the cache: note that we must start from a cache aligned 889 * address. Otherwise we might miss one cache line. 890 */ 8914: cmpwi r6,0 892 add r5,r3,r5 893 beq 7f /* Always flush prefetch queue in any case */ 894 subi r0,r6,1 895 andc r3,r3,r0 896 mr r4,r3 8975: dcbst 0,r4 898 add r4,r4,r6 899 cmplw r4,r5 900 blt 5b 901 sync /* Wait for all dcbst to complete on bus */ 902 mr r4,r3 9036: icbi 0,r4 904 add r4,r4,r6 905 cmplw r4,r5 906 blt 6b 9077: sync /* Wait for all icbi to complete on bus */ 908 isync 909 910/* 911 * We are done. Do not return, instead branch to second part of board 912 * initialization, now running from RAM. 913 */ 914 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 915 mtlr r0 916 blr 917 918in_ram: 919 920 /* 921 * Relocation Function, r12 point to got2+0x8000 922 * 923 * Adjust got2 pointers, no need to check for 0, this code 924 * already puts a few entries in the table. 925 */ 926 li r0,__got2_entries@sectoff@l 927 la r3,GOT(_GOT2_TABLE_) 928 lwz r11,GOT(_GOT2_TABLE_) 929 mtctr r0 930 sub r11,r3,r11 931 addi r3,r3,-4 9321: lwzu r0,4(r3) 933 cmpwi r0,0 934 beq- 2f 935 add r0,r0,r11 936 stw r0,0(r3) 9372: bdnz 1b 938 939#ifndef CONFIG_NAND_SPL 940 /* 941 * Now adjust the fixups and the pointers to the fixups 942 * in case we need to move ourselves again. 943 */ 944 li r0,__fixup_entries@sectoff@l 945 lwz r3,GOT(_FIXUP_TABLE_) 946 cmpwi r0,0 947 mtctr r0 948 addi r3,r3,-4 949 beq 4f 9503: lwzu r4,4(r3) 951 lwzux r0,r4,r11 952 cmpwi r0,0 953 add r0,r0,r11 954 stw r4,0(r3) 955 beq- 5f 956 stw r0,0(r4) 9575: bdnz 3b 9584: 959#endif 960 961clear_bss: 962 /* 963 * Now clear BSS segment 964 */ 965 lwz r3,GOT(__bss_start) 966#if defined(CONFIG_HYMOD) 967 /* 968 * For HYMOD - the environment is the very last item in flash. 969 * The real .bss stops just before environment starts, so only 970 * clear up to that point. 971 * 972 * taken from mods for FADS board 973 */ 974 lwz r4,GOT(environment) 975#else 976 lwz r4,GOT(__bss_end__) 977#endif 978 979 cmplw 0, r3, r4 980 beq 6f 981 982 li r0, 0 9835: 984 stw r0, 0(r3) 985 addi r3, r3, 4 986 cmplw 0, r3, r4 987 bne 5b 9886: 989 990 mr r3, r9 /* Global Data pointer */ 991 mr r4, r10 /* Destination Address */ 992 bl board_init_r 993 994#ifndef CONFIG_NAND_SPL 995 /* 996 * Copy exception vector code to low memory 997 * 998 * r3: dest_addr 999 * r7: source address, r8: end address, r9: target address 1000 */ 1001 .globl trap_init 1002trap_init: 1003 mflr r4 /* save link register */ 1004 GET_GOT 1005 lwz r7, GOT(_start) 1006 lwz r8, GOT(_end_of_vectors) 1007 1008 li r9, 0x100 /* reset vector always at 0x100 */ 1009 1010 cmplw 0, r7, r8 1011 bgelr /* return if r7>=r8 - just in case */ 10121: 1013 lwz r0, 0(r7) 1014 stw r0, 0(r9) 1015 addi r7, r7, 4 1016 addi r9, r9, 4 1017 cmplw 0, r7, r8 1018 bne 1b 1019 1020 /* 1021 * relocate `hdlr' and `int_return' entries 1022 */ 1023 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1024 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10252: 1026 bl trap_reloc 1027 addi r7, r7, 0x100 /* next exception vector */ 1028 cmplw 0, r7, r8 1029 blt 2b 1030 1031 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1032 bl trap_reloc 1033 1034 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1035 bl trap_reloc 1036 1037 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1038 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10393: 1040 bl trap_reloc 1041 addi r7, r7, 0x100 /* next exception vector */ 1042 cmplw 0, r7, r8 1043 blt 3b 1044 1045 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1046 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10474: 1048 bl trap_reloc 1049 addi r7, r7, 0x100 /* next exception vector */ 1050 cmplw 0, r7, r8 1051 blt 4b 1052 1053 mfmsr r3 /* now that the vectors have */ 1054 lis r7, MSR_IP@h /* relocated into low memory */ 1055 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1056 andc r3, r3, r7 /* (if it was on) */ 1057 SYNC /* Some chip revs need this... */ 1058 mtmsr r3 1059 SYNC 1060 1061 mtlr r4 /* restore link register */ 1062 blr 1063 1064#endif /* !CONFIG_NAND_SPL */ 1065 1066#ifdef CONFIG_SYS_INIT_RAM_LOCK 1067lock_ram_in_cache: 1068 /* Allocate Initial RAM in data cache. 1069 */ 1070 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1071 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1072 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1073 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1074 mtctr r4 10751: 1076 dcbz r0, r3 1077 addi r3, r3, 32 1078 bdnz 1b 1079 1080 /* Lock the data cache */ 1081 mfspr r0, HID0 1082 ori r0, r0, HID0_DLOCK 1083 sync 1084 mtspr HID0, r0 1085 sync 1086 blr 1087 1088#ifndef CONFIG_NAND_SPL 1089.globl unlock_ram_in_cache 1090unlock_ram_in_cache: 1091 /* invalidate the INIT_RAM section */ 1092 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1093 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1094 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1095 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1096 mtctr r4 10971: icbi r0, r3 1098 dcbi r0, r3 1099 addi r3, r3, 32 1100 bdnz 1b 1101 sync /* Wait for all icbi to complete on bus */ 1102 isync 1103 1104 /* Unlock the data cache and invalidate it */ 1105 mfspr r3, HID0 1106 li r5, HID0_DLOCK|HID0_DCFI 1107 andc r3, r3, r5 /* no invalidate, unlock */ 1108 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1109 sync 1110 mtspr HID0, r5 /* invalidate, unlock */ 1111 sync 1112 mtspr HID0, r3 /* no invalidate, unlock */ 1113 blr 1114#endif /* !CONFIG_NAND_SPL */ 1115#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1116 1117#ifdef CONFIG_SYS_FLASHBOOT 1118map_flash_by_law1: 1119 /* When booting from ROM (Flash or EPROM), clear the */ 1120 /* Address Mask in OR0 so ROM appears everywhere */ 1121 /*----------------------------------------------------*/ 1122 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1123 lwz r4, OR0@l(r3) 1124 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1125 and r4, r4, r5 1126 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1127 1128 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1129 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1130 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1131 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1132 * 0xFF800. From the hard resetting to here, the processor fetched and 1133 * executed the instructions one by one. There is not absolutely 1134 * jumping happened. Laterly, the u-boot code has to do an absolutely 1135 * jumping to tell the CPU instruction fetching component what the 1136 * u-boot TEXT base address is. Because the TEXT base resides in the 1137 * boot ROM memory space, to garantee the code can run smoothly after 1138 * that jumping, we must map in the entire boot ROM by Local Access 1139 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1140 * address for boot ROM, such as 0xFE000000. In this case, the default 1141 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1142 * need another window to map in it. 1143 */ 1144 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1145 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1146 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1147 1148 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1149 lis r4, (0x80000012)@h 1150 ori r4, r4, (0x80000012)@l 1151 li r5, CONFIG_SYS_FLASH_SIZE 11521: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1153 addi r4, r4, 1 1154 bne 1b 1155 1156 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1157 /* Wait for HW to catch up */ 1158 lwz r4, LBLAWAR1(r3) 1159 twi 0,r4,0 1160 isync 1161 blr 1162 1163 /* Though all the LBIU Local Access Windows and LBC Banks will be 1164 * initialized in the C code, we'd better configure boot ROM's 1165 * window 0 and bank 0 correctly at here. 1166 */ 1167remap_flash_by_law0: 1168 /* Initialize the BR0 with the boot ROM starting address. */ 1169 lwz r4, BR0(r3) 1170 li r5, 0x7FFF 1171 and r4, r4, r5 1172 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1173 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1174 or r5, r5, r4 1175 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1176 1177 lwz r4, OR0(r3) 1178 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1179 or r4, r4, r5 1180 stw r4, OR0(r3) 1181 1182 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1183 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1184 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1185 1186 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1187 lis r4, (0x80000012)@h 1188 ori r4, r4, (0x80000012)@l 1189 li r5, CONFIG_SYS_FLASH_SIZE 11901: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1191 addi r4, r4, 1 1192 bne 1b 1193 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1194 1195 1196 xor r4, r4, r4 1197 stw r4, LBLAWBAR1(r3) 1198 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1199 /* Wait for HW to catch up */ 1200 lwz r4, LBLAWAR1(r3) 1201 twi 0,r4,0 1202 isync 1203 blr 1204#endif /* CONFIG_SYS_FLASHBOOT */ 1205