1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 12 */ 13 14#include <asm-offsets.h> 15#include <config.h> 16#include <mpc83xx.h> 17#ifndef CONFIG_IDENT_STRING 18#define CONFIG_IDENT_STRING "MPC83XX" 19#endif 20#include <version.h> 21 22#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 23 24#include <ppc_asm.tmpl> 25#include <ppc_defs.h> 26 27#include <asm/cache.h> 28#include <asm/mmu.h> 29#include <asm/u-boot.h> 30 31/* We don't want the MMU yet. 32 */ 33#undef MSR_KERNEL 34 35/* 36 * Floating Point enable, Machine Check and Recoverable Interr. 37 */ 38#ifdef DEBUG 39#define MSR_KERNEL (MSR_FP|MSR_RI) 40#else 41#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 42#endif 43 44#if defined(CONFIG_NAND_SPL) || \ 45 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 46#define MINIMAL_SPL 47#endif 48 49#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 50 !defined(CONFIG_SYS_RAMBOOT) 51#define CONFIG_SYS_FLASHBOOT 52#endif 53 54/* 55 * Set up GOT: Global Offset Table 56 * 57 * Use r12 to access the GOT 58 */ 59 START_GOT 60 GOT_ENTRY(_GOT2_TABLE_) 61 GOT_ENTRY(__bss_start) 62 GOT_ENTRY(__bss_end) 63 64#ifndef MINIMAL_SPL 65 GOT_ENTRY(_FIXUP_TABLE_) 66 GOT_ENTRY(_start) 67 GOT_ENTRY(_start_of_vectors) 68 GOT_ENTRY(_end_of_vectors) 69 GOT_ENTRY(transfer_to_handler) 70#endif 71 END_GOT 72 73/* 74 * The Hard Reset Configuration Word (HRCW) table is in the first 64 75 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 76 * times so the processor can fetch it out of flash whether the flash 77 * is 8, 16, 32, or 64 bits wide (hardware trickery). 78 */ 79 .text 80#define _HRCW_TABLE_ENTRY(w) \ 81 .fill 8,1,(((w)>>24)&0xff); \ 82 .fill 8,1,(((w)>>16)&0xff); \ 83 .fill 8,1,(((w)>> 8)&0xff); \ 84 .fill 8,1,(((w) )&0xff) 85 86 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 87 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 88 89/* 90 * Magic number and version string - put it after the HRCW since it 91 * cannot be first in flash like it is in many other processors. 92 */ 93 .long 0x27051956 /* U-Boot Magic Number */ 94 95 .globl version_string 96version_string: 97 .ascii U_BOOT_VERSION_STRING, "\0" 98 99 .align 2 100 101 .globl enable_addr_trans 102enable_addr_trans: 103 /* enable address translation */ 104 mfmsr r5 105 ori r5, r5, (MSR_IR | MSR_DR) 106 mtmsr r5 107 isync 108 blr 109 110 .globl disable_addr_trans 111disable_addr_trans: 112 /* disable address translation */ 113 mflr r4 114 mfmsr r3 115 andi. r0, r3, (MSR_IR | MSR_DR) 116 beqlr 117 andc r3, r3, r0 118 mtspr SRR0, r4 119 mtspr SRR1, r3 120 rfi 121 122 .globl get_svr 123get_svr: 124 mfspr r3, SVR 125 blr 126 127 .globl get_pvr 128get_pvr: 129 mfspr r3, PVR 130 blr 131 132 .globl ppcDWstore 133ppcDWstore: 134 lfd 1, 0(r4) 135 stfd 1, 0(r3) 136 blr 137 138 .globl ppcDWload 139ppcDWload: 140 lfd 1, 0(r3) 141 stfd 1, 0(r4) 142 blr 143 144#ifndef CONFIG_DEFAULT_IMMR 145#error CONFIG_DEFAULT_IMMR must be defined 146#endif /* CONFIG_SYS_DEFAULT_IMMR */ 147#ifndef CONFIG_SYS_IMMR 148#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 149#endif /* CONFIG_SYS_IMMR */ 150 151/* 152 * After configuration, a system reset exception is executed using the 153 * vector at offset 0x100 relative to the base set by MSR[IP]. If 154 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 155 * base address is 0xfff00000. In the case of a Power On Reset or Hard 156 * Reset, the value of MSR[IP] is determined by the CIP field in the 157 * HRCW. 158 * 159 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 160 * This determines the location of the boot ROM (flash or EPROM) in the 161 * processor's address space at boot time. As long as the HRCW is set up 162 * so that we eventually end up executing the code below when the 163 * processor executes the reset exception, the actual values used should 164 * not matter. 165 * 166 * Once we have got here, the address mask in OR0 is cleared so that the 167 * bottom 32K of the boot ROM is effectively repeated all throughout the 168 * processor's address space, after which we can jump to the absolute 169 * address at which the boot ROM was linked at compile time, and proceed 170 * to initialise the memory controller without worrying if the rug will 171 * be pulled out from under us, so to speak (it will be fine as long as 172 * we configure BR0 with the same boot ROM link address). 173 */ 174 . = EXC_OFF_SYS_RESET 175 176 .globl _start 177_start: /* time t 0 */ 178 lis r4, CONFIG_DEFAULT_IMMR@h 179 nop 180 181 mfmsr r5 /* save msr contents */ 182 183 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 184 bl 1f 1851: mflr r7 186 187 lis r3, CONFIG_SYS_IMMR@h 188 ori r3, r3, CONFIG_SYS_IMMR@l 189 190 lwz r6, IMMRBAR(r4) 191 isync 192 193 stw r3, IMMRBAR(r4) 194 lwz r6, 0(r7) /* Arbitrary external load */ 195 isync 196 197 lwz r6, IMMRBAR(r3) 198 isync 199 200 /* Initialise the E300 processor core */ 201 /*------------------------------------------*/ 202 203#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 204 defined(CONFIG_NAND_SPL) 205 /* The FCM begins execution after only the first page 206 * is loaded. Wait for the rest before branching 207 * to another flash page. 208 */ 2091: lwz r6, 0x50b0(r3) 210 andi. r6, r6, 1 211 beq 1b 212#endif 213 214 bl init_e300_core 215 216#ifdef CONFIG_SYS_FLASHBOOT 217 218 /* Inflate flash location so it appears everywhere, calculate */ 219 /* the absolute address in final location of the FLASH, jump */ 220 /* there and deflate the flash size back to minimal size */ 221 /*------------------------------------------------------------*/ 222 bl map_flash_by_law1 223 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 224 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 225 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 226 mtlr r5 227 blr 228in_flash: 229#if 1 /* Remapping flash with LAW0. */ 230 bl remap_flash_by_law0 231#endif 232#endif /* CONFIG_SYS_FLASHBOOT */ 233 234 /* setup the bats */ 235 bl setup_bats 236 sync 237 238 /* 239 * Cache must be enabled here for stack-in-cache trick. 240 * This means we need to enable the BATS. 241 * This means: 242 * 1) for the EVB, original gt regs need to be mapped 243 * 2) need to have an IBAT for the 0xf region, 244 * we are running there! 245 * Cache should be turned on after BATs, since by default 246 * everything is write-through. 247 * The init-mem BAT can be reused after reloc. The old 248 * gt-regs BAT can be reused after board_init_f calls 249 * board_early_init_f (EVB only). 250 */ 251 /* enable address translation */ 252 bl enable_addr_trans 253 sync 254 255 /* enable the data cache */ 256 bl dcache_enable 257 sync 258#ifdef CONFIG_SYS_INIT_RAM_LOCK 259 bl lock_ram_in_cache 260 sync 261#endif 262 263 /* set up the stack pointer in our newly created 264 * cache-ram (r1) */ 265 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 266 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 267 268 li r0, 0 /* Make room for stack frame header and */ 269 stwu r0, -4(r1) /* clear final stack frame so that */ 270 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 271 272 273 /* let the C-code set up the rest */ 274 /* */ 275 /* Be careful to keep code relocatable & stack humble */ 276 /*------------------------------------------------------*/ 277 278 GET_GOT /* initialize GOT access */ 279 280 /* r3: IMMR */ 281 lis r3, CONFIG_SYS_IMMR@h 282 /* run low-level CPU init code (in Flash)*/ 283 bl cpu_init_f 284 285 /* run 1st part of board init code (in Flash)*/ 286 bl board_init_f 287 288 /* NOTREACHED - board_init_f() does not return */ 289 290#ifndef MINIMAL_SPL 291/* 292 * Vector Table 293 */ 294 295 .globl _start_of_vectors 296_start_of_vectors: 297 298/* Machine check */ 299 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 300 301/* Data Storage exception. */ 302 STD_EXCEPTION(0x300, DataStorage, UnknownException) 303 304/* Instruction Storage exception. */ 305 STD_EXCEPTION(0x400, InstStorage, UnknownException) 306 307/* External Interrupt exception. */ 308#ifndef FIXME 309 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 310#endif 311 312/* Alignment exception. */ 313 . = 0x600 314Alignment: 315 EXCEPTION_PROLOG(SRR0, SRR1) 316 mfspr r4,DAR 317 stw r4,_DAR(r21) 318 mfspr r5,DSISR 319 stw r5,_DSISR(r21) 320 addi r3,r1,STACK_FRAME_OVERHEAD 321 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 322 323/* Program check exception */ 324 . = 0x700 325ProgramCheck: 326 EXCEPTION_PROLOG(SRR0, SRR1) 327 addi r3,r1,STACK_FRAME_OVERHEAD 328 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 329 MSR_KERNEL, COPY_EE) 330 331 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 332 333 /* I guess we could implement decrementer, and may have 334 * to someday for timekeeping. 335 */ 336 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 337 338 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 339 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 340 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 341 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 342 343 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 344 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 345 346 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 347 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 348 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 349#ifdef DEBUG 350 . = 0x1300 351 /* 352 * This exception occurs when the program counter matches the 353 * Instruction Address Breakpoint Register (IABR). 354 * 355 * I want the cpu to halt if this occurs so I can hunt around 356 * with the debugger and look at things. 357 * 358 * When DEBUG is defined, both machine check enable (in the MSR) 359 * and checkstop reset enable (in the reset mode register) are 360 * turned off and so a checkstop condition will result in the cpu 361 * halting. 362 * 363 * I force the cpu into a checkstop condition by putting an illegal 364 * instruction here (at least this is the theory). 365 * 366 * well - that didnt work, so just do an infinite loop! 367 */ 3681: b 1b 369#else 370 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 371#endif 372 STD_EXCEPTION(0x1400, SMI, UnknownException) 373 374 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 375 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 376 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 377 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 378 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 379 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 380 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 381 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 382 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 383 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 384 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 385 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 386 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 387 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 388 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 389 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 390 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 391 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 392 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 393 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 394 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 395 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 396 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 397 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 398 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 399 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 400 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 401 402 403 .globl _end_of_vectors 404_end_of_vectors: 405 406 . = 0x3000 407 408/* 409 * This code finishes saving the registers to the exception frame 410 * and jumps to the appropriate handler for the exception. 411 * Register r21 is pointer into trap frame, r1 has new stack pointer. 412 */ 413 .globl transfer_to_handler 414transfer_to_handler: 415 stw r22,_NIP(r21) 416 lis r22,MSR_POW@h 417 andc r23,r23,r22 418 stw r23,_MSR(r21) 419 SAVE_GPR(7, r21) 420 SAVE_4GPRS(8, r21) 421 SAVE_8GPRS(12, r21) 422 SAVE_8GPRS(24, r21) 423 mflr r23 424 andi. r24,r23,0x3f00 /* get vector offset */ 425 stw r24,TRAP(r21) 426 li r22,0 427 stw r22,RESULT(r21) 428 lwz r24,0(r23) /* virtual address of handler */ 429 lwz r23,4(r23) /* where to go when done */ 430 mtspr SRR0,r24 431 mtspr SRR1,r20 432 mtlr r23 433 SYNC 434 rfi /* jump to handler, enable MMU */ 435 436int_return: 437 mfmsr r28 /* Disable interrupts */ 438 li r4,0 439 ori r4,r4,MSR_EE 440 andc r28,r28,r4 441 SYNC /* Some chip revs need this... */ 442 mtmsr r28 443 SYNC 444 lwz r2,_CTR(r1) 445 lwz r0,_LINK(r1) 446 mtctr r2 447 mtlr r0 448 lwz r2,_XER(r1) 449 lwz r0,_CCR(r1) 450 mtspr XER,r2 451 mtcrf 0xFF,r0 452 REST_10GPRS(3, r1) 453 REST_10GPRS(13, r1) 454 REST_8GPRS(23, r1) 455 REST_GPR(31, r1) 456 lwz r2,_NIP(r1) /* Restore environment */ 457 lwz r0,_MSR(r1) 458 mtspr SRR0,r2 459 mtspr SRR1,r0 460 lwz r0,GPR0(r1) 461 lwz r2,GPR2(r1) 462 lwz r1,GPR1(r1) 463 SYNC 464 rfi 465#endif /* !MINIMAL_SPL */ 466 467/* 468 * This code initialises the E300 processor core 469 * (conforms to PowerPC 603e spec) 470 * Note: expects original MSR contents to be in r5. 471 */ 472 .globl init_e300_core 473init_e300_core: /* time t 10 */ 474 /* Initialize machine status; enable machine check interrupt */ 475 /*-----------------------------------------------------------*/ 476 477 li r3, MSR_KERNEL /* Set ME and RI flags */ 478 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 479#ifdef DEBUG 480 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 481#endif 482 SYNC /* Some chip revs need this... */ 483 mtmsr r3 484 SYNC 485 mtspr SRR1, r3 /* Make SRR1 match MSR */ 486 487 488 lis r3, CONFIG_SYS_IMMR@h 489#if defined(CONFIG_WATCHDOG) 490 /* Initialise the Watchdog values and reset it (if req) */ 491 /*------------------------------------------------------*/ 492 lis r4, CONFIG_SYS_WATCHDOG_VALUE 493 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 494 stw r4, SWCRR(r3) 495 496 /* and reset it */ 497 498 li r4, 0x556C 499 sth r4, SWSRR@l(r3) 500 li r4, -0x55C7 501 sth r4, SWSRR@l(r3) 502#else 503 /* Disable Watchdog */ 504 /*-------------------*/ 505 lwz r4, SWCRR(r3) 506 /* Check to see if its enabled for disabling 507 once disabled by SW you can't re-enable */ 508 andi. r4, r4, 0x4 509 beq 1f 510 xor r4, r4, r4 511 stw r4, SWCRR(r3) 5121: 513#endif /* CONFIG_WATCHDOG */ 514 515#if defined(CONFIG_MASK_AER_AO) 516 /* Write the Arbiter Event Enable to mask Address Only traps. */ 517 /* This prevents the dcbz instruction from being trapped when */ 518 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 519 /* COHERENCY bit is set in the WIMG bits, which is often */ 520 /* needed for PCI operation. */ 521 lwz r4, 0x0808(r3) 522 rlwinm r0, r4, 0, ~AER_AO 523 stw r0, 0x0808(r3) 524#endif /* CONFIG_MASK_AER_AO */ 525 526 /* Initialize the Hardware Implementation-dependent Registers */ 527 /* HID0 also contains cache control */ 528 /* - force invalidation of data and instruction caches */ 529 /*------------------------------------------------------*/ 530 531 lis r3, CONFIG_SYS_HID0_INIT@h 532 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 533 SYNC 534 mtspr HID0, r3 535 536 lis r3, CONFIG_SYS_HID0_FINAL@h 537 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 538 SYNC 539 mtspr HID0, r3 540 541 lis r3, CONFIG_SYS_HID2@h 542 ori r3, r3, CONFIG_SYS_HID2@l 543 SYNC 544 mtspr HID2, r3 545 546 /* Done! */ 547 /*------------------------------*/ 548 blr 549 550 /* setup_bats - set them up to some initial state */ 551 .globl setup_bats 552setup_bats: 553 addis r0, r0, 0x0000 554 555 /* IBAT 0 */ 556 addis r4, r0, CONFIG_SYS_IBAT0L@h 557 ori r4, r4, CONFIG_SYS_IBAT0L@l 558 addis r3, r0, CONFIG_SYS_IBAT0U@h 559 ori r3, r3, CONFIG_SYS_IBAT0U@l 560 mtspr IBAT0L, r4 561 mtspr IBAT0U, r3 562 563 /* DBAT 0 */ 564 addis r4, r0, CONFIG_SYS_DBAT0L@h 565 ori r4, r4, CONFIG_SYS_DBAT0L@l 566 addis r3, r0, CONFIG_SYS_DBAT0U@h 567 ori r3, r3, CONFIG_SYS_DBAT0U@l 568 mtspr DBAT0L, r4 569 mtspr DBAT0U, r3 570 571 /* IBAT 1 */ 572 addis r4, r0, CONFIG_SYS_IBAT1L@h 573 ori r4, r4, CONFIG_SYS_IBAT1L@l 574 addis r3, r0, CONFIG_SYS_IBAT1U@h 575 ori r3, r3, CONFIG_SYS_IBAT1U@l 576 mtspr IBAT1L, r4 577 mtspr IBAT1U, r3 578 579 /* DBAT 1 */ 580 addis r4, r0, CONFIG_SYS_DBAT1L@h 581 ori r4, r4, CONFIG_SYS_DBAT1L@l 582 addis r3, r0, CONFIG_SYS_DBAT1U@h 583 ori r3, r3, CONFIG_SYS_DBAT1U@l 584 mtspr DBAT1L, r4 585 mtspr DBAT1U, r3 586 587 /* IBAT 2 */ 588 addis r4, r0, CONFIG_SYS_IBAT2L@h 589 ori r4, r4, CONFIG_SYS_IBAT2L@l 590 addis r3, r0, CONFIG_SYS_IBAT2U@h 591 ori r3, r3, CONFIG_SYS_IBAT2U@l 592 mtspr IBAT2L, r4 593 mtspr IBAT2U, r3 594 595 /* DBAT 2 */ 596 addis r4, r0, CONFIG_SYS_DBAT2L@h 597 ori r4, r4, CONFIG_SYS_DBAT2L@l 598 addis r3, r0, CONFIG_SYS_DBAT2U@h 599 ori r3, r3, CONFIG_SYS_DBAT2U@l 600 mtspr DBAT2L, r4 601 mtspr DBAT2U, r3 602 603 /* IBAT 3 */ 604 addis r4, r0, CONFIG_SYS_IBAT3L@h 605 ori r4, r4, CONFIG_SYS_IBAT3L@l 606 addis r3, r0, CONFIG_SYS_IBAT3U@h 607 ori r3, r3, CONFIG_SYS_IBAT3U@l 608 mtspr IBAT3L, r4 609 mtspr IBAT3U, r3 610 611 /* DBAT 3 */ 612 addis r4, r0, CONFIG_SYS_DBAT3L@h 613 ori r4, r4, CONFIG_SYS_DBAT3L@l 614 addis r3, r0, CONFIG_SYS_DBAT3U@h 615 ori r3, r3, CONFIG_SYS_DBAT3U@l 616 mtspr DBAT3L, r4 617 mtspr DBAT3U, r3 618 619#ifdef CONFIG_HIGH_BATS 620 /* IBAT 4 */ 621 addis r4, r0, CONFIG_SYS_IBAT4L@h 622 ori r4, r4, CONFIG_SYS_IBAT4L@l 623 addis r3, r0, CONFIG_SYS_IBAT4U@h 624 ori r3, r3, CONFIG_SYS_IBAT4U@l 625 mtspr IBAT4L, r4 626 mtspr IBAT4U, r3 627 628 /* DBAT 4 */ 629 addis r4, r0, CONFIG_SYS_DBAT4L@h 630 ori r4, r4, CONFIG_SYS_DBAT4L@l 631 addis r3, r0, CONFIG_SYS_DBAT4U@h 632 ori r3, r3, CONFIG_SYS_DBAT4U@l 633 mtspr DBAT4L, r4 634 mtspr DBAT4U, r3 635 636 /* IBAT 5 */ 637 addis r4, r0, CONFIG_SYS_IBAT5L@h 638 ori r4, r4, CONFIG_SYS_IBAT5L@l 639 addis r3, r0, CONFIG_SYS_IBAT5U@h 640 ori r3, r3, CONFIG_SYS_IBAT5U@l 641 mtspr IBAT5L, r4 642 mtspr IBAT5U, r3 643 644 /* DBAT 5 */ 645 addis r4, r0, CONFIG_SYS_DBAT5L@h 646 ori r4, r4, CONFIG_SYS_DBAT5L@l 647 addis r3, r0, CONFIG_SYS_DBAT5U@h 648 ori r3, r3, CONFIG_SYS_DBAT5U@l 649 mtspr DBAT5L, r4 650 mtspr DBAT5U, r3 651 652 /* IBAT 6 */ 653 addis r4, r0, CONFIG_SYS_IBAT6L@h 654 ori r4, r4, CONFIG_SYS_IBAT6L@l 655 addis r3, r0, CONFIG_SYS_IBAT6U@h 656 ori r3, r3, CONFIG_SYS_IBAT6U@l 657 mtspr IBAT6L, r4 658 mtspr IBAT6U, r3 659 660 /* DBAT 6 */ 661 addis r4, r0, CONFIG_SYS_DBAT6L@h 662 ori r4, r4, CONFIG_SYS_DBAT6L@l 663 addis r3, r0, CONFIG_SYS_DBAT6U@h 664 ori r3, r3, CONFIG_SYS_DBAT6U@l 665 mtspr DBAT6L, r4 666 mtspr DBAT6U, r3 667 668 /* IBAT 7 */ 669 addis r4, r0, CONFIG_SYS_IBAT7L@h 670 ori r4, r4, CONFIG_SYS_IBAT7L@l 671 addis r3, r0, CONFIG_SYS_IBAT7U@h 672 ori r3, r3, CONFIG_SYS_IBAT7U@l 673 mtspr IBAT7L, r4 674 mtspr IBAT7U, r3 675 676 /* DBAT 7 */ 677 addis r4, r0, CONFIG_SYS_DBAT7L@h 678 ori r4, r4, CONFIG_SYS_DBAT7L@l 679 addis r3, r0, CONFIG_SYS_DBAT7U@h 680 ori r3, r3, CONFIG_SYS_DBAT7U@l 681 mtspr DBAT7L, r4 682 mtspr DBAT7U, r3 683#endif 684 685 isync 686 687 /* invalidate all tlb's 688 * 689 * From the 603e User Manual: "The 603e provides the ability to 690 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 691 * instruction invalidates the TLB entry indexed by the EA, and 692 * operates on both the instruction and data TLBs simultaneously 693 * invalidating four TLB entries (both sets in each TLB). The 694 * index corresponds to bits 15-19 of the EA. To invalidate all 695 * entries within both TLBs, 32 tlbie instructions should be 696 * issued, incrementing this field by one each time." 697 * 698 * "Note that the tlbia instruction is not implemented on the 699 * 603e." 700 * 701 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 702 * incrementing by 0x1000 each time. The code below is sort of 703 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 704 * 705 */ 706 lis r3, 0 707 lis r5, 2 708 7091: 710 tlbie r3 711 addi r3, r3, 0x1000 712 cmp 0, 0, r3, r5 713 blt 1b 714 715 blr 716 717/* Cache functions. 718 * 719 * Note: requires that all cache bits in 720 * HID0 are in the low half word. 721 */ 722#ifndef MINIMAL_SPL 723 .globl icache_enable 724icache_enable: 725 mfspr r3, HID0 726 ori r3, r3, HID0_ICE 727 li r4, HID0_ICFI|HID0_ILOCK 728 andc r3, r3, r4 729 ori r4, r3, HID0_ICFI 730 isync 731 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 732 isync 733 mtspr HID0, r3 /* clears invalidate */ 734 blr 735 736 .globl icache_disable 737icache_disable: 738 mfspr r3, HID0 739 lis r4, 0 740 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 741 andc r3, r3, r4 742 isync 743 mtspr HID0, r3 /* clears invalidate, enable and lock */ 744 blr 745 746 .globl icache_status 747icache_status: 748 mfspr r3, HID0 749 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 750 blr 751#endif /* !MINIMAL_SPL */ 752 753 .globl dcache_enable 754dcache_enable: 755 mfspr r3, HID0 756 li r5, HID0_DCFI|HID0_DLOCK 757 andc r3, r3, r5 758 ori r3, r3, HID0_DCE 759 sync 760 mtspr HID0, r3 /* enable, no invalidate */ 761 blr 762 763 .globl dcache_disable 764dcache_disable: 765 mflr r4 766 bl flush_dcache /* uses r3 and r5 */ 767 mfspr r3, HID0 768 li r5, HID0_DCE|HID0_DLOCK 769 andc r3, r3, r5 770 ori r5, r3, HID0_DCFI 771 sync 772 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 773 sync 774 mtspr HID0, r3 /* clears invalidate */ 775 mtlr r4 776 blr 777 778 .globl dcache_status 779dcache_status: 780 mfspr r3, HID0 781 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 782 blr 783 784 .globl flush_dcache 785flush_dcache: 786 lis r3, 0 787 lis r5, CONFIG_SYS_CACHELINE_SIZE 7881: cmp 0, 1, r3, r5 789 bge 2f 790 lwz r5, 0(r3) 791 lis r5, CONFIG_SYS_CACHELINE_SIZE 792 addi r3, r3, 0x4 793 b 1b 7942: blr 795 796/*-------------------------------------------------------------------*/ 797 798/* 799 * void relocate_code (addr_sp, gd, addr_moni) 800 * 801 * This "function" does not return, instead it continues in RAM 802 * after relocating the monitor code. 803 * 804 * r3 = dest 805 * r4 = src 806 * r5 = length in bytes 807 * r6 = cachelinesize 808 */ 809 .globl relocate_code 810relocate_code: 811 mr r1, r3 /* Set new stack pointer */ 812 mr r9, r4 /* Save copy of Global Data pointer */ 813 mr r10, r5 /* Save copy of Destination Address */ 814 815 GET_GOT 816 mr r3, r5 /* Destination Address */ 817 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 818 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 819 lwz r5, GOT(__bss_start) 820 sub r5, r5, r4 821 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 822 823 /* 824 * Fix GOT pointer: 825 * 826 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 827 * + Destination Address 828 * 829 * Offset: 830 */ 831 sub r15, r10, r4 832 833 /* First our own GOT */ 834 add r12, r12, r15 835 /* then the one used by the C code */ 836 add r30, r30, r15 837 838 /* 839 * Now relocate code 840 */ 841 842 cmplw cr1,r3,r4 843 addi r0,r5,3 844 srwi. r0,r0,2 845 beq cr1,4f /* In place copy is not necessary */ 846 beq 7f /* Protect against 0 count */ 847 mtctr r0 848 bge cr1,2f 849 la r8,-4(r4) 850 la r7,-4(r3) 851 852 /* copy */ 8531: lwzu r0,4(r8) 854 stwu r0,4(r7) 855 bdnz 1b 856 857 addi r0,r5,3 858 srwi. r0,r0,2 859 mtctr r0 860 la r8,-4(r4) 861 la r7,-4(r3) 862 863 /* and compare */ 86420: lwzu r20,4(r8) 865 lwzu r21,4(r7) 866 xor. r22, r20, r21 867 bne 30f 868 bdnz 20b 869 b 4f 870 871 /* compare failed */ 87230: li r3, 0 873 blr 874 8752: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 876 add r8,r4,r0 877 add r7,r3,r0 8783: lwzu r0,-4(r8) 879 stwu r0,-4(r7) 880 bdnz 3b 881 882/* 883 * Now flush the cache: note that we must start from a cache aligned 884 * address. Otherwise we might miss one cache line. 885 */ 8864: cmpwi r6,0 887 add r5,r3,r5 888 beq 7f /* Always flush prefetch queue in any case */ 889 subi r0,r6,1 890 andc r3,r3,r0 891 mr r4,r3 8925: dcbst 0,r4 893 add r4,r4,r6 894 cmplw r4,r5 895 blt 5b 896 sync /* Wait for all dcbst to complete on bus */ 897 mr r4,r3 8986: icbi 0,r4 899 add r4,r4,r6 900 cmplw r4,r5 901 blt 6b 9027: sync /* Wait for all icbi to complete on bus */ 903 isync 904 905/* 906 * We are done. Do not return, instead branch to second part of board 907 * initialization, now running from RAM. 908 */ 909 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 910 mtlr r0 911 blr 912 913in_ram: 914 915 /* 916 * Relocation Function, r12 point to got2+0x8000 917 * 918 * Adjust got2 pointers, no need to check for 0, this code 919 * already puts a few entries in the table. 920 */ 921 li r0,__got2_entries@sectoff@l 922 la r3,GOT(_GOT2_TABLE_) 923 lwz r11,GOT(_GOT2_TABLE_) 924 mtctr r0 925 sub r11,r3,r11 926 addi r3,r3,-4 9271: lwzu r0,4(r3) 928 cmpwi r0,0 929 beq- 2f 930 add r0,r0,r11 931 stw r0,0(r3) 9322: bdnz 1b 933 934#ifndef MINIMAL_SPL 935 /* 936 * Now adjust the fixups and the pointers to the fixups 937 * in case we need to move ourselves again. 938 */ 939 li r0,__fixup_entries@sectoff@l 940 lwz r3,GOT(_FIXUP_TABLE_) 941 cmpwi r0,0 942 mtctr r0 943 addi r3,r3,-4 944 beq 4f 9453: lwzu r4,4(r3) 946 lwzux r0,r4,r11 947 cmpwi r0,0 948 add r0,r0,r11 949 stw r4,0(r3) 950 beq- 5f 951 stw r0,0(r4) 9525: bdnz 3b 9534: 954#endif 955 956clear_bss: 957 /* 958 * Now clear BSS segment 959 */ 960 lwz r3,GOT(__bss_start) 961 lwz r4,GOT(__bss_end) 962 963 cmplw 0, r3, r4 964 beq 6f 965 966 li r0, 0 9675: 968 stw r0, 0(r3) 969 addi r3, r3, 4 970 cmplw 0, r3, r4 971 bne 5b 9726: 973 974 mr r3, r9 /* Global Data pointer */ 975 mr r4, r10 /* Destination Address */ 976 bl board_init_r 977 978#ifndef MINIMAL_SPL 979 /* 980 * Copy exception vector code to low memory 981 * 982 * r3: dest_addr 983 * r7: source address, r8: end address, r9: target address 984 */ 985 .globl trap_init 986trap_init: 987 mflr r4 /* save link register */ 988 GET_GOT 989 lwz r7, GOT(_start) 990 lwz r8, GOT(_end_of_vectors) 991 992 li r9, 0x100 /* reset vector always at 0x100 */ 993 994 cmplw 0, r7, r8 995 bgelr /* return if r7>=r8 - just in case */ 9961: 997 lwz r0, 0(r7) 998 stw r0, 0(r9) 999 addi r7, r7, 4 1000 addi r9, r9, 4 1001 cmplw 0, r7, r8 1002 bne 1b 1003 1004 /* 1005 * relocate `hdlr' and `int_return' entries 1006 */ 1007 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1008 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10092: 1010 bl trap_reloc 1011 addi r7, r7, 0x100 /* next exception vector */ 1012 cmplw 0, r7, r8 1013 blt 2b 1014 1015 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1016 bl trap_reloc 1017 1018 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1019 bl trap_reloc 1020 1021 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1022 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10233: 1024 bl trap_reloc 1025 addi r7, r7, 0x100 /* next exception vector */ 1026 cmplw 0, r7, r8 1027 blt 3b 1028 1029 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1030 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10314: 1032 bl trap_reloc 1033 addi r7, r7, 0x100 /* next exception vector */ 1034 cmplw 0, r7, r8 1035 blt 4b 1036 1037 mfmsr r3 /* now that the vectors have */ 1038 lis r7, MSR_IP@h /* relocated into low memory */ 1039 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1040 andc r3, r3, r7 /* (if it was on) */ 1041 SYNC /* Some chip revs need this... */ 1042 mtmsr r3 1043 SYNC 1044 1045 mtlr r4 /* restore link register */ 1046 blr 1047 1048#endif /* !MINIMAL_SPL */ 1049 1050#ifdef CONFIG_SYS_INIT_RAM_LOCK 1051lock_ram_in_cache: 1052 /* Allocate Initial RAM in data cache. 1053 */ 1054 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1055 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1056 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1057 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1058 mtctr r4 10591: 1060 dcbz r0, r3 1061 addi r3, r3, 32 1062 bdnz 1b 1063 1064 /* Lock the data cache */ 1065 mfspr r0, HID0 1066 ori r0, r0, HID0_DLOCK 1067 sync 1068 mtspr HID0, r0 1069 sync 1070 blr 1071 1072#ifndef MINIMAL_SPL 1073.globl unlock_ram_in_cache 1074unlock_ram_in_cache: 1075 /* invalidate the INIT_RAM section */ 1076 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1077 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1078 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1079 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1080 mtctr r4 10811: icbi r0, r3 1082 dcbi r0, r3 1083 addi r3, r3, 32 1084 bdnz 1b 1085 sync /* Wait for all icbi to complete on bus */ 1086 isync 1087 1088 /* Unlock the data cache and invalidate it */ 1089 mfspr r3, HID0 1090 li r5, HID0_DLOCK|HID0_DCFI 1091 andc r3, r3, r5 /* no invalidate, unlock */ 1092 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1093 sync 1094 mtspr HID0, r5 /* invalidate, unlock */ 1095 sync 1096 mtspr HID0, r3 /* no invalidate, unlock */ 1097 blr 1098#endif /* !MINIMAL_SPL */ 1099#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1100 1101#ifdef CONFIG_SYS_FLASHBOOT 1102map_flash_by_law1: 1103 /* When booting from ROM (Flash or EPROM), clear the */ 1104 /* Address Mask in OR0 so ROM appears everywhere */ 1105 /*----------------------------------------------------*/ 1106 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1107 lwz r4, OR0@l(r3) 1108 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1109 and r4, r4, r5 1110 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1111 1112 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1113 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1114 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1115 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1116 * 0xFF800. From the hard resetting to here, the processor fetched and 1117 * executed the instructions one by one. There is not absolutely 1118 * jumping happened. Laterly, the u-boot code has to do an absolutely 1119 * jumping to tell the CPU instruction fetching component what the 1120 * u-boot TEXT base address is. Because the TEXT base resides in the 1121 * boot ROM memory space, to garantee the code can run smoothly after 1122 * that jumping, we must map in the entire boot ROM by Local Access 1123 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1124 * address for boot ROM, such as 0xFE000000. In this case, the default 1125 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1126 * need another window to map in it. 1127 */ 1128 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1129 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1130 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1131 1132 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1133 lis r4, (0x80000012)@h 1134 ori r4, r4, (0x80000012)@l 1135 li r5, CONFIG_SYS_FLASH_SIZE 11361: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1137 addi r4, r4, 1 1138 bne 1b 1139 1140 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1141 /* Wait for HW to catch up */ 1142 lwz r4, LBLAWAR1(r3) 1143 twi 0,r4,0 1144 isync 1145 blr 1146 1147 /* Though all the LBIU Local Access Windows and LBC Banks will be 1148 * initialized in the C code, we'd better configure boot ROM's 1149 * window 0 and bank 0 correctly at here. 1150 */ 1151remap_flash_by_law0: 1152 /* Initialize the BR0 with the boot ROM starting address. */ 1153 lwz r4, BR0(r3) 1154 li r5, 0x7FFF 1155 and r4, r4, r5 1156 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1157 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1158 or r5, r5, r4 1159 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1160 1161 lwz r4, OR0(r3) 1162 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1163 or r4, r4, r5 1164 stw r4, OR0(r3) 1165 1166 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1167 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1168 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1169 1170 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1171 lis r4, (0x80000012)@h 1172 ori r4, r4, (0x80000012)@l 1173 li r5, CONFIG_SYS_FLASH_SIZE 11741: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1175 addi r4, r4, 1 1176 bne 1b 1177 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1178 1179 1180 xor r4, r4, r4 1181 stw r4, LBLAWBAR1(r3) 1182 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1183 /* Wait for HW to catch up */ 1184 lwz r4, LBLAWAR1(r3) 1185 twi 0,r4,0 1186 isync 1187 blr 1188#endif /* CONFIG_SYS_FLASHBOOT */ 1189