1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 12 */ 13 14#include <asm-offsets.h> 15#include <config.h> 16#include <mpc83xx.h> 17#ifndef CONFIG_IDENT_STRING 18#define CONFIG_IDENT_STRING "MPC83XX" 19#endif 20#include <version.h> 21 22#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 23#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 24 25#include <ppc_asm.tmpl> 26#include <ppc_defs.h> 27 28#include <asm/cache.h> 29#include <asm/mmu.h> 30#include <asm/u-boot.h> 31 32/* We don't want the MMU yet. 33 */ 34#undef MSR_KERNEL 35 36/* 37 * Floating Point enable, Machine Check and Recoverable Interr. 38 */ 39#ifdef DEBUG 40#define MSR_KERNEL (MSR_FP|MSR_RI) 41#else 42#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 43#endif 44 45#if defined(CONFIG_NAND_SPL) || \ 46 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 47#define MINIMAL_SPL 48#endif 49 50#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 51 !defined(CONFIG_SYS_RAMBOOT) 52#define CONFIG_SYS_FLASHBOOT 53#endif 54 55/* 56 * Set up GOT: Global Offset Table 57 * 58 * Use r12 to access the GOT 59 */ 60 START_GOT 61 GOT_ENTRY(_GOT2_TABLE_) 62 GOT_ENTRY(__bss_start) 63 GOT_ENTRY(__bss_end) 64 65#ifndef MINIMAL_SPL 66 GOT_ENTRY(_FIXUP_TABLE_) 67 GOT_ENTRY(_start) 68 GOT_ENTRY(_start_of_vectors) 69 GOT_ENTRY(_end_of_vectors) 70 GOT_ENTRY(transfer_to_handler) 71#endif 72 END_GOT 73 74/* 75 * The Hard Reset Configuration Word (HRCW) table is in the first 64 76 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 77 * times so the processor can fetch it out of flash whether the flash 78 * is 8, 16, 32, or 64 bits wide (hardware trickery). 79 */ 80 .text 81#define _HRCW_TABLE_ENTRY(w) \ 82 .fill 8,1,(((w)>>24)&0xff); \ 83 .fill 8,1,(((w)>>16)&0xff); \ 84 .fill 8,1,(((w)>> 8)&0xff); \ 85 .fill 8,1,(((w) )&0xff) 86 87 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 88 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 89 90/* 91 * Magic number and version string - put it after the HRCW since it 92 * cannot be first in flash like it is in many other processors. 93 */ 94 .long 0x27051956 /* U-Boot Magic Number */ 95 96 .globl version_string 97version_string: 98 .ascii U_BOOT_VERSION_STRING, "\0" 99 100 .align 2 101 102 .globl enable_addr_trans 103enable_addr_trans: 104 /* enable address translation */ 105 mfmsr r5 106 ori r5, r5, (MSR_IR | MSR_DR) 107 mtmsr r5 108 isync 109 blr 110 111 .globl disable_addr_trans 112disable_addr_trans: 113 /* disable address translation */ 114 mflr r4 115 mfmsr r3 116 andi. r0, r3, (MSR_IR | MSR_DR) 117 beqlr 118 andc r3, r3, r0 119 mtspr SRR0, r4 120 mtspr SRR1, r3 121 rfi 122 123 .globl get_pvr 124get_pvr: 125 mfspr r3, PVR 126 blr 127 128 .globl ppcDWstore 129ppcDWstore: 130 lfd 1, 0(r4) 131 stfd 1, 0(r3) 132 blr 133 134 .globl ppcDWload 135ppcDWload: 136 lfd 1, 0(r3) 137 stfd 1, 0(r4) 138 blr 139 140#ifndef CONFIG_DEFAULT_IMMR 141#error CONFIG_DEFAULT_IMMR must be defined 142#endif /* CONFIG_SYS_DEFAULT_IMMR */ 143#ifndef CONFIG_SYS_IMMR 144#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 145#endif /* CONFIG_SYS_IMMR */ 146 147/* 148 * After configuration, a system reset exception is executed using the 149 * vector at offset 0x100 relative to the base set by MSR[IP]. If 150 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 151 * base address is 0xfff00000. In the case of a Power On Reset or Hard 152 * Reset, the value of MSR[IP] is determined by the CIP field in the 153 * HRCW. 154 * 155 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 156 * This determines the location of the boot ROM (flash or EPROM) in the 157 * processor's address space at boot time. As long as the HRCW is set up 158 * so that we eventually end up executing the code below when the 159 * processor executes the reset exception, the actual values used should 160 * not matter. 161 * 162 * Once we have got here, the address mask in OR0 is cleared so that the 163 * bottom 32K of the boot ROM is effectively repeated all throughout the 164 * processor's address space, after which we can jump to the absolute 165 * address at which the boot ROM was linked at compile time, and proceed 166 * to initialise the memory controller without worrying if the rug will 167 * be pulled out from under us, so to speak (it will be fine as long as 168 * we configure BR0 with the same boot ROM link address). 169 */ 170 . = EXC_OFF_SYS_RESET 171 172 .globl _start 173_start: /* time t 0 */ 174 lis r4, CONFIG_DEFAULT_IMMR@h 175 nop 176 177 mfmsr r5 /* save msr contents */ 178 179 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 180 bl 1f 1811: mflr r7 182 183 lis r3, CONFIG_SYS_IMMR@h 184 ori r3, r3, CONFIG_SYS_IMMR@l 185 186 lwz r6, IMMRBAR(r4) 187 isync 188 189 stw r3, IMMRBAR(r4) 190 lwz r6, 0(r7) /* Arbitrary external load */ 191 isync 192 193 lwz r6, IMMRBAR(r3) 194 isync 195 196 /* Initialise the E300 processor core */ 197 /*------------------------------------------*/ 198 199#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 200 defined(CONFIG_NAND_SPL) 201 /* The FCM begins execution after only the first page 202 * is loaded. Wait for the rest before branching 203 * to another flash page. 204 */ 2051: lwz r6, 0x50b0(r3) 206 andi. r6, r6, 1 207 beq 1b 208#endif 209 210 bl init_e300_core 211 212#ifdef CONFIG_SYS_FLASHBOOT 213 214 /* Inflate flash location so it appears everywhere, calculate */ 215 /* the absolute address in final location of the FLASH, jump */ 216 /* there and deflate the flash size back to minimal size */ 217 /*------------------------------------------------------------*/ 218 bl map_flash_by_law1 219 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 220 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 221 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 222 mtlr r5 223 blr 224in_flash: 225#if 1 /* Remapping flash with LAW0. */ 226 bl remap_flash_by_law0 227#endif 228#endif /* CONFIG_SYS_FLASHBOOT */ 229 230 /* setup the bats */ 231 bl setup_bats 232 sync 233 234 /* 235 * Cache must be enabled here for stack-in-cache trick. 236 * This means we need to enable the BATS. 237 * This means: 238 * 1) for the EVB, original gt regs need to be mapped 239 * 2) need to have an IBAT for the 0xf region, 240 * we are running there! 241 * Cache should be turned on after BATs, since by default 242 * everything is write-through. 243 * The init-mem BAT can be reused after reloc. The old 244 * gt-regs BAT can be reused after board_init_f calls 245 * board_early_init_f (EVB only). 246 */ 247 /* enable address translation */ 248 bl enable_addr_trans 249 sync 250 251 /* enable the data cache */ 252 bl dcache_enable 253 sync 254#ifdef CONFIG_SYS_INIT_RAM_LOCK 255 bl lock_ram_in_cache 256 sync 257#endif 258 259 /* set up the stack pointer in our newly created 260 * cache-ram (r1) */ 261 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 262 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 263 264 li r0, 0 /* Make room for stack frame header and */ 265 stwu r0, -4(r1) /* clear final stack frame so that */ 266 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 267 268 269 /* let the C-code set up the rest */ 270 /* */ 271 /* Be careful to keep code relocatable & stack humble */ 272 /*------------------------------------------------------*/ 273 274 GET_GOT /* initialize GOT access */ 275 276 /* r3: IMMR */ 277 lis r3, CONFIG_SYS_IMMR@h 278 /* run low-level CPU init code (in Flash)*/ 279 bl cpu_init_f 280 281 /* run 1st part of board init code (in Flash)*/ 282 bl board_init_f 283 284 /* NOTREACHED - board_init_f() does not return */ 285 286#ifndef MINIMAL_SPL 287/* 288 * Vector Table 289 */ 290 291 .globl _start_of_vectors 292_start_of_vectors: 293 294/* Machine check */ 295 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 296 297/* Data Storage exception. */ 298 STD_EXCEPTION(0x300, DataStorage, UnknownException) 299 300/* Instruction Storage exception. */ 301 STD_EXCEPTION(0x400, InstStorage, UnknownException) 302 303/* External Interrupt exception. */ 304#ifndef FIXME 305 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 306#endif 307 308/* Alignment exception. */ 309 . = 0x600 310Alignment: 311 EXCEPTION_PROLOG(SRR0, SRR1) 312 mfspr r4,DAR 313 stw r4,_DAR(r21) 314 mfspr r5,DSISR 315 stw r5,_DSISR(r21) 316 addi r3,r1,STACK_FRAME_OVERHEAD 317 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 318 319/* Program check exception */ 320 . = 0x700 321ProgramCheck: 322 EXCEPTION_PROLOG(SRR0, SRR1) 323 addi r3,r1,STACK_FRAME_OVERHEAD 324 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 325 MSR_KERNEL, COPY_EE) 326 327 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 328 329 /* I guess we could implement decrementer, and may have 330 * to someday for timekeeping. 331 */ 332 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 333 334 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 335 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 336 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 337 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 338 339 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 340 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 341 342 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 343 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 344 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 345#ifdef DEBUG 346 . = 0x1300 347 /* 348 * This exception occurs when the program counter matches the 349 * Instruction Address Breakpoint Register (IABR). 350 * 351 * I want the cpu to halt if this occurs so I can hunt around 352 * with the debugger and look at things. 353 * 354 * When DEBUG is defined, both machine check enable (in the MSR) 355 * and checkstop reset enable (in the reset mode register) are 356 * turned off and so a checkstop condition will result in the cpu 357 * halting. 358 * 359 * I force the cpu into a checkstop condition by putting an illegal 360 * instruction here (at least this is the theory). 361 * 362 * well - that didnt work, so just do an infinite loop! 363 */ 3641: b 1b 365#else 366 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 367#endif 368 STD_EXCEPTION(0x1400, SMI, UnknownException) 369 370 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 371 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 372 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 373 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 374 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 375 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 376 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 377 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 378 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 379 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 380 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 381 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 382 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 383 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 384 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 385 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 386 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 387 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 388 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 389 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 390 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 391 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 392 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 393 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 394 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 395 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 396 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 397 398 399 .globl _end_of_vectors 400_end_of_vectors: 401 402 . = 0x3000 403 404/* 405 * This code finishes saving the registers to the exception frame 406 * and jumps to the appropriate handler for the exception. 407 * Register r21 is pointer into trap frame, r1 has new stack pointer. 408 */ 409 .globl transfer_to_handler 410transfer_to_handler: 411 stw r22,_NIP(r21) 412 lis r22,MSR_POW@h 413 andc r23,r23,r22 414 stw r23,_MSR(r21) 415 SAVE_GPR(7, r21) 416 SAVE_4GPRS(8, r21) 417 SAVE_8GPRS(12, r21) 418 SAVE_8GPRS(24, r21) 419 mflr r23 420 andi. r24,r23,0x3f00 /* get vector offset */ 421 stw r24,TRAP(r21) 422 li r22,0 423 stw r22,RESULT(r21) 424 lwz r24,0(r23) /* virtual address of handler */ 425 lwz r23,4(r23) /* where to go when done */ 426 mtspr SRR0,r24 427 mtspr SRR1,r20 428 mtlr r23 429 SYNC 430 rfi /* jump to handler, enable MMU */ 431 432int_return: 433 mfmsr r28 /* Disable interrupts */ 434 li r4,0 435 ori r4,r4,MSR_EE 436 andc r28,r28,r4 437 SYNC /* Some chip revs need this... */ 438 mtmsr r28 439 SYNC 440 lwz r2,_CTR(r1) 441 lwz r0,_LINK(r1) 442 mtctr r2 443 mtlr r0 444 lwz r2,_XER(r1) 445 lwz r0,_CCR(r1) 446 mtspr XER,r2 447 mtcrf 0xFF,r0 448 REST_10GPRS(3, r1) 449 REST_10GPRS(13, r1) 450 REST_8GPRS(23, r1) 451 REST_GPR(31, r1) 452 lwz r2,_NIP(r1) /* Restore environment */ 453 lwz r0,_MSR(r1) 454 mtspr SRR0,r2 455 mtspr SRR1,r0 456 lwz r0,GPR0(r1) 457 lwz r2,GPR2(r1) 458 lwz r1,GPR1(r1) 459 SYNC 460 rfi 461#endif /* !MINIMAL_SPL */ 462 463/* 464 * This code initialises the E300 processor core 465 * (conforms to PowerPC 603e spec) 466 * Note: expects original MSR contents to be in r5. 467 */ 468 .globl init_e300_core 469init_e300_core: /* time t 10 */ 470 /* Initialize machine status; enable machine check interrupt */ 471 /*-----------------------------------------------------------*/ 472 473 li r3, MSR_KERNEL /* Set ME and RI flags */ 474 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 475#ifdef DEBUG 476 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 477#endif 478 SYNC /* Some chip revs need this... */ 479 mtmsr r3 480 SYNC 481 mtspr SRR1, r3 /* Make SRR1 match MSR */ 482 483 484 lis r3, CONFIG_SYS_IMMR@h 485#if defined(CONFIG_WATCHDOG) 486 /* Initialise the Watchdog values and reset it (if req) */ 487 /*------------------------------------------------------*/ 488 lis r4, CONFIG_SYS_WATCHDOG_VALUE 489 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 490 stw r4, SWCRR(r3) 491 492 /* and reset it */ 493 494 li r4, 0x556C 495 sth r4, SWSRR@l(r3) 496 li r4, -0x55C7 497 sth r4, SWSRR@l(r3) 498#else 499 /* Disable Watchdog */ 500 /*-------------------*/ 501 lwz r4, SWCRR(r3) 502 /* Check to see if its enabled for disabling 503 once disabled by SW you can't re-enable */ 504 andi. r4, r4, 0x4 505 beq 1f 506 xor r4, r4, r4 507 stw r4, SWCRR(r3) 5081: 509#endif /* CONFIG_WATCHDOG */ 510 511#if defined(CONFIG_MASK_AER_AO) 512 /* Write the Arbiter Event Enable to mask Address Only traps. */ 513 /* This prevents the dcbz instruction from being trapped when */ 514 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 515 /* COHERENCY bit is set in the WIMG bits, which is often */ 516 /* needed for PCI operation. */ 517 lwz r4, 0x0808(r3) 518 rlwinm r0, r4, 0, ~AER_AO 519 stw r0, 0x0808(r3) 520#endif /* CONFIG_MASK_AER_AO */ 521 522 /* Initialize the Hardware Implementation-dependent Registers */ 523 /* HID0 also contains cache control */ 524 /* - force invalidation of data and instruction caches */ 525 /*------------------------------------------------------*/ 526 527 lis r3, CONFIG_SYS_HID0_INIT@h 528 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 529 SYNC 530 mtspr HID0, r3 531 532 lis r3, CONFIG_SYS_HID0_FINAL@h 533 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 534 SYNC 535 mtspr HID0, r3 536 537 lis r3, CONFIG_SYS_HID2@h 538 ori r3, r3, CONFIG_SYS_HID2@l 539 SYNC 540 mtspr HID2, r3 541 542 /* Done! */ 543 /*------------------------------*/ 544 blr 545 546 /* setup_bats - set them up to some initial state */ 547 .globl setup_bats 548setup_bats: 549 addis r0, r0, 0x0000 550 551 /* IBAT 0 */ 552 addis r4, r0, CONFIG_SYS_IBAT0L@h 553 ori r4, r4, CONFIG_SYS_IBAT0L@l 554 addis r3, r0, CONFIG_SYS_IBAT0U@h 555 ori r3, r3, CONFIG_SYS_IBAT0U@l 556 mtspr IBAT0L, r4 557 mtspr IBAT0U, r3 558 559 /* DBAT 0 */ 560 addis r4, r0, CONFIG_SYS_DBAT0L@h 561 ori r4, r4, CONFIG_SYS_DBAT0L@l 562 addis r3, r0, CONFIG_SYS_DBAT0U@h 563 ori r3, r3, CONFIG_SYS_DBAT0U@l 564 mtspr DBAT0L, r4 565 mtspr DBAT0U, r3 566 567 /* IBAT 1 */ 568 addis r4, r0, CONFIG_SYS_IBAT1L@h 569 ori r4, r4, CONFIG_SYS_IBAT1L@l 570 addis r3, r0, CONFIG_SYS_IBAT1U@h 571 ori r3, r3, CONFIG_SYS_IBAT1U@l 572 mtspr IBAT1L, r4 573 mtspr IBAT1U, r3 574 575 /* DBAT 1 */ 576 addis r4, r0, CONFIG_SYS_DBAT1L@h 577 ori r4, r4, CONFIG_SYS_DBAT1L@l 578 addis r3, r0, CONFIG_SYS_DBAT1U@h 579 ori r3, r3, CONFIG_SYS_DBAT1U@l 580 mtspr DBAT1L, r4 581 mtspr DBAT1U, r3 582 583 /* IBAT 2 */ 584 addis r4, r0, CONFIG_SYS_IBAT2L@h 585 ori r4, r4, CONFIG_SYS_IBAT2L@l 586 addis r3, r0, CONFIG_SYS_IBAT2U@h 587 ori r3, r3, CONFIG_SYS_IBAT2U@l 588 mtspr IBAT2L, r4 589 mtspr IBAT2U, r3 590 591 /* DBAT 2 */ 592 addis r4, r0, CONFIG_SYS_DBAT2L@h 593 ori r4, r4, CONFIG_SYS_DBAT2L@l 594 addis r3, r0, CONFIG_SYS_DBAT2U@h 595 ori r3, r3, CONFIG_SYS_DBAT2U@l 596 mtspr DBAT2L, r4 597 mtspr DBAT2U, r3 598 599 /* IBAT 3 */ 600 addis r4, r0, CONFIG_SYS_IBAT3L@h 601 ori r4, r4, CONFIG_SYS_IBAT3L@l 602 addis r3, r0, CONFIG_SYS_IBAT3U@h 603 ori r3, r3, CONFIG_SYS_IBAT3U@l 604 mtspr IBAT3L, r4 605 mtspr IBAT3U, r3 606 607 /* DBAT 3 */ 608 addis r4, r0, CONFIG_SYS_DBAT3L@h 609 ori r4, r4, CONFIG_SYS_DBAT3L@l 610 addis r3, r0, CONFIG_SYS_DBAT3U@h 611 ori r3, r3, CONFIG_SYS_DBAT3U@l 612 mtspr DBAT3L, r4 613 mtspr DBAT3U, r3 614 615#ifdef CONFIG_HIGH_BATS 616 /* IBAT 4 */ 617 addis r4, r0, CONFIG_SYS_IBAT4L@h 618 ori r4, r4, CONFIG_SYS_IBAT4L@l 619 addis r3, r0, CONFIG_SYS_IBAT4U@h 620 ori r3, r3, CONFIG_SYS_IBAT4U@l 621 mtspr IBAT4L, r4 622 mtspr IBAT4U, r3 623 624 /* DBAT 4 */ 625 addis r4, r0, CONFIG_SYS_DBAT4L@h 626 ori r4, r4, CONFIG_SYS_DBAT4L@l 627 addis r3, r0, CONFIG_SYS_DBAT4U@h 628 ori r3, r3, CONFIG_SYS_DBAT4U@l 629 mtspr DBAT4L, r4 630 mtspr DBAT4U, r3 631 632 /* IBAT 5 */ 633 addis r4, r0, CONFIG_SYS_IBAT5L@h 634 ori r4, r4, CONFIG_SYS_IBAT5L@l 635 addis r3, r0, CONFIG_SYS_IBAT5U@h 636 ori r3, r3, CONFIG_SYS_IBAT5U@l 637 mtspr IBAT5L, r4 638 mtspr IBAT5U, r3 639 640 /* DBAT 5 */ 641 addis r4, r0, CONFIG_SYS_DBAT5L@h 642 ori r4, r4, CONFIG_SYS_DBAT5L@l 643 addis r3, r0, CONFIG_SYS_DBAT5U@h 644 ori r3, r3, CONFIG_SYS_DBAT5U@l 645 mtspr DBAT5L, r4 646 mtspr DBAT5U, r3 647 648 /* IBAT 6 */ 649 addis r4, r0, CONFIG_SYS_IBAT6L@h 650 ori r4, r4, CONFIG_SYS_IBAT6L@l 651 addis r3, r0, CONFIG_SYS_IBAT6U@h 652 ori r3, r3, CONFIG_SYS_IBAT6U@l 653 mtspr IBAT6L, r4 654 mtspr IBAT6U, r3 655 656 /* DBAT 6 */ 657 addis r4, r0, CONFIG_SYS_DBAT6L@h 658 ori r4, r4, CONFIG_SYS_DBAT6L@l 659 addis r3, r0, CONFIG_SYS_DBAT6U@h 660 ori r3, r3, CONFIG_SYS_DBAT6U@l 661 mtspr DBAT6L, r4 662 mtspr DBAT6U, r3 663 664 /* IBAT 7 */ 665 addis r4, r0, CONFIG_SYS_IBAT7L@h 666 ori r4, r4, CONFIG_SYS_IBAT7L@l 667 addis r3, r0, CONFIG_SYS_IBAT7U@h 668 ori r3, r3, CONFIG_SYS_IBAT7U@l 669 mtspr IBAT7L, r4 670 mtspr IBAT7U, r3 671 672 /* DBAT 7 */ 673 addis r4, r0, CONFIG_SYS_DBAT7L@h 674 ori r4, r4, CONFIG_SYS_DBAT7L@l 675 addis r3, r0, CONFIG_SYS_DBAT7U@h 676 ori r3, r3, CONFIG_SYS_DBAT7U@l 677 mtspr DBAT7L, r4 678 mtspr DBAT7U, r3 679#endif 680 681 isync 682 683 /* invalidate all tlb's 684 * 685 * From the 603e User Manual: "The 603e provides the ability to 686 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 687 * instruction invalidates the TLB entry indexed by the EA, and 688 * operates on both the instruction and data TLBs simultaneously 689 * invalidating four TLB entries (both sets in each TLB). The 690 * index corresponds to bits 15-19 of the EA. To invalidate all 691 * entries within both TLBs, 32 tlbie instructions should be 692 * issued, incrementing this field by one each time." 693 * 694 * "Note that the tlbia instruction is not implemented on the 695 * 603e." 696 * 697 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 698 * incrementing by 0x1000 each time. The code below is sort of 699 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 700 * 701 */ 702 lis r3, 0 703 lis r5, 2 704 7051: 706 tlbie r3 707 addi r3, r3, 0x1000 708 cmp 0, 0, r3, r5 709 blt 1b 710 711 blr 712 713/* Cache functions. 714 * 715 * Note: requires that all cache bits in 716 * HID0 are in the low half word. 717 */ 718#ifndef MINIMAL_SPL 719 .globl icache_enable 720icache_enable: 721 mfspr r3, HID0 722 ori r3, r3, HID0_ICE 723 li r4, HID0_ICFI|HID0_ILOCK 724 andc r3, r3, r4 725 ori r4, r3, HID0_ICFI 726 isync 727 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 728 isync 729 mtspr HID0, r3 /* clears invalidate */ 730 blr 731 732 .globl icache_disable 733icache_disable: 734 mfspr r3, HID0 735 lis r4, 0 736 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 737 andc r3, r3, r4 738 isync 739 mtspr HID0, r3 /* clears invalidate, enable and lock */ 740 blr 741 742 .globl icache_status 743icache_status: 744 mfspr r3, HID0 745 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 746 blr 747#endif /* !MINIMAL_SPL */ 748 749 .globl dcache_enable 750dcache_enable: 751 mfspr r3, HID0 752 li r5, HID0_DCFI|HID0_DLOCK 753 andc r3, r3, r5 754 ori r3, r3, HID0_DCE 755 sync 756 mtspr HID0, r3 /* enable, no invalidate */ 757 blr 758 759 .globl dcache_disable 760dcache_disable: 761 mflr r4 762 bl flush_dcache /* uses r3 and r5 */ 763 mfspr r3, HID0 764 li r5, HID0_DCE|HID0_DLOCK 765 andc r3, r3, r5 766 ori r5, r3, HID0_DCFI 767 sync 768 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 769 sync 770 mtspr HID0, r3 /* clears invalidate */ 771 mtlr r4 772 blr 773 774 .globl dcache_status 775dcache_status: 776 mfspr r3, HID0 777 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 778 blr 779 780 .globl flush_dcache 781flush_dcache: 782 lis r3, 0 783 lis r5, CONFIG_SYS_CACHELINE_SIZE 7841: cmp 0, 1, r3, r5 785 bge 2f 786 lwz r5, 0(r3) 787 lis r5, CONFIG_SYS_CACHELINE_SIZE 788 addi r3, r3, 0x4 789 b 1b 7902: blr 791 792/*-------------------------------------------------------------------*/ 793 794/* 795 * void relocate_code (addr_sp, gd, addr_moni) 796 * 797 * This "function" does not return, instead it continues in RAM 798 * after relocating the monitor code. 799 * 800 * r3 = dest 801 * r4 = src 802 * r5 = length in bytes 803 * r6 = cachelinesize 804 */ 805 .globl relocate_code 806relocate_code: 807 mr r1, r3 /* Set new stack pointer */ 808 mr r9, r4 /* Save copy of Global Data pointer */ 809 mr r10, r5 /* Save copy of Destination Address */ 810 811 GET_GOT 812 mr r3, r5 /* Destination Address */ 813 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 814 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 815 lwz r5, GOT(__bss_start) 816 sub r5, r5, r4 817 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 818 819 /* 820 * Fix GOT pointer: 821 * 822 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 823 * + Destination Address 824 * 825 * Offset: 826 */ 827 sub r15, r10, r4 828 829 /* First our own GOT */ 830 add r12, r12, r15 831 /* then the one used by the C code */ 832 add r30, r30, r15 833 834 /* 835 * Now relocate code 836 */ 837 838 cmplw cr1,r3,r4 839 addi r0,r5,3 840 srwi. r0,r0,2 841 beq cr1,4f /* In place copy is not necessary */ 842 beq 7f /* Protect against 0 count */ 843 mtctr r0 844 bge cr1,2f 845 la r8,-4(r4) 846 la r7,-4(r3) 847 848 /* copy */ 8491: lwzu r0,4(r8) 850 stwu r0,4(r7) 851 bdnz 1b 852 853 addi r0,r5,3 854 srwi. r0,r0,2 855 mtctr r0 856 la r8,-4(r4) 857 la r7,-4(r3) 858 859 /* and compare */ 86020: lwzu r20,4(r8) 861 lwzu r21,4(r7) 862 xor. r22, r20, r21 863 bne 30f 864 bdnz 20b 865 b 4f 866 867 /* compare failed */ 86830: li r3, 0 869 blr 870 8712: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 872 add r8,r4,r0 873 add r7,r3,r0 8743: lwzu r0,-4(r8) 875 stwu r0,-4(r7) 876 bdnz 3b 877 878/* 879 * Now flush the cache: note that we must start from a cache aligned 880 * address. Otherwise we might miss one cache line. 881 */ 8824: cmpwi r6,0 883 add r5,r3,r5 884 beq 7f /* Always flush prefetch queue in any case */ 885 subi r0,r6,1 886 andc r3,r3,r0 887 mr r4,r3 8885: dcbst 0,r4 889 add r4,r4,r6 890 cmplw r4,r5 891 blt 5b 892 sync /* Wait for all dcbst to complete on bus */ 893 mr r4,r3 8946: icbi 0,r4 895 add r4,r4,r6 896 cmplw r4,r5 897 blt 6b 8987: sync /* Wait for all icbi to complete on bus */ 899 isync 900 901/* 902 * We are done. Do not return, instead branch to second part of board 903 * initialization, now running from RAM. 904 */ 905 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 906 mtlr r0 907 blr 908 909in_ram: 910 911 /* 912 * Relocation Function, r12 point to got2+0x8000 913 * 914 * Adjust got2 pointers, no need to check for 0, this code 915 * already puts a few entries in the table. 916 */ 917 li r0,__got2_entries@sectoff@l 918 la r3,GOT(_GOT2_TABLE_) 919 lwz r11,GOT(_GOT2_TABLE_) 920 mtctr r0 921 sub r11,r3,r11 922 addi r3,r3,-4 9231: lwzu r0,4(r3) 924 cmpwi r0,0 925 beq- 2f 926 add r0,r0,r11 927 stw r0,0(r3) 9282: bdnz 1b 929 930#ifndef MINIMAL_SPL 931 /* 932 * Now adjust the fixups and the pointers to the fixups 933 * in case we need to move ourselves again. 934 */ 935 li r0,__fixup_entries@sectoff@l 936 lwz r3,GOT(_FIXUP_TABLE_) 937 cmpwi r0,0 938 mtctr r0 939 addi r3,r3,-4 940 beq 4f 9413: lwzu r4,4(r3) 942 lwzux r0,r4,r11 943 cmpwi r0,0 944 add r0,r0,r11 945 stw r4,0(r3) 946 beq- 5f 947 stw r0,0(r4) 9485: bdnz 3b 9494: 950#endif 951 952clear_bss: 953 /* 954 * Now clear BSS segment 955 */ 956 lwz r3,GOT(__bss_start) 957#if defined(CONFIG_HYMOD) 958 /* 959 * For HYMOD - the environment is the very last item in flash. 960 * The real .bss stops just before environment starts, so only 961 * clear up to that point. 962 * 963 * taken from mods for FADS board 964 */ 965 lwz r4,GOT(environment) 966#else 967 lwz r4,GOT(__bss_end) 968#endif 969 970 cmplw 0, r3, r4 971 beq 6f 972 973 li r0, 0 9745: 975 stw r0, 0(r3) 976 addi r3, r3, 4 977 cmplw 0, r3, r4 978 bne 5b 9796: 980 981 mr r3, r9 /* Global Data pointer */ 982 mr r4, r10 /* Destination Address */ 983 bl board_init_r 984 985#ifndef MINIMAL_SPL 986 /* 987 * Copy exception vector code to low memory 988 * 989 * r3: dest_addr 990 * r7: source address, r8: end address, r9: target address 991 */ 992 .globl trap_init 993trap_init: 994 mflr r4 /* save link register */ 995 GET_GOT 996 lwz r7, GOT(_start) 997 lwz r8, GOT(_end_of_vectors) 998 999 li r9, 0x100 /* reset vector always at 0x100 */ 1000 1001 cmplw 0, r7, r8 1002 bgelr /* return if r7>=r8 - just in case */ 10031: 1004 lwz r0, 0(r7) 1005 stw r0, 0(r9) 1006 addi r7, r7, 4 1007 addi r9, r9, 4 1008 cmplw 0, r7, r8 1009 bne 1b 1010 1011 /* 1012 * relocate `hdlr' and `int_return' entries 1013 */ 1014 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1015 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10162: 1017 bl trap_reloc 1018 addi r7, r7, 0x100 /* next exception vector */ 1019 cmplw 0, r7, r8 1020 blt 2b 1021 1022 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1023 bl trap_reloc 1024 1025 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1026 bl trap_reloc 1027 1028 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1029 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10303: 1031 bl trap_reloc 1032 addi r7, r7, 0x100 /* next exception vector */ 1033 cmplw 0, r7, r8 1034 blt 3b 1035 1036 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1037 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10384: 1039 bl trap_reloc 1040 addi r7, r7, 0x100 /* next exception vector */ 1041 cmplw 0, r7, r8 1042 blt 4b 1043 1044 mfmsr r3 /* now that the vectors have */ 1045 lis r7, MSR_IP@h /* relocated into low memory */ 1046 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1047 andc r3, r3, r7 /* (if it was on) */ 1048 SYNC /* Some chip revs need this... */ 1049 mtmsr r3 1050 SYNC 1051 1052 mtlr r4 /* restore link register */ 1053 blr 1054 1055#endif /* !MINIMAL_SPL */ 1056 1057#ifdef CONFIG_SYS_INIT_RAM_LOCK 1058lock_ram_in_cache: 1059 /* Allocate Initial RAM in data cache. 1060 */ 1061 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1062 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1063 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1064 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1065 mtctr r4 10661: 1067 dcbz r0, r3 1068 addi r3, r3, 32 1069 bdnz 1b 1070 1071 /* Lock the data cache */ 1072 mfspr r0, HID0 1073 ori r0, r0, HID0_DLOCK 1074 sync 1075 mtspr HID0, r0 1076 sync 1077 blr 1078 1079#ifndef MINIMAL_SPL 1080.globl unlock_ram_in_cache 1081unlock_ram_in_cache: 1082 /* invalidate the INIT_RAM section */ 1083 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1084 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1085 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1086 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1087 mtctr r4 10881: icbi r0, r3 1089 dcbi r0, r3 1090 addi r3, r3, 32 1091 bdnz 1b 1092 sync /* Wait for all icbi to complete on bus */ 1093 isync 1094 1095 /* Unlock the data cache and invalidate it */ 1096 mfspr r3, HID0 1097 li r5, HID0_DLOCK|HID0_DCFI 1098 andc r3, r3, r5 /* no invalidate, unlock */ 1099 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1100 sync 1101 mtspr HID0, r5 /* invalidate, unlock */ 1102 sync 1103 mtspr HID0, r3 /* no invalidate, unlock */ 1104 blr 1105#endif /* !MINIMAL_SPL */ 1106#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1107 1108#ifdef CONFIG_SYS_FLASHBOOT 1109map_flash_by_law1: 1110 /* When booting from ROM (Flash or EPROM), clear the */ 1111 /* Address Mask in OR0 so ROM appears everywhere */ 1112 /*----------------------------------------------------*/ 1113 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1114 lwz r4, OR0@l(r3) 1115 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1116 and r4, r4, r5 1117 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1118 1119 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1120 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1121 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1122 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1123 * 0xFF800. From the hard resetting to here, the processor fetched and 1124 * executed the instructions one by one. There is not absolutely 1125 * jumping happened. Laterly, the u-boot code has to do an absolutely 1126 * jumping to tell the CPU instruction fetching component what the 1127 * u-boot TEXT base address is. Because the TEXT base resides in the 1128 * boot ROM memory space, to garantee the code can run smoothly after 1129 * that jumping, we must map in the entire boot ROM by Local Access 1130 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1131 * address for boot ROM, such as 0xFE000000. In this case, the default 1132 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1133 * need another window to map in it. 1134 */ 1135 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1136 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1137 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1138 1139 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1140 lis r4, (0x80000012)@h 1141 ori r4, r4, (0x80000012)@l 1142 li r5, CONFIG_SYS_FLASH_SIZE 11431: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1144 addi r4, r4, 1 1145 bne 1b 1146 1147 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1148 /* Wait for HW to catch up */ 1149 lwz r4, LBLAWAR1(r3) 1150 twi 0,r4,0 1151 isync 1152 blr 1153 1154 /* Though all the LBIU Local Access Windows and LBC Banks will be 1155 * initialized in the C code, we'd better configure boot ROM's 1156 * window 0 and bank 0 correctly at here. 1157 */ 1158remap_flash_by_law0: 1159 /* Initialize the BR0 with the boot ROM starting address. */ 1160 lwz r4, BR0(r3) 1161 li r5, 0x7FFF 1162 and r4, r4, r5 1163 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1164 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1165 or r5, r5, r4 1166 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1167 1168 lwz r4, OR0(r3) 1169 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1170 or r4, r4, r5 1171 stw r4, OR0(r3) 1172 1173 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1174 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1175 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1176 1177 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1178 lis r4, (0x80000012)@h 1179 ori r4, r4, (0x80000012)@l 1180 li r5, CONFIG_SYS_FLASH_SIZE 11811: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1182 addi r4, r4, 1 1183 bne 1b 1184 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1185 1186 1187 xor r4, r4, r4 1188 stw r4, LBLAWBAR1(r3) 1189 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1190 /* Wait for HW to catch up */ 1191 lwz r4, LBLAWAR1(r3) 1192 twi 0,r4,0 1193 isync 1194 blr 1195#endif /* CONFIG_SYS_FLASHBOOT */ 1196