1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 28 */ 29 30#include <config.h> 31#include <mpc83xx.h> 32#include <timestamp.h> 33#include <version.h> 34 35#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43 44#ifndef CONFIG_IDENT_STRING 45#define CONFIG_IDENT_STRING "MPC83XX" 46#endif 47 48/* We don't want the MMU yet. 49 */ 50#undef MSR_KERNEL 51 52/* 53 * Floating Point enable, Machine Check and Recoverable Interr. 54 */ 55#ifdef DEBUG 56#define MSR_KERNEL (MSR_FP|MSR_RI) 57#else 58#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 59#endif 60 61#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) 62#define CONFIG_SYS_FLASHBOOT 63#endif 64 65/* 66 * Set up GOT: Global Offset Table 67 * 68 * Use r12 to access the GOT 69 */ 70 START_GOT 71 GOT_ENTRY(_GOT2_TABLE_) 72 GOT_ENTRY(__bss_start) 73 GOT_ENTRY(_end) 74 75#ifndef CONFIG_NAND_SPL 76 GOT_ENTRY(_FIXUP_TABLE_) 77 GOT_ENTRY(_start) 78 GOT_ENTRY(_start_of_vectors) 79 GOT_ENTRY(_end_of_vectors) 80 GOT_ENTRY(transfer_to_handler) 81#endif 82 END_GOT 83 84/* 85 * The Hard Reset Configuration Word (HRCW) table is in the first 64 86 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 87 * times so the processor can fetch it out of flash whether the flash 88 * is 8, 16, 32, or 64 bits wide (hardware trickery). 89 */ 90 .text 91#define _HRCW_TABLE_ENTRY(w) \ 92 .fill 8,1,(((w)>>24)&0xff); \ 93 .fill 8,1,(((w)>>16)&0xff); \ 94 .fill 8,1,(((w)>> 8)&0xff); \ 95 .fill 8,1,(((w) )&0xff) 96 97 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 98 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 99 100/* 101 * Magic number and version string - put it after the HRCW since it 102 * cannot be first in flash like it is in many other processors. 103 */ 104 .long 0x27051956 /* U-Boot Magic Number */ 105 106 .globl version_string 107version_string: 108 .ascii U_BOOT_VERSION 109 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 110 .ascii " ", CONFIG_IDENT_STRING, "\0" 111 112 .align 2 113 114 .globl enable_addr_trans 115enable_addr_trans: 116 /* enable address translation */ 117 mfmsr r5 118 ori r5, r5, (MSR_IR | MSR_DR) 119 mtmsr r5 120 isync 121 blr 122 123 .globl disable_addr_trans 124disable_addr_trans: 125 /* disable address translation */ 126 mflr r4 127 mfmsr r3 128 andi. r0, r3, (MSR_IR | MSR_DR) 129 beqlr 130 andc r3, r3, r0 131 mtspr SRR0, r4 132 mtspr SRR1, r3 133 rfi 134 135 .globl get_pvr 136get_pvr: 137 mfspr r3, PVR 138 blr 139 140 .globl ppcDWstore 141ppcDWstore: 142 lfd 1, 0(r4) 143 stfd 1, 0(r3) 144 blr 145 146 .globl ppcDWload 147ppcDWload: 148 lfd 1, 0(r3) 149 stfd 1, 0(r4) 150 blr 151 152#ifndef CONFIG_DEFAULT_IMMR 153#error CONFIG_DEFAULT_IMMR must be defined 154#endif /* CONFIG_SYS_DEFAULT_IMMR */ 155#ifndef CONFIG_SYS_IMMR 156#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 157#endif /* CONFIG_SYS_IMMR */ 158 159/* 160 * After configuration, a system reset exception is executed using the 161 * vector at offset 0x100 relative to the base set by MSR[IP]. If 162 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 163 * base address is 0xfff00000. In the case of a Power On Reset or Hard 164 * Reset, the value of MSR[IP] is determined by the CIP field in the 165 * HRCW. 166 * 167 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 168 * This determines the location of the boot ROM (flash or EPROM) in the 169 * processor's address space at boot time. As long as the HRCW is set up 170 * so that we eventually end up executing the code below when the 171 * processor executes the reset exception, the actual values used should 172 * not matter. 173 * 174 * Once we have got here, the address mask in OR0 is cleared so that the 175 * bottom 32K of the boot ROM is effectively repeated all throughout the 176 * processor's address space, after which we can jump to the absolute 177 * address at which the boot ROM was linked at compile time, and proceed 178 * to initialise the memory controller without worrying if the rug will 179 * be pulled out from under us, so to speak (it will be fine as long as 180 * we configure BR0 with the same boot ROM link address). 181 */ 182 . = EXC_OFF_SYS_RESET 183 184 .globl _start 185_start: /* time t 0 */ 186 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/ 187 nop 188 b boot_cold 189 190 . = EXC_OFF_SYS_RESET + 0x10 191 192 .globl _start_warm 193_start_warm: 194 li r21, BOOTFLAG_WARM /* Software reboot */ 195 b boot_warm 196 197 198boot_cold: /* time t 3 */ 199 lis r4, CONFIG_DEFAULT_IMMR@h 200 nop 201boot_warm: /* time t 5 */ 202 mfmsr r5 /* save msr contents */ 203 204 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 205 bl 1f 2061: mflr r7 207 208 lis r3, CONFIG_SYS_IMMR@h 209 ori r3, r3, CONFIG_SYS_IMMR@l 210 211 lwz r6, IMMRBAR(r4) 212 isync 213 214 stw r3, IMMRBAR(r4) 215 lwz r6, 0(r7) /* Arbitrary external load */ 216 isync 217 218 lwz r6, IMMRBAR(r3) 219 isync 220 221 /* Initialise the E300 processor core */ 222 /*------------------------------------------*/ 223 224#ifdef CONFIG_NAND_SPL 225 /* The FCM begins execution after only the first page 226 * is loaded. Wait for the rest before branching 227 * to another flash page. 228 */ 2291: lwz r6, 0x50b0(r3) 230 andi. r6, r6, 1 231 beq 1b 232#endif 233 234 bl init_e300_core 235 236#ifdef CONFIG_SYS_FLASHBOOT 237 238 /* Inflate flash location so it appears everywhere, calculate */ 239 /* the absolute address in final location of the FLASH, jump */ 240 /* there and deflate the flash size back to minimal size */ 241 /*------------------------------------------------------------*/ 242 bl map_flash_by_law1 243 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 244 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 245 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 246 mtlr r5 247 blr 248in_flash: 249#if 1 /* Remapping flash with LAW0. */ 250 bl remap_flash_by_law0 251#endif 252#endif /* CONFIG_SYS_FLASHBOOT */ 253 254 /* setup the bats */ 255 bl setup_bats 256 sync 257 258 /* 259 * Cache must be enabled here for stack-in-cache trick. 260 * This means we need to enable the BATS. 261 * This means: 262 * 1) for the EVB, original gt regs need to be mapped 263 * 2) need to have an IBAT for the 0xf region, 264 * we are running there! 265 * Cache should be turned on after BATs, since by default 266 * everything is write-through. 267 * The init-mem BAT can be reused after reloc. The old 268 * gt-regs BAT can be reused after board_init_f calls 269 * board_early_init_f (EVB only). 270 */ 271 /* enable address translation */ 272 bl enable_addr_trans 273 sync 274 275 /* enable the data cache */ 276 bl dcache_enable 277 sync 278#ifdef CONFIG_SYS_INIT_RAM_LOCK 279 bl lock_ram_in_cache 280 sync 281#endif 282 283 /* set up the stack pointer in our newly created 284 * cache-ram (r1) */ 285 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 286 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 287 288 li r0, 0 /* Make room for stack frame header and */ 289 stwu r0, -4(r1) /* clear final stack frame so that */ 290 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 291 292 293 /* let the C-code set up the rest */ 294 /* */ 295 /* Be careful to keep code relocatable & stack humble */ 296 /*------------------------------------------------------*/ 297 298 GET_GOT /* initialize GOT access */ 299 300 /* r3: IMMR */ 301 lis r3, CONFIG_SYS_IMMR@h 302 /* run low-level CPU init code (in Flash)*/ 303 bl cpu_init_f 304 305 /* r3: BOOTFLAG */ 306 mr r3, r21 307 /* run 1st part of board init code (in Flash)*/ 308 bl board_init_f 309 310#ifndef CONFIG_NAND_SPL 311/* 312 * Vector Table 313 */ 314 315 .globl _start_of_vectors 316_start_of_vectors: 317 318/* Machine check */ 319 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 320 321/* Data Storage exception. */ 322 STD_EXCEPTION(0x300, DataStorage, UnknownException) 323 324/* Instruction Storage exception. */ 325 STD_EXCEPTION(0x400, InstStorage, UnknownException) 326 327/* External Interrupt exception. */ 328#ifndef FIXME 329 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 330#endif 331 332/* Alignment exception. */ 333 . = 0x600 334Alignment: 335 EXCEPTION_PROLOG(SRR0, SRR1) 336 mfspr r4,DAR 337 stw r4,_DAR(r21) 338 mfspr r5,DSISR 339 stw r5,_DSISR(r21) 340 addi r3,r1,STACK_FRAME_OVERHEAD 341 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 342 343/* Program check exception */ 344 . = 0x700 345ProgramCheck: 346 EXCEPTION_PROLOG(SRR0, SRR1) 347 addi r3,r1,STACK_FRAME_OVERHEAD 348 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 349 MSR_KERNEL, COPY_EE) 350 351 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 352 353 /* I guess we could implement decrementer, and may have 354 * to someday for timekeeping. 355 */ 356 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 357 358 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 359 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 360 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 361 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 362 363 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 364 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 365 366 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 367 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 368 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 369#ifdef DEBUG 370 . = 0x1300 371 /* 372 * This exception occurs when the program counter matches the 373 * Instruction Address Breakpoint Register (IABR). 374 * 375 * I want the cpu to halt if this occurs so I can hunt around 376 * with the debugger and look at things. 377 * 378 * When DEBUG is defined, both machine check enable (in the MSR) 379 * and checkstop reset enable (in the reset mode register) are 380 * turned off and so a checkstop condition will result in the cpu 381 * halting. 382 * 383 * I force the cpu into a checkstop condition by putting an illegal 384 * instruction here (at least this is the theory). 385 * 386 * well - that didnt work, so just do an infinite loop! 387 */ 3881: b 1b 389#else 390 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 391#endif 392 STD_EXCEPTION(0x1400, SMI, UnknownException) 393 394 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 395 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 396 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 397 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 398 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 399 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 400 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 401 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 402 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 403 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 404 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 405 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 406 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 407 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 408 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 409 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 410 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 411 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 412 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 413 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 414 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 415 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 416 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 417 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 418 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 419 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 420 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 421 422 423 .globl _end_of_vectors 424_end_of_vectors: 425 426 . = 0x3000 427 428/* 429 * This code finishes saving the registers to the exception frame 430 * and jumps to the appropriate handler for the exception. 431 * Register r21 is pointer into trap frame, r1 has new stack pointer. 432 */ 433 .globl transfer_to_handler 434transfer_to_handler: 435 stw r22,_NIP(r21) 436 lis r22,MSR_POW@h 437 andc r23,r23,r22 438 stw r23,_MSR(r21) 439 SAVE_GPR(7, r21) 440 SAVE_4GPRS(8, r21) 441 SAVE_8GPRS(12, r21) 442 SAVE_8GPRS(24, r21) 443 mflr r23 444 andi. r24,r23,0x3f00 /* get vector offset */ 445 stw r24,TRAP(r21) 446 li r22,0 447 stw r22,RESULT(r21) 448 lwz r24,0(r23) /* virtual address of handler */ 449 lwz r23,4(r23) /* where to go when done */ 450 mtspr SRR0,r24 451 mtspr SRR1,r20 452 mtlr r23 453 SYNC 454 rfi /* jump to handler, enable MMU */ 455 456int_return: 457 mfmsr r28 /* Disable interrupts */ 458 li r4,0 459 ori r4,r4,MSR_EE 460 andc r28,r28,r4 461 SYNC /* Some chip revs need this... */ 462 mtmsr r28 463 SYNC 464 lwz r2,_CTR(r1) 465 lwz r0,_LINK(r1) 466 mtctr r2 467 mtlr r0 468 lwz r2,_XER(r1) 469 lwz r0,_CCR(r1) 470 mtspr XER,r2 471 mtcrf 0xFF,r0 472 REST_10GPRS(3, r1) 473 REST_10GPRS(13, r1) 474 REST_8GPRS(23, r1) 475 REST_GPR(31, r1) 476 lwz r2,_NIP(r1) /* Restore environment */ 477 lwz r0,_MSR(r1) 478 mtspr SRR0,r2 479 mtspr SRR1,r0 480 lwz r0,GPR0(r1) 481 lwz r2,GPR2(r1) 482 lwz r1,GPR1(r1) 483 SYNC 484 rfi 485#endif /* !CONFIG_NAND_SPL */ 486 487/* 488 * This code initialises the E300 processor core 489 * (conforms to PowerPC 603e spec) 490 * Note: expects original MSR contents to be in r5. 491 */ 492 .globl init_e300_core 493init_e300_core: /* time t 10 */ 494 /* Initialize machine status; enable machine check interrupt */ 495 /*-----------------------------------------------------------*/ 496 497 li r3, MSR_KERNEL /* Set ME and RI flags */ 498 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 499#ifdef DEBUG 500 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 501#endif 502 SYNC /* Some chip revs need this... */ 503 mtmsr r3 504 SYNC 505 mtspr SRR1, r3 /* Make SRR1 match MSR */ 506 507 508 lis r3, CONFIG_SYS_IMMR@h 509#if defined(CONFIG_WATCHDOG) 510 /* Initialise the Watchdog values and reset it (if req) */ 511 /*------------------------------------------------------*/ 512 lis r4, CONFIG_SYS_WATCHDOG_VALUE 513 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 514 stw r4, SWCRR(r3) 515 516 /* and reset it */ 517 518 li r4, 0x556C 519 sth r4, SWSRR@l(r3) 520 li r4, -0x55C7 521 sth r4, SWSRR@l(r3) 522#else 523 /* Disable Watchdog */ 524 /*-------------------*/ 525 lwz r4, SWCRR(r3) 526 /* Check to see if its enabled for disabling 527 once disabled by SW you can't re-enable */ 528 andi. r4, r4, 0x4 529 beq 1f 530 xor r4, r4, r4 531 stw r4, SWCRR(r3) 5321: 533#endif /* CONFIG_WATCHDOG */ 534 535#if defined(CONFIG_MASK_AER_AO) 536 /* Write the Arbiter Event Enable to mask Address Only traps. */ 537 /* This prevents the dcbz instruction from being trapped when */ 538 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 539 /* COHERENCY bit is set in the WIMG bits, which is often */ 540 /* needed for PCI operation. */ 541 lwz r4, 0x0808(r3) 542 rlwinm r0, r4, 0, ~AER_AO 543 stw r0, 0x0808(r3) 544#endif /* CONFIG_MASK_AER_AO */ 545 546 /* Initialize the Hardware Implementation-dependent Registers */ 547 /* HID0 also contains cache control */ 548 /* - force invalidation of data and instruction caches */ 549 /*------------------------------------------------------*/ 550 551 lis r3, CONFIG_SYS_HID0_INIT@h 552 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 553 SYNC 554 mtspr HID0, r3 555 556 lis r3, CONFIG_SYS_HID0_FINAL@h 557 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 558 SYNC 559 mtspr HID0, r3 560 561 lis r3, CONFIG_SYS_HID2@h 562 ori r3, r3, CONFIG_SYS_HID2@l 563 SYNC 564 mtspr HID2, r3 565 566 /* Done! */ 567 /*------------------------------*/ 568 blr 569 570 /* setup_bats - set them up to some initial state */ 571 .globl setup_bats 572setup_bats: 573 addis r0, r0, 0x0000 574 575 /* IBAT 0 */ 576 addis r4, r0, CONFIG_SYS_IBAT0L@h 577 ori r4, r4, CONFIG_SYS_IBAT0L@l 578 addis r3, r0, CONFIG_SYS_IBAT0U@h 579 ori r3, r3, CONFIG_SYS_IBAT0U@l 580 mtspr IBAT0L, r4 581 mtspr IBAT0U, r3 582 583 /* DBAT 0 */ 584 addis r4, r0, CONFIG_SYS_DBAT0L@h 585 ori r4, r4, CONFIG_SYS_DBAT0L@l 586 addis r3, r0, CONFIG_SYS_DBAT0U@h 587 ori r3, r3, CONFIG_SYS_DBAT0U@l 588 mtspr DBAT0L, r4 589 mtspr DBAT0U, r3 590 591 /* IBAT 1 */ 592 addis r4, r0, CONFIG_SYS_IBAT1L@h 593 ori r4, r4, CONFIG_SYS_IBAT1L@l 594 addis r3, r0, CONFIG_SYS_IBAT1U@h 595 ori r3, r3, CONFIG_SYS_IBAT1U@l 596 mtspr IBAT1L, r4 597 mtspr IBAT1U, r3 598 599 /* DBAT 1 */ 600 addis r4, r0, CONFIG_SYS_DBAT1L@h 601 ori r4, r4, CONFIG_SYS_DBAT1L@l 602 addis r3, r0, CONFIG_SYS_DBAT1U@h 603 ori r3, r3, CONFIG_SYS_DBAT1U@l 604 mtspr DBAT1L, r4 605 mtspr DBAT1U, r3 606 607 /* IBAT 2 */ 608 addis r4, r0, CONFIG_SYS_IBAT2L@h 609 ori r4, r4, CONFIG_SYS_IBAT2L@l 610 addis r3, r0, CONFIG_SYS_IBAT2U@h 611 ori r3, r3, CONFIG_SYS_IBAT2U@l 612 mtspr IBAT2L, r4 613 mtspr IBAT2U, r3 614 615 /* DBAT 2 */ 616 addis r4, r0, CONFIG_SYS_DBAT2L@h 617 ori r4, r4, CONFIG_SYS_DBAT2L@l 618 addis r3, r0, CONFIG_SYS_DBAT2U@h 619 ori r3, r3, CONFIG_SYS_DBAT2U@l 620 mtspr DBAT2L, r4 621 mtspr DBAT2U, r3 622 623 /* IBAT 3 */ 624 addis r4, r0, CONFIG_SYS_IBAT3L@h 625 ori r4, r4, CONFIG_SYS_IBAT3L@l 626 addis r3, r0, CONFIG_SYS_IBAT3U@h 627 ori r3, r3, CONFIG_SYS_IBAT3U@l 628 mtspr IBAT3L, r4 629 mtspr IBAT3U, r3 630 631 /* DBAT 3 */ 632 addis r4, r0, CONFIG_SYS_DBAT3L@h 633 ori r4, r4, CONFIG_SYS_DBAT3L@l 634 addis r3, r0, CONFIG_SYS_DBAT3U@h 635 ori r3, r3, CONFIG_SYS_DBAT3U@l 636 mtspr DBAT3L, r4 637 mtspr DBAT3U, r3 638 639#ifdef CONFIG_HIGH_BATS 640 /* IBAT 4 */ 641 addis r4, r0, CONFIG_SYS_IBAT4L@h 642 ori r4, r4, CONFIG_SYS_IBAT4L@l 643 addis r3, r0, CONFIG_SYS_IBAT4U@h 644 ori r3, r3, CONFIG_SYS_IBAT4U@l 645 mtspr IBAT4L, r4 646 mtspr IBAT4U, r3 647 648 /* DBAT 4 */ 649 addis r4, r0, CONFIG_SYS_DBAT4L@h 650 ori r4, r4, CONFIG_SYS_DBAT4L@l 651 addis r3, r0, CONFIG_SYS_DBAT4U@h 652 ori r3, r3, CONFIG_SYS_DBAT4U@l 653 mtspr DBAT4L, r4 654 mtspr DBAT4U, r3 655 656 /* IBAT 5 */ 657 addis r4, r0, CONFIG_SYS_IBAT5L@h 658 ori r4, r4, CONFIG_SYS_IBAT5L@l 659 addis r3, r0, CONFIG_SYS_IBAT5U@h 660 ori r3, r3, CONFIG_SYS_IBAT5U@l 661 mtspr IBAT5L, r4 662 mtspr IBAT5U, r3 663 664 /* DBAT 5 */ 665 addis r4, r0, CONFIG_SYS_DBAT5L@h 666 ori r4, r4, CONFIG_SYS_DBAT5L@l 667 addis r3, r0, CONFIG_SYS_DBAT5U@h 668 ori r3, r3, CONFIG_SYS_DBAT5U@l 669 mtspr DBAT5L, r4 670 mtspr DBAT5U, r3 671 672 /* IBAT 6 */ 673 addis r4, r0, CONFIG_SYS_IBAT6L@h 674 ori r4, r4, CONFIG_SYS_IBAT6L@l 675 addis r3, r0, CONFIG_SYS_IBAT6U@h 676 ori r3, r3, CONFIG_SYS_IBAT6U@l 677 mtspr IBAT6L, r4 678 mtspr IBAT6U, r3 679 680 /* DBAT 6 */ 681 addis r4, r0, CONFIG_SYS_DBAT6L@h 682 ori r4, r4, CONFIG_SYS_DBAT6L@l 683 addis r3, r0, CONFIG_SYS_DBAT6U@h 684 ori r3, r3, CONFIG_SYS_DBAT6U@l 685 mtspr DBAT6L, r4 686 mtspr DBAT6U, r3 687 688 /* IBAT 7 */ 689 addis r4, r0, CONFIG_SYS_IBAT7L@h 690 ori r4, r4, CONFIG_SYS_IBAT7L@l 691 addis r3, r0, CONFIG_SYS_IBAT7U@h 692 ori r3, r3, CONFIG_SYS_IBAT7U@l 693 mtspr IBAT7L, r4 694 mtspr IBAT7U, r3 695 696 /* DBAT 7 */ 697 addis r4, r0, CONFIG_SYS_DBAT7L@h 698 ori r4, r4, CONFIG_SYS_DBAT7L@l 699 addis r3, r0, CONFIG_SYS_DBAT7U@h 700 ori r3, r3, CONFIG_SYS_DBAT7U@l 701 mtspr DBAT7L, r4 702 mtspr DBAT7U, r3 703#endif 704 705 isync 706 707 /* invalidate all tlb's 708 * 709 * From the 603e User Manual: "The 603e provides the ability to 710 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 711 * instruction invalidates the TLB entry indexed by the EA, and 712 * operates on both the instruction and data TLBs simultaneously 713 * invalidating four TLB entries (both sets in each TLB). The 714 * index corresponds to bits 15-19 of the EA. To invalidate all 715 * entries within both TLBs, 32 tlbie instructions should be 716 * issued, incrementing this field by one each time." 717 * 718 * "Note that the tlbia instruction is not implemented on the 719 * 603e." 720 * 721 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 722 * incrementing by 0x1000 each time. The code below is sort of 723 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 724 * 725 */ 726 lis r3, 0 727 lis r5, 2 728 7291: 730 tlbie r3 731 addi r3, r3, 0x1000 732 cmp 0, 0, r3, r5 733 blt 1b 734 735 blr 736 737/* Cache functions. 738 * 739 * Note: requires that all cache bits in 740 * HID0 are in the low half word. 741 */ 742#ifndef CONFIG_NAND_SPL 743 .globl icache_enable 744icache_enable: 745 mfspr r3, HID0 746 ori r3, r3, HID0_ICE 747 li r4, HID0_ICFI|HID0_ILOCK 748 andc r3, r3, r4 749 ori r4, r3, HID0_ICFI 750 isync 751 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 752 isync 753 mtspr HID0, r3 /* clears invalidate */ 754 blr 755 756 .globl icache_disable 757icache_disable: 758 mfspr r3, HID0 759 lis r4, 0 760 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 761 andc r3, r3, r4 762 isync 763 mtspr HID0, r3 /* clears invalidate, enable and lock */ 764 blr 765 766 .globl icache_status 767icache_status: 768 mfspr r3, HID0 769 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 770 blr 771#endif /* !CONFIG_NAND_SPL */ 772 773 .globl dcache_enable 774dcache_enable: 775 mfspr r3, HID0 776 li r5, HID0_DCFI|HID0_DLOCK 777 andc r3, r3, r5 778 ori r3, r3, HID0_DCE 779 sync 780 mtspr HID0, r3 /* enable, no invalidate */ 781 blr 782 783 .globl dcache_disable 784dcache_disable: 785 mflr r4 786 bl flush_dcache /* uses r3 and r5 */ 787 mfspr r3, HID0 788 li r5, HID0_DCE|HID0_DLOCK 789 andc r3, r3, r5 790 ori r5, r3, HID0_DCFI 791 sync 792 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 793 sync 794 mtspr HID0, r3 /* clears invalidate */ 795 mtlr r4 796 blr 797 798 .globl dcache_status 799dcache_status: 800 mfspr r3, HID0 801 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 802 blr 803 804 .globl flush_dcache 805flush_dcache: 806 lis r3, 0 807 lis r5, CONFIG_SYS_CACHELINE_SIZE 8081: cmp 0, 1, r3, r5 809 bge 2f 810 lwz r5, 0(r3) 811 lis r5, CONFIG_SYS_CACHELINE_SIZE 812 addi r3, r3, 0x4 813 b 1b 8142: blr 815 816/*-------------------------------------------------------------------*/ 817 818/* 819 * void relocate_code (addr_sp, gd, addr_moni) 820 * 821 * This "function" does not return, instead it continues in RAM 822 * after relocating the monitor code. 823 * 824 * r3 = dest 825 * r4 = src 826 * r5 = length in bytes 827 * r6 = cachelinesize 828 */ 829 .globl relocate_code 830relocate_code: 831 mr r1, r3 /* Set new stack pointer */ 832 mr r9, r4 /* Save copy of Global Data pointer */ 833 mr r10, r5 /* Save copy of Destination Address */ 834 835 GET_GOT 836 mr r3, r5 /* Destination Address */ 837 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 838 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 839 lwz r5, GOT(__bss_start) 840 sub r5, r5, r4 841 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 842 843 /* 844 * Fix GOT pointer: 845 * 846 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 847 * + Destination Address 848 * 849 * Offset: 850 */ 851 sub r15, r10, r4 852 853 /* First our own GOT */ 854 add r12, r12, r15 855 /* then the one used by the C code */ 856 add r30, r30, r15 857 858 /* 859 * Now relocate code 860 */ 861 862 cmplw cr1,r3,r4 863 addi r0,r5,3 864 srwi. r0,r0,2 865 beq cr1,4f /* In place copy is not necessary */ 866 beq 7f /* Protect against 0 count */ 867 mtctr r0 868 bge cr1,2f 869 la r8,-4(r4) 870 la r7,-4(r3) 871 872 /* copy */ 8731: lwzu r0,4(r8) 874 stwu r0,4(r7) 875 bdnz 1b 876 877 addi r0,r5,3 878 srwi. r0,r0,2 879 mtctr r0 880 la r8,-4(r4) 881 la r7,-4(r3) 882 883 /* and compare */ 88420: lwzu r20,4(r8) 885 lwzu r21,4(r7) 886 xor. r22, r20, r21 887 bne 30f 888 bdnz 20b 889 b 4f 890 891 /* compare failed */ 89230: li r3, 0 893 blr 894 8952: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 896 add r8,r4,r0 897 add r7,r3,r0 8983: lwzu r0,-4(r8) 899 stwu r0,-4(r7) 900 bdnz 3b 901 902/* 903 * Now flush the cache: note that we must start from a cache aligned 904 * address. Otherwise we might miss one cache line. 905 */ 9064: cmpwi r6,0 907 add r5,r3,r5 908 beq 7f /* Always flush prefetch queue in any case */ 909 subi r0,r6,1 910 andc r3,r3,r0 911 mr r4,r3 9125: dcbst 0,r4 913 add r4,r4,r6 914 cmplw r4,r5 915 blt 5b 916 sync /* Wait for all dcbst to complete on bus */ 917 mr r4,r3 9186: icbi 0,r4 919 add r4,r4,r6 920 cmplw r4,r5 921 blt 6b 9227: sync /* Wait for all icbi to complete on bus */ 923 isync 924 925/* 926 * We are done. Do not return, instead branch to second part of board 927 * initialization, now running from RAM. 928 */ 929 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 930 mtlr r0 931 blr 932 933in_ram: 934 935 /* 936 * Relocation Function, r12 point to got2+0x8000 937 * 938 * Adjust got2 pointers, no need to check for 0, this code 939 * already puts a few entries in the table. 940 */ 941 li r0,__got2_entries@sectoff@l 942 la r3,GOT(_GOT2_TABLE_) 943 lwz r11,GOT(_GOT2_TABLE_) 944 mtctr r0 945 sub r11,r3,r11 946 addi r3,r3,-4 9471: lwzu r0,4(r3) 948 cmpwi r0,0 949 beq- 2f 950 add r0,r0,r11 951 stw r0,0(r3) 9522: bdnz 1b 953 954#ifndef CONFIG_NAND_SPL 955 /* 956 * Now adjust the fixups and the pointers to the fixups 957 * in case we need to move ourselves again. 958 */ 959 li r0,__fixup_entries@sectoff@l 960 lwz r3,GOT(_FIXUP_TABLE_) 961 cmpwi r0,0 962 mtctr r0 963 addi r3,r3,-4 964 beq 4f 9653: lwzu r4,4(r3) 966 lwzux r0,r4,r11 967 add r0,r0,r11 968 stw r10,0(r3) 969 stw r0,0(r4) 970 bdnz 3b 9714: 972#endif 973 974clear_bss: 975 /* 976 * Now clear BSS segment 977 */ 978 lwz r3,GOT(__bss_start) 979#if defined(CONFIG_HYMOD) 980 /* 981 * For HYMOD - the environment is the very last item in flash. 982 * The real .bss stops just before environment starts, so only 983 * clear up to that point. 984 * 985 * taken from mods for FADS board 986 */ 987 lwz r4,GOT(environment) 988#else 989 lwz r4,GOT(_end) 990#endif 991 992 cmplw 0, r3, r4 993 beq 6f 994 995 li r0, 0 9965: 997 stw r0, 0(r3) 998 addi r3, r3, 4 999 cmplw 0, r3, r4 1000 bne 5b 10016: 1002 1003 mr r3, r9 /* Global Data pointer */ 1004 mr r4, r10 /* Destination Address */ 1005 bl board_init_r 1006 1007#ifndef CONFIG_NAND_SPL 1008 /* 1009 * Copy exception vector code to low memory 1010 * 1011 * r3: dest_addr 1012 * r7: source address, r8: end address, r9: target address 1013 */ 1014 .globl trap_init 1015trap_init: 1016 mflr r4 /* save link register */ 1017 GET_GOT 1018 lwz r7, GOT(_start) 1019 lwz r8, GOT(_end_of_vectors) 1020 1021 li r9, 0x100 /* reset vector always at 0x100 */ 1022 1023 cmplw 0, r7, r8 1024 bgelr /* return if r7>=r8 - just in case */ 10251: 1026 lwz r0, 0(r7) 1027 stw r0, 0(r9) 1028 addi r7, r7, 4 1029 addi r9, r9, 4 1030 cmplw 0, r7, r8 1031 bne 1b 1032 1033 /* 1034 * relocate `hdlr' and `int_return' entries 1035 */ 1036 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1037 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10382: 1039 bl trap_reloc 1040 addi r7, r7, 0x100 /* next exception vector */ 1041 cmplw 0, r7, r8 1042 blt 2b 1043 1044 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1045 bl trap_reloc 1046 1047 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1048 bl trap_reloc 1049 1050 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1051 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10523: 1053 bl trap_reloc 1054 addi r7, r7, 0x100 /* next exception vector */ 1055 cmplw 0, r7, r8 1056 blt 3b 1057 1058 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1059 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10604: 1061 bl trap_reloc 1062 addi r7, r7, 0x100 /* next exception vector */ 1063 cmplw 0, r7, r8 1064 blt 4b 1065 1066 mfmsr r3 /* now that the vectors have */ 1067 lis r7, MSR_IP@h /* relocated into low memory */ 1068 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1069 andc r3, r3, r7 /* (if it was on) */ 1070 SYNC /* Some chip revs need this... */ 1071 mtmsr r3 1072 SYNC 1073 1074 mtlr r4 /* restore link register */ 1075 blr 1076 1077#endif /* !CONFIG_NAND_SPL */ 1078 1079#ifdef CONFIG_SYS_INIT_RAM_LOCK 1080lock_ram_in_cache: 1081 /* Allocate Initial RAM in data cache. 1082 */ 1083 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1084 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1085 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 1086 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1087 mtctr r4 10881: 1089 dcbz r0, r3 1090 addi r3, r3, 32 1091 bdnz 1b 1092 1093 /* Lock the data cache */ 1094 mfspr r0, HID0 1095 ori r0, r0, HID0_DLOCK 1096 sync 1097 mtspr HID0, r0 1098 sync 1099 blr 1100 1101#ifndef CONFIG_NAND_SPL 1102.globl unlock_ram_in_cache 1103unlock_ram_in_cache: 1104 /* invalidate the INIT_RAM section */ 1105 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1106 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1107 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ 1108 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1109 mtctr r4 11101: icbi r0, r3 1111 dcbi r0, r3 1112 addi r3, r3, 32 1113 bdnz 1b 1114 sync /* Wait for all icbi to complete on bus */ 1115 isync 1116 1117 /* Unlock the data cache and invalidate it */ 1118 mfspr r3, HID0 1119 li r5, HID0_DLOCK|HID0_DCFI 1120 andc r3, r3, r5 /* no invalidate, unlock */ 1121 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1122 sync 1123 mtspr HID0, r5 /* invalidate, unlock */ 1124 sync 1125 mtspr HID0, r3 /* no invalidate, unlock */ 1126 blr 1127#endif /* !CONFIG_NAND_SPL */ 1128#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1129 1130#ifdef CONFIG_SYS_FLASHBOOT 1131map_flash_by_law1: 1132 /* When booting from ROM (Flash or EPROM), clear the */ 1133 /* Address Mask in OR0 so ROM appears everywhere */ 1134 /*----------------------------------------------------*/ 1135 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1136 lwz r4, OR0@l(r3) 1137 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1138 and r4, r4, r5 1139 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1140 1141 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1142 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1143 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1144 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1145 * 0xFF800. From the hard resetting to here, the processor fetched and 1146 * executed the instructions one by one. There is not absolutely 1147 * jumping happened. Laterly, the u-boot code has to do an absolutely 1148 * jumping to tell the CPU instruction fetching component what the 1149 * u-boot TEXT base address is. Because the TEXT base resides in the 1150 * boot ROM memory space, to garantee the code can run smoothly after 1151 * that jumping, we must map in the entire boot ROM by Local Access 1152 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1153 * address for boot ROM, such as 0xFE000000. In this case, the default 1154 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1155 * need another window to map in it. 1156 */ 1157 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1158 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1159 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1160 1161 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1162 lis r4, (0x80000012)@h 1163 ori r4, r4, (0x80000012)@l 1164 li r5, CONFIG_SYS_FLASH_SIZE 11651: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1166 addi r4, r4, 1 1167 bne 1b 1168 1169 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1170 blr 1171 1172 /* Though all the LBIU Local Access Windows and LBC Banks will be 1173 * initialized in the C code, we'd better configure boot ROM's 1174 * window 0 and bank 0 correctly at here. 1175 */ 1176remap_flash_by_law0: 1177 /* Initialize the BR0 with the boot ROM starting address. */ 1178 lwz r4, BR0(r3) 1179 li r5, 0x7FFF 1180 and r4, r4, r5 1181 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1182 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1183 or r5, r5, r4 1184 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1185 1186 lwz r4, OR0(r3) 1187 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1188 or r4, r4, r5 1189 stw r4, OR0(r3) 1190 1191 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1192 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1193 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1194 1195 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1196 lis r4, (0x80000012)@h 1197 ori r4, r4, (0x80000012)@l 1198 li r5, CONFIG_SYS_FLASH_SIZE 11991: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1200 addi r4, r4, 1 1201 bne 1b 1202 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1203 1204 1205 xor r4, r4, r4 1206 stw r4, LBLAWBAR1(r3) 1207 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1208 blr 1209#endif /* CONFIG_SYS_FLASHBOOT */ 1210