1/* 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 12 */ 13 14#include <asm-offsets.h> 15#include <config.h> 16#include <mpc83xx.h> 17#include <version.h> 18 19#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 20 21#include <ppc_asm.tmpl> 22#include <ppc_defs.h> 23 24#include <asm/cache.h> 25#include <asm/mmu.h> 26#include <asm/u-boot.h> 27 28/* We don't want the MMU yet. 29 */ 30#undef MSR_KERNEL 31 32/* 33 * Floating Point enable, Machine Check and Recoverable Interr. 34 */ 35#ifdef DEBUG 36#define MSR_KERNEL (MSR_FP|MSR_RI) 37#else 38#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 39#endif 40 41#if defined(CONFIG_NAND_SPL) || \ 42 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 43#define MINIMAL_SPL 44#endif 45 46#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 47 !defined(CONFIG_SYS_RAMBOOT) 48#define CONFIG_SYS_FLASHBOOT 49#endif 50 51/* 52 * Set up GOT: Global Offset Table 53 * 54 * Use r12 to access the GOT 55 */ 56 START_GOT 57 GOT_ENTRY(_GOT2_TABLE_) 58 GOT_ENTRY(__bss_start) 59 GOT_ENTRY(__bss_end) 60 61#ifndef MINIMAL_SPL 62 GOT_ENTRY(_FIXUP_TABLE_) 63 GOT_ENTRY(_start) 64 GOT_ENTRY(_start_of_vectors) 65 GOT_ENTRY(_end_of_vectors) 66 GOT_ENTRY(transfer_to_handler) 67#endif 68 END_GOT 69 70/* 71 * The Hard Reset Configuration Word (HRCW) table is in the first 64 72 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 73 * times so the processor can fetch it out of flash whether the flash 74 * is 8, 16, 32, or 64 bits wide (hardware trickery). 75 */ 76 .text 77#define _HRCW_TABLE_ENTRY(w) \ 78 .fill 8,1,(((w)>>24)&0xff); \ 79 .fill 8,1,(((w)>>16)&0xff); \ 80 .fill 8,1,(((w)>> 8)&0xff); \ 81 .fill 8,1,(((w) )&0xff) 82 83 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 84 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 85 86/* 87 * Magic number and version string - put it after the HRCW since it 88 * cannot be first in flash like it is in many other processors. 89 */ 90 .long 0x27051956 /* U-Boot Magic Number */ 91 92 .globl version_string 93version_string: 94 .ascii U_BOOT_VERSION_STRING, "\0" 95 96 .align 2 97 98 .globl enable_addr_trans 99enable_addr_trans: 100 /* enable address translation */ 101 mfmsr r5 102 ori r5, r5, (MSR_IR | MSR_DR) 103 mtmsr r5 104 isync 105 blr 106 107 .globl disable_addr_trans 108disable_addr_trans: 109 /* disable address translation */ 110 mflr r4 111 mfmsr r3 112 andi. r0, r3, (MSR_IR | MSR_DR) 113 beqlr 114 andc r3, r3, r0 115 mtspr SRR0, r4 116 mtspr SRR1, r3 117 rfi 118 119 .globl get_svr 120get_svr: 121 mfspr r3, SVR 122 blr 123 124 .globl get_pvr 125get_pvr: 126 mfspr r3, PVR 127 blr 128 129 .globl ppcDWstore 130ppcDWstore: 131 lfd 1, 0(r4) 132 stfd 1, 0(r3) 133 blr 134 135 .globl ppcDWload 136ppcDWload: 137 lfd 1, 0(r3) 138 stfd 1, 0(r4) 139 blr 140 141#ifndef CONFIG_DEFAULT_IMMR 142#error CONFIG_DEFAULT_IMMR must be defined 143#endif /* CONFIG_DEFAULT_IMMR */ 144#ifndef CONFIG_SYS_IMMR 145#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 146#endif /* CONFIG_SYS_IMMR */ 147 148/* 149 * After configuration, a system reset exception is executed using the 150 * vector at offset 0x100 relative to the base set by MSR[IP]. If 151 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 152 * base address is 0xfff00000. In the case of a Power On Reset or Hard 153 * Reset, the value of MSR[IP] is determined by the CIP field in the 154 * HRCW. 155 * 156 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 157 * This determines the location of the boot ROM (flash or EPROM) in the 158 * processor's address space at boot time. As long as the HRCW is set up 159 * so that we eventually end up executing the code below when the 160 * processor executes the reset exception, the actual values used should 161 * not matter. 162 * 163 * Once we have got here, the address mask in OR0 is cleared so that the 164 * bottom 32K of the boot ROM is effectively repeated all throughout the 165 * processor's address space, after which we can jump to the absolute 166 * address at which the boot ROM was linked at compile time, and proceed 167 * to initialise the memory controller without worrying if the rug will 168 * be pulled out from under us, so to speak (it will be fine as long as 169 * we configure BR0 with the same boot ROM link address). 170 */ 171 . = EXC_OFF_SYS_RESET 172 173 .globl _start 174_start: /* time t 0 */ 175 lis r4, CONFIG_DEFAULT_IMMR@h 176 nop 177 178 mfmsr r5 /* save msr contents */ 179 180 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 181 bl 1f 1821: mflr r7 183 184 lis r3, CONFIG_SYS_IMMR@h 185 ori r3, r3, CONFIG_SYS_IMMR@l 186 187 lwz r6, IMMRBAR(r4) 188 isync 189 190 stw r3, IMMRBAR(r4) 191 lwz r6, 0(r7) /* Arbitrary external load */ 192 isync 193 194 lwz r6, IMMRBAR(r3) 195 isync 196 197 /* Initialise the E300 processor core */ 198 /*------------------------------------------*/ 199 200#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 201 defined(CONFIG_NAND_SPL) 202 /* The FCM begins execution after only the first page 203 * is loaded. Wait for the rest before branching 204 * to another flash page. 205 */ 2061: lwz r6, 0x50b0(r3) 207 andi. r6, r6, 1 208 beq 1b 209#endif 210 211 bl init_e300_core 212 213#ifdef CONFIG_SYS_FLASHBOOT 214 215 /* Inflate flash location so it appears everywhere, calculate */ 216 /* the absolute address in final location of the FLASH, jump */ 217 /* there and deflate the flash size back to minimal size */ 218 /*------------------------------------------------------------*/ 219 bl map_flash_by_law1 220 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 221 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 222 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 223 mtlr r5 224 blr 225in_flash: 226#if 1 /* Remapping flash with LAW0. */ 227 bl remap_flash_by_law0 228#endif 229#endif /* CONFIG_SYS_FLASHBOOT */ 230 231 /* setup the bats */ 232 bl setup_bats 233 sync 234 235 /* 236 * Cache must be enabled here for stack-in-cache trick. 237 * This means we need to enable the BATS. 238 * This means: 239 * 1) for the EVB, original gt regs need to be mapped 240 * 2) need to have an IBAT for the 0xf region, 241 * we are running there! 242 * Cache should be turned on after BATs, since by default 243 * everything is write-through. 244 * The init-mem BAT can be reused after reloc. The old 245 * gt-regs BAT can be reused after board_init_f calls 246 * board_early_init_f (EVB only). 247 */ 248 /* enable address translation */ 249 bl enable_addr_trans 250 sync 251 252 /* enable the data cache */ 253 bl dcache_enable 254 sync 255#ifdef CONFIG_SYS_INIT_RAM_LOCK 256 bl lock_ram_in_cache 257 sync 258#endif 259 260 /* set up the stack pointer in our newly created 261 * cache-ram; use r3 to keep the new SP for now to 262 * avoid overiding the SP it uselessly */ 263 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 264 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 265 266 /* r4 = end of GD area */ 267 addi r4, r3, GENERATED_GBL_DATA_SIZE 268 269 /* Zero GD area */ 270 li r0, 0 2711: 272 subi r4, r4, 1 273 stb r0, 0(r4) 274 cmplw r3, r4 275 bne 1b 276 277#ifdef CONFIG_SYS_MALLOC_F_LEN 278 279#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE 280#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." 281#endif 282 283 /* r3 = new stack pointer / pre-reloc malloc area */ 284 subi r3, r3, CONFIG_SYS_MALLOC_F_LEN 285 286 /* Set pointer to pre-reloc malloc area in GD */ 287 stw r3, GD_MALLOC_BASE(r4) 288#endif 289 li r0, 0 /* Make room for stack frame header and */ 290 stwu r0, -4(r3) /* clear final stack frame so that */ 291 stwu r0, -4(r3) /* stack backtraces terminate cleanly */ 292 293 /* Finally, actually set SP */ 294 mr r1, r3 295 296 /* let the C-code set up the rest */ 297 /* */ 298 /* Be careful to keep code relocatable & stack humble */ 299 /*------------------------------------------------------*/ 300 301 GET_GOT /* initialize GOT access */ 302 303 /* r3: IMMR */ 304 lis r3, CONFIG_SYS_IMMR@h 305 /* run low-level CPU init code (in Flash)*/ 306 bl cpu_init_f 307 308 /* run 1st part of board init code (in Flash)*/ 309 li r3, 0 /* clear boot_flag for calling board_init_f */ 310 bl board_init_f 311 312 /* NOTREACHED - board_init_f() does not return */ 313 314#ifndef MINIMAL_SPL 315/* 316 * Vector Table 317 */ 318 319 .globl _start_of_vectors 320_start_of_vectors: 321 322/* Machine check */ 323 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 324 325/* Data Storage exception. */ 326 STD_EXCEPTION(0x300, DataStorage, UnknownException) 327 328/* Instruction Storage exception. */ 329 STD_EXCEPTION(0x400, InstStorage, UnknownException) 330 331/* External Interrupt exception. */ 332#ifndef FIXME 333 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 334#endif 335 336/* Alignment exception. */ 337 . = 0x600 338Alignment: 339 EXCEPTION_PROLOG(SRR0, SRR1) 340 mfspr r4,DAR 341 stw r4,_DAR(r21) 342 mfspr r5,DSISR 343 stw r5,_DSISR(r21) 344 addi r3,r1,STACK_FRAME_OVERHEAD 345 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 346 347/* Program check exception */ 348 . = 0x700 349ProgramCheck: 350 EXCEPTION_PROLOG(SRR0, SRR1) 351 addi r3,r1,STACK_FRAME_OVERHEAD 352 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 353 MSR_KERNEL, COPY_EE) 354 355 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 356 357 /* I guess we could implement decrementer, and may have 358 * to someday for timekeeping. 359 */ 360 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 361 362 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 363 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 364 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 365 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 366 367 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 368 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 369 370 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 371 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 372 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 373#ifdef DEBUG 374 . = 0x1300 375 /* 376 * This exception occurs when the program counter matches the 377 * Instruction Address Breakpoint Register (IABR). 378 * 379 * I want the cpu to halt if this occurs so I can hunt around 380 * with the debugger and look at things. 381 * 382 * When DEBUG is defined, both machine check enable (in the MSR) 383 * and checkstop reset enable (in the reset mode register) are 384 * turned off and so a checkstop condition will result in the cpu 385 * halting. 386 * 387 * I force the cpu into a checkstop condition by putting an illegal 388 * instruction here (at least this is the theory). 389 * 390 * well - that didnt work, so just do an infinite loop! 391 */ 3921: b 1b 393#else 394 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 395#endif 396 STD_EXCEPTION(0x1400, SMI, UnknownException) 397 398 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 399 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 400 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 401 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 402 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 403 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 404 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 405 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 406 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 407 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 408 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 409 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 410 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 411 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 412 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 413 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 414 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 415 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 416 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 417 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 418 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 419 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 420 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 421 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 422 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 423 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 424 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 425 426 427 .globl _end_of_vectors 428_end_of_vectors: 429 430 . = 0x3000 431 432/* 433 * This code finishes saving the registers to the exception frame 434 * and jumps to the appropriate handler for the exception. 435 * Register r21 is pointer into trap frame, r1 has new stack pointer. 436 */ 437 .globl transfer_to_handler 438transfer_to_handler: 439 stw r22,_NIP(r21) 440 lis r22,MSR_POW@h 441 andc r23,r23,r22 442 stw r23,_MSR(r21) 443 SAVE_GPR(7, r21) 444 SAVE_4GPRS(8, r21) 445 SAVE_8GPRS(12, r21) 446 SAVE_8GPRS(24, r21) 447 mflr r23 448 andi. r24,r23,0x3f00 /* get vector offset */ 449 stw r24,TRAP(r21) 450 li r22,0 451 stw r22,RESULT(r21) 452 lwz r24,0(r23) /* virtual address of handler */ 453 lwz r23,4(r23) /* where to go when done */ 454 mtspr SRR0,r24 455 mtspr SRR1,r20 456 mtlr r23 457 SYNC 458 rfi /* jump to handler, enable MMU */ 459 460int_return: 461 mfmsr r28 /* Disable interrupts */ 462 li r4,0 463 ori r4,r4,MSR_EE 464 andc r28,r28,r4 465 SYNC /* Some chip revs need this... */ 466 mtmsr r28 467 SYNC 468 lwz r2,_CTR(r1) 469 lwz r0,_LINK(r1) 470 mtctr r2 471 mtlr r0 472 lwz r2,_XER(r1) 473 lwz r0,_CCR(r1) 474 mtspr XER,r2 475 mtcrf 0xFF,r0 476 REST_10GPRS(3, r1) 477 REST_10GPRS(13, r1) 478 REST_8GPRS(23, r1) 479 REST_GPR(31, r1) 480 lwz r2,_NIP(r1) /* Restore environment */ 481 lwz r0,_MSR(r1) 482 mtspr SRR0,r2 483 mtspr SRR1,r0 484 lwz r0,GPR0(r1) 485 lwz r2,GPR2(r1) 486 lwz r1,GPR1(r1) 487 SYNC 488 rfi 489#endif /* !MINIMAL_SPL */ 490 491/* 492 * This code initialises the E300 processor core 493 * (conforms to PowerPC 603e spec) 494 * Note: expects original MSR contents to be in r5. 495 */ 496 .globl init_e300_core 497init_e300_core: /* time t 10 */ 498 /* Initialize machine status; enable machine check interrupt */ 499 /*-----------------------------------------------------------*/ 500 501 li r3, MSR_KERNEL /* Set ME and RI flags */ 502 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 503#ifdef DEBUG 504 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 505#endif 506 SYNC /* Some chip revs need this... */ 507 mtmsr r3 508 SYNC 509 mtspr SRR1, r3 /* Make SRR1 match MSR */ 510 511 512 lis r3, CONFIG_SYS_IMMR@h 513#if defined(CONFIG_WATCHDOG) 514 /* Initialise the Watchdog values and reset it (if req) */ 515 /*------------------------------------------------------*/ 516 lis r4, CONFIG_SYS_WATCHDOG_VALUE 517 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 518 stw r4, SWCRR(r3) 519 520 /* and reset it */ 521 522 li r4, 0x556C 523 sth r4, SWSRR@l(r3) 524 li r4, -0x55C7 525 sth r4, SWSRR@l(r3) 526#else 527 /* Disable Watchdog */ 528 /*-------------------*/ 529 lwz r4, SWCRR(r3) 530 /* Check to see if its enabled for disabling 531 once disabled by SW you can't re-enable */ 532 andi. r4, r4, 0x4 533 beq 1f 534 xor r4, r4, r4 535 stw r4, SWCRR(r3) 5361: 537#endif /* CONFIG_WATCHDOG */ 538 539#if defined(CONFIG_MASK_AER_AO) 540 /* Write the Arbiter Event Enable to mask Address Only traps. */ 541 /* This prevents the dcbz instruction from being trapped when */ 542 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 543 /* COHERENCY bit is set in the WIMG bits, which is often */ 544 /* needed for PCI operation. */ 545 lwz r4, 0x0808(r3) 546 rlwinm r0, r4, 0, ~AER_AO 547 stw r0, 0x0808(r3) 548#endif /* CONFIG_MASK_AER_AO */ 549 550 /* Initialize the Hardware Implementation-dependent Registers */ 551 /* HID0 also contains cache control */ 552 /* - force invalidation of data and instruction caches */ 553 /*------------------------------------------------------*/ 554 555 lis r3, CONFIG_SYS_HID0_INIT@h 556 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 557 SYNC 558 mtspr HID0, r3 559 560 lis r3, CONFIG_SYS_HID0_FINAL@h 561 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 562 SYNC 563 mtspr HID0, r3 564 565 lis r3, CONFIG_SYS_HID2@h 566 ori r3, r3, CONFIG_SYS_HID2@l 567 SYNC 568 mtspr HID2, r3 569 570 /* Done! */ 571 /*------------------------------*/ 572 blr 573 574 /* setup_bats - set them up to some initial state */ 575 .globl setup_bats 576setup_bats: 577 addis r0, r0, 0x0000 578 579 /* IBAT 0 */ 580 addis r4, r0, CONFIG_SYS_IBAT0L@h 581 ori r4, r4, CONFIG_SYS_IBAT0L@l 582 addis r3, r0, CONFIG_SYS_IBAT0U@h 583 ori r3, r3, CONFIG_SYS_IBAT0U@l 584 mtspr IBAT0L, r4 585 mtspr IBAT0U, r3 586 587 /* DBAT 0 */ 588 addis r4, r0, CONFIG_SYS_DBAT0L@h 589 ori r4, r4, CONFIG_SYS_DBAT0L@l 590 addis r3, r0, CONFIG_SYS_DBAT0U@h 591 ori r3, r3, CONFIG_SYS_DBAT0U@l 592 mtspr DBAT0L, r4 593 mtspr DBAT0U, r3 594 595 /* IBAT 1 */ 596 addis r4, r0, CONFIG_SYS_IBAT1L@h 597 ori r4, r4, CONFIG_SYS_IBAT1L@l 598 addis r3, r0, CONFIG_SYS_IBAT1U@h 599 ori r3, r3, CONFIG_SYS_IBAT1U@l 600 mtspr IBAT1L, r4 601 mtspr IBAT1U, r3 602 603 /* DBAT 1 */ 604 addis r4, r0, CONFIG_SYS_DBAT1L@h 605 ori r4, r4, CONFIG_SYS_DBAT1L@l 606 addis r3, r0, CONFIG_SYS_DBAT1U@h 607 ori r3, r3, CONFIG_SYS_DBAT1U@l 608 mtspr DBAT1L, r4 609 mtspr DBAT1U, r3 610 611 /* IBAT 2 */ 612 addis r4, r0, CONFIG_SYS_IBAT2L@h 613 ori r4, r4, CONFIG_SYS_IBAT2L@l 614 addis r3, r0, CONFIG_SYS_IBAT2U@h 615 ori r3, r3, CONFIG_SYS_IBAT2U@l 616 mtspr IBAT2L, r4 617 mtspr IBAT2U, r3 618 619 /* DBAT 2 */ 620 addis r4, r0, CONFIG_SYS_DBAT2L@h 621 ori r4, r4, CONFIG_SYS_DBAT2L@l 622 addis r3, r0, CONFIG_SYS_DBAT2U@h 623 ori r3, r3, CONFIG_SYS_DBAT2U@l 624 mtspr DBAT2L, r4 625 mtspr DBAT2U, r3 626 627 /* IBAT 3 */ 628 addis r4, r0, CONFIG_SYS_IBAT3L@h 629 ori r4, r4, CONFIG_SYS_IBAT3L@l 630 addis r3, r0, CONFIG_SYS_IBAT3U@h 631 ori r3, r3, CONFIG_SYS_IBAT3U@l 632 mtspr IBAT3L, r4 633 mtspr IBAT3U, r3 634 635 /* DBAT 3 */ 636 addis r4, r0, CONFIG_SYS_DBAT3L@h 637 ori r4, r4, CONFIG_SYS_DBAT3L@l 638 addis r3, r0, CONFIG_SYS_DBAT3U@h 639 ori r3, r3, CONFIG_SYS_DBAT3U@l 640 mtspr DBAT3L, r4 641 mtspr DBAT3U, r3 642 643#ifdef CONFIG_HIGH_BATS 644 /* IBAT 4 */ 645 addis r4, r0, CONFIG_SYS_IBAT4L@h 646 ori r4, r4, CONFIG_SYS_IBAT4L@l 647 addis r3, r0, CONFIG_SYS_IBAT4U@h 648 ori r3, r3, CONFIG_SYS_IBAT4U@l 649 mtspr IBAT4L, r4 650 mtspr IBAT4U, r3 651 652 /* DBAT 4 */ 653 addis r4, r0, CONFIG_SYS_DBAT4L@h 654 ori r4, r4, CONFIG_SYS_DBAT4L@l 655 addis r3, r0, CONFIG_SYS_DBAT4U@h 656 ori r3, r3, CONFIG_SYS_DBAT4U@l 657 mtspr DBAT4L, r4 658 mtspr DBAT4U, r3 659 660 /* IBAT 5 */ 661 addis r4, r0, CONFIG_SYS_IBAT5L@h 662 ori r4, r4, CONFIG_SYS_IBAT5L@l 663 addis r3, r0, CONFIG_SYS_IBAT5U@h 664 ori r3, r3, CONFIG_SYS_IBAT5U@l 665 mtspr IBAT5L, r4 666 mtspr IBAT5U, r3 667 668 /* DBAT 5 */ 669 addis r4, r0, CONFIG_SYS_DBAT5L@h 670 ori r4, r4, CONFIG_SYS_DBAT5L@l 671 addis r3, r0, CONFIG_SYS_DBAT5U@h 672 ori r3, r3, CONFIG_SYS_DBAT5U@l 673 mtspr DBAT5L, r4 674 mtspr DBAT5U, r3 675 676 /* IBAT 6 */ 677 addis r4, r0, CONFIG_SYS_IBAT6L@h 678 ori r4, r4, CONFIG_SYS_IBAT6L@l 679 addis r3, r0, CONFIG_SYS_IBAT6U@h 680 ori r3, r3, CONFIG_SYS_IBAT6U@l 681 mtspr IBAT6L, r4 682 mtspr IBAT6U, r3 683 684 /* DBAT 6 */ 685 addis r4, r0, CONFIG_SYS_DBAT6L@h 686 ori r4, r4, CONFIG_SYS_DBAT6L@l 687 addis r3, r0, CONFIG_SYS_DBAT6U@h 688 ori r3, r3, CONFIG_SYS_DBAT6U@l 689 mtspr DBAT6L, r4 690 mtspr DBAT6U, r3 691 692 /* IBAT 7 */ 693 addis r4, r0, CONFIG_SYS_IBAT7L@h 694 ori r4, r4, CONFIG_SYS_IBAT7L@l 695 addis r3, r0, CONFIG_SYS_IBAT7U@h 696 ori r3, r3, CONFIG_SYS_IBAT7U@l 697 mtspr IBAT7L, r4 698 mtspr IBAT7U, r3 699 700 /* DBAT 7 */ 701 addis r4, r0, CONFIG_SYS_DBAT7L@h 702 ori r4, r4, CONFIG_SYS_DBAT7L@l 703 addis r3, r0, CONFIG_SYS_DBAT7U@h 704 ori r3, r3, CONFIG_SYS_DBAT7U@l 705 mtspr DBAT7L, r4 706 mtspr DBAT7U, r3 707#endif 708 709 isync 710 711 /* invalidate all tlb's 712 * 713 * From the 603e User Manual: "The 603e provides the ability to 714 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 715 * instruction invalidates the TLB entry indexed by the EA, and 716 * operates on both the instruction and data TLBs simultaneously 717 * invalidating four TLB entries (both sets in each TLB). The 718 * index corresponds to bits 15-19 of the EA. To invalidate all 719 * entries within both TLBs, 32 tlbie instructions should be 720 * issued, incrementing this field by one each time." 721 * 722 * "Note that the tlbia instruction is not implemented on the 723 * 603e." 724 * 725 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 726 * incrementing by 0x1000 each time. The code below is sort of 727 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 728 * 729 */ 730 lis r3, 0 731 lis r5, 2 732 7331: 734 tlbie r3 735 addi r3, r3, 0x1000 736 cmp 0, 0, r3, r5 737 blt 1b 738 739 blr 740 741/* Cache functions. 742 * 743 * Note: requires that all cache bits in 744 * HID0 are in the low half word. 745 */ 746#ifndef MINIMAL_SPL 747 .globl icache_enable 748icache_enable: 749 mfspr r3, HID0 750 ori r3, r3, HID0_ICE 751 li r4, HID0_ICFI|HID0_ILOCK 752 andc r3, r3, r4 753 ori r4, r3, HID0_ICFI 754 isync 755 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 756 isync 757 mtspr HID0, r3 /* clears invalidate */ 758 blr 759 760 .globl icache_disable 761icache_disable: 762 mfspr r3, HID0 763 lis r4, 0 764 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 765 andc r3, r3, r4 766 isync 767 mtspr HID0, r3 /* clears invalidate, enable and lock */ 768 blr 769 770 .globl icache_status 771icache_status: 772 mfspr r3, HID0 773 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 774 blr 775#endif /* !MINIMAL_SPL */ 776 777 .globl dcache_enable 778dcache_enable: 779 mfspr r3, HID0 780 li r5, HID0_DCFI|HID0_DLOCK 781 andc r3, r3, r5 782 ori r3, r3, HID0_DCE 783 sync 784 mtspr HID0, r3 /* enable, no invalidate */ 785 blr 786 787 .globl dcache_disable 788dcache_disable: 789 mflr r4 790 bl flush_dcache /* uses r3 and r5 */ 791 mfspr r3, HID0 792 li r5, HID0_DCE|HID0_DLOCK 793 andc r3, r3, r5 794 ori r5, r3, HID0_DCFI 795 sync 796 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 797 sync 798 mtspr HID0, r3 /* clears invalidate */ 799 mtlr r4 800 blr 801 802 .globl dcache_status 803dcache_status: 804 mfspr r3, HID0 805 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 806 blr 807 808 .globl flush_dcache 809flush_dcache: 810 lis r3, 0 811 lis r5, CONFIG_SYS_CACHELINE_SIZE 8121: cmp 0, 1, r3, r5 813 bge 2f 814 lwz r5, 0(r3) 815 lis r5, CONFIG_SYS_CACHELINE_SIZE 816 addi r3, r3, 0x4 817 b 1b 8182: blr 819 820/*-------------------------------------------------------------------*/ 821 822/* 823 * void relocate_code (addr_sp, gd, addr_moni) 824 * 825 * This "function" does not return, instead it continues in RAM 826 * after relocating the monitor code. 827 * 828 * r3 = dest 829 * r4 = src 830 * r5 = length in bytes 831 * r6 = cachelinesize 832 */ 833 .globl relocate_code 834relocate_code: 835 mr r1, r3 /* Set new stack pointer */ 836 mr r9, r4 /* Save copy of Global Data pointer */ 837 mr r10, r5 /* Save copy of Destination Address */ 838 839 GET_GOT 840 mr r3, r5 /* Destination Address */ 841 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 842 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 843 lwz r5, GOT(__bss_start) 844 sub r5, r5, r4 845 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 846 847 /* 848 * Fix GOT pointer: 849 * 850 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 851 * + Destination Address 852 * 853 * Offset: 854 */ 855 sub r15, r10, r4 856 857 /* First our own GOT */ 858 add r12, r12, r15 859 /* then the one used by the C code */ 860 add r30, r30, r15 861 862 /* 863 * Now relocate code 864 */ 865 866 cmplw cr1,r3,r4 867 addi r0,r5,3 868 srwi. r0,r0,2 869 beq cr1,4f /* In place copy is not necessary */ 870 beq 7f /* Protect against 0 count */ 871 mtctr r0 872 bge cr1,2f 873 la r8,-4(r4) 874 la r7,-4(r3) 875 876 /* copy */ 8771: lwzu r0,4(r8) 878 stwu r0,4(r7) 879 bdnz 1b 880 881 addi r0,r5,3 882 srwi. r0,r0,2 883 mtctr r0 884 la r8,-4(r4) 885 la r7,-4(r3) 886 887 /* and compare */ 88820: lwzu r20,4(r8) 889 lwzu r21,4(r7) 890 xor. r22, r20, r21 891 bne 30f 892 bdnz 20b 893 b 4f 894 895 /* compare failed */ 89630: li r3, 0 897 blr 898 8992: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 900 add r8,r4,r0 901 add r7,r3,r0 9023: lwzu r0,-4(r8) 903 stwu r0,-4(r7) 904 bdnz 3b 905 906/* 907 * Now flush the cache: note that we must start from a cache aligned 908 * address. Otherwise we might miss one cache line. 909 */ 9104: cmpwi r6,0 911 add r5,r3,r5 912 beq 7f /* Always flush prefetch queue in any case */ 913 subi r0,r6,1 914 andc r3,r3,r0 915 mr r4,r3 9165: dcbst 0,r4 917 add r4,r4,r6 918 cmplw r4,r5 919 blt 5b 920 sync /* Wait for all dcbst to complete on bus */ 921 mr r4,r3 9226: icbi 0,r4 923 add r4,r4,r6 924 cmplw r4,r5 925 blt 6b 9267: sync /* Wait for all icbi to complete on bus */ 927 isync 928 929/* 930 * We are done. Do not return, instead branch to second part of board 931 * initialization, now running from RAM. 932 */ 933 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 934 mtlr r0 935 blr 936 937in_ram: 938 939 /* 940 * Relocation Function, r12 point to got2+0x8000 941 * 942 * Adjust got2 pointers, no need to check for 0, this code 943 * already puts a few entries in the table. 944 */ 945 li r0,__got2_entries@sectoff@l 946 la r3,GOT(_GOT2_TABLE_) 947 lwz r11,GOT(_GOT2_TABLE_) 948 mtctr r0 949 sub r11,r3,r11 950 addi r3,r3,-4 9511: lwzu r0,4(r3) 952 cmpwi r0,0 953 beq- 2f 954 add r0,r0,r11 955 stw r0,0(r3) 9562: bdnz 1b 957 958#ifndef MINIMAL_SPL 959 /* 960 * Now adjust the fixups and the pointers to the fixups 961 * in case we need to move ourselves again. 962 */ 963 li r0,__fixup_entries@sectoff@l 964 lwz r3,GOT(_FIXUP_TABLE_) 965 cmpwi r0,0 966 mtctr r0 967 addi r3,r3,-4 968 beq 4f 9693: lwzu r4,4(r3) 970 lwzux r0,r4,r11 971 cmpwi r0,0 972 add r0,r0,r11 973 stw r4,0(r3) 974 beq- 5f 975 stw r0,0(r4) 9765: bdnz 3b 9774: 978#endif 979 980clear_bss: 981 /* 982 * Now clear BSS segment 983 */ 984 lwz r3,GOT(__bss_start) 985 lwz r4,GOT(__bss_end) 986 987 cmplw 0, r3, r4 988 beq 6f 989 990 li r0, 0 9915: 992 stw r0, 0(r3) 993 addi r3, r3, 4 994 cmplw 0, r3, r4 995 bne 5b 9966: 997 998 mr r3, r9 /* Global Data pointer */ 999 mr r4, r10 /* Destination Address */ 1000 bl board_init_r 1001 1002#ifndef MINIMAL_SPL 1003 /* 1004 * Copy exception vector code to low memory 1005 * 1006 * r3: dest_addr 1007 * r7: source address, r8: end address, r9: target address 1008 */ 1009 .globl trap_init 1010trap_init: 1011 mflr r4 /* save link register */ 1012 GET_GOT 1013 lwz r7, GOT(_start) 1014 lwz r8, GOT(_end_of_vectors) 1015 1016 li r9, 0x100 /* reset vector always at 0x100 */ 1017 1018 cmplw 0, r7, r8 1019 bgelr /* return if r7>=r8 - just in case */ 10201: 1021 lwz r0, 0(r7) 1022 stw r0, 0(r9) 1023 addi r7, r7, 4 1024 addi r9, r9, 4 1025 cmplw 0, r7, r8 1026 bne 1b 1027 1028 /* 1029 * relocate `hdlr' and `int_return' entries 1030 */ 1031 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1032 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10332: 1034 bl trap_reloc 1035 addi r7, r7, 0x100 /* next exception vector */ 1036 cmplw 0, r7, r8 1037 blt 2b 1038 1039 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1040 bl trap_reloc 1041 1042 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1043 bl trap_reloc 1044 1045 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1046 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10473: 1048 bl trap_reloc 1049 addi r7, r7, 0x100 /* next exception vector */ 1050 cmplw 0, r7, r8 1051 blt 3b 1052 1053 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1054 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10554: 1056 bl trap_reloc 1057 addi r7, r7, 0x100 /* next exception vector */ 1058 cmplw 0, r7, r8 1059 blt 4b 1060 1061 mfmsr r3 /* now that the vectors have */ 1062 lis r7, MSR_IP@h /* relocated into low memory */ 1063 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1064 andc r3, r3, r7 /* (if it was on) */ 1065 SYNC /* Some chip revs need this... */ 1066 mtmsr r3 1067 SYNC 1068 1069 mtlr r4 /* restore link register */ 1070 blr 1071 1072#endif /* !MINIMAL_SPL */ 1073 1074#ifdef CONFIG_SYS_INIT_RAM_LOCK 1075lock_ram_in_cache: 1076 /* Allocate Initial RAM in data cache. 1077 */ 1078 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1079 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1080 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1081 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1082 mtctr r4 10831: 1084 dcbz r0, r3 1085 addi r3, r3, 32 1086 bdnz 1b 1087 1088 /* Lock the data cache */ 1089 mfspr r0, HID0 1090 ori r0, r0, HID0_DLOCK 1091 sync 1092 mtspr HID0, r0 1093 sync 1094 blr 1095 1096#ifndef MINIMAL_SPL 1097.globl unlock_ram_in_cache 1098unlock_ram_in_cache: 1099 /* invalidate the INIT_RAM section */ 1100 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1101 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1102 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1103 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1104 mtctr r4 11051: icbi r0, r3 1106 dcbi r0, r3 1107 addi r3, r3, 32 1108 bdnz 1b 1109 sync /* Wait for all icbi to complete on bus */ 1110 isync 1111 1112 /* Unlock the data cache and invalidate it */ 1113 mfspr r3, HID0 1114 li r5, HID0_DLOCK|HID0_DCFI 1115 andc r3, r3, r5 /* no invalidate, unlock */ 1116 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1117 sync 1118 mtspr HID0, r5 /* invalidate, unlock */ 1119 sync 1120 mtspr HID0, r3 /* no invalidate, unlock */ 1121 blr 1122#endif /* !MINIMAL_SPL */ 1123#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1124 1125#ifdef CONFIG_SYS_FLASHBOOT 1126map_flash_by_law1: 1127 /* When booting from ROM (Flash or EPROM), clear the */ 1128 /* Address Mask in OR0 so ROM appears everywhere */ 1129 /*----------------------------------------------------*/ 1130 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1131 lwz r4, OR0@l(r3) 1132 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1133 and r4, r4, r5 1134 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1135 1136 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1137 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1138 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1139 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1140 * 0xFF800. From the hard resetting to here, the processor fetched and 1141 * executed the instructions one by one. There is not absolutely 1142 * jumping happened. Laterly, the u-boot code has to do an absolutely 1143 * jumping to tell the CPU instruction fetching component what the 1144 * u-boot TEXT base address is. Because the TEXT base resides in the 1145 * boot ROM memory space, to garantee the code can run smoothly after 1146 * that jumping, we must map in the entire boot ROM by Local Access 1147 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1148 * address for boot ROM, such as 0xFE000000. In this case, the default 1149 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1150 * need another window to map in it. 1151 */ 1152 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1153 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1154 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1155 1156 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1157 lis r4, (0x80000012)@h 1158 ori r4, r4, (0x80000012)@l 1159 li r5, CONFIG_SYS_FLASH_SIZE 11601: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1161 addi r4, r4, 1 1162 bne 1b 1163 1164 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1165 /* Wait for HW to catch up */ 1166 lwz r4, LBLAWAR1(r3) 1167 twi 0,r4,0 1168 isync 1169 blr 1170 1171 /* Though all the LBIU Local Access Windows and LBC Banks will be 1172 * initialized in the C code, we'd better configure boot ROM's 1173 * window 0 and bank 0 correctly at here. 1174 */ 1175remap_flash_by_law0: 1176 /* Initialize the BR0 with the boot ROM starting address. */ 1177 lwz r4, BR0(r3) 1178 li r5, 0x7FFF 1179 and r4, r4, r5 1180 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1181 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1182 or r5, r5, r4 1183 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1184 1185 lwz r4, OR0(r3) 1186 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1187 or r4, r4, r5 1188 stw r4, OR0(r3) 1189 1190 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1191 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1192 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1193 1194 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1195 lis r4, (0x80000012)@h 1196 ori r4, r4, (0x80000012)@l 1197 li r5, CONFIG_SYS_FLASH_SIZE 11981: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1199 addi r4, r4, 1 1200 bne 1b 1201 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1202 1203 1204 xor r4, r4, r4 1205 stw r4, LBLAWBAR1(r3) 1206 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1207 /* Wait for HW to catch up */ 1208 lwz r4, LBLAWAR1(r3) 1209 twi 0,r4,0 1210 isync 1211 blr 1212#endif /* CONFIG_SYS_FLASHBOOT */ 1213