1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <mpc83xx.h> 28 #include <command.h> 29 #include <asm/processor.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* ----------------------------------------------------------------- */ 34 35 typedef enum { 36 _unk, 37 _off, 38 _byp, 39 _x8, 40 _x4, 41 _x2, 42 _x1, 43 _1x, 44 _1_5x, 45 _2x, 46 _2_5x, 47 _3x 48 } mult_t; 49 50 typedef struct { 51 mult_t core_csb_ratio; 52 mult_t vco_divider; 53 } corecnf_t; 54 55 corecnf_t corecnf_tab[] = { 56 {_byp, _byp}, /* 0x00 */ 57 {_byp, _byp}, /* 0x01 */ 58 {_byp, _byp}, /* 0x02 */ 59 {_byp, _byp}, /* 0x03 */ 60 {_byp, _byp}, /* 0x04 */ 61 {_byp, _byp}, /* 0x05 */ 62 {_byp, _byp}, /* 0x06 */ 63 {_byp, _byp}, /* 0x07 */ 64 {_1x, _x2}, /* 0x08 */ 65 {_1x, _x4}, /* 0x09 */ 66 {_1x, _x8}, /* 0x0A */ 67 {_1x, _x8}, /* 0x0B */ 68 {_1_5x, _x2}, /* 0x0C */ 69 {_1_5x, _x4}, /* 0x0D */ 70 {_1_5x, _x8}, /* 0x0E */ 71 {_1_5x, _x8}, /* 0x0F */ 72 {_2x, _x2}, /* 0x10 */ 73 {_2x, _x4}, /* 0x11 */ 74 {_2x, _x8}, /* 0x12 */ 75 {_2x, _x8}, /* 0x13 */ 76 {_2_5x, _x2}, /* 0x14 */ 77 {_2_5x, _x4}, /* 0x15 */ 78 {_2_5x, _x8}, /* 0x16 */ 79 {_2_5x, _x8}, /* 0x17 */ 80 {_3x, _x2}, /* 0x18 */ 81 {_3x, _x4}, /* 0x19 */ 82 {_3x, _x8}, /* 0x1A */ 83 {_3x, _x8}, /* 0x1B */ 84 }; 85 86 /* ----------------------------------------------------------------- */ 87 88 /* 89 * 90 */ 91 int get_clocks(void) 92 { 93 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 94 u32 pci_sync_in; 95 u8 spmf; 96 u8 clkin_div; 97 u32 sccr; 98 u32 corecnf_tab_index; 99 u8 corepll; 100 u32 lcrr; 101 102 u32 csb_clk; 103 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 104 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 105 u32 tsec1_clk; 106 u32 tsec2_clk; 107 u32 usbdr_clk; 108 #endif 109 #ifdef CONFIG_MPC834x 110 u32 usbmph_clk; 111 #endif 112 u32 core_clk; 113 u32 i2c1_clk; 114 #if !defined(CONFIG_MPC832x) 115 u32 i2c2_clk; 116 #endif 117 #if defined(CONFIG_MPC8315) 118 u32 tdm_clk; 119 #endif 120 #if defined(CONFIG_FSL_ESDHC) 121 u32 sdhc_clk; 122 #endif 123 u32 enc_clk; 124 u32 lbiu_clk; 125 u32 lclk_clk; 126 u32 mem_clk; 127 #if defined(CONFIG_MPC8360) 128 u32 mem_sec_clk; 129 #endif 130 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 131 u32 qepmf; 132 u32 qepdf; 133 u32 qe_clk; 134 u32 brg_clk; 135 #endif 136 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 137 defined(CONFIG_MPC837x) 138 u32 pciexp1_clk; 139 u32 pciexp2_clk; 140 #endif 141 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 142 u32 sata_clk; 143 #endif 144 145 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 146 return -1; 147 148 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); 149 150 if (im->reset.rcwh & HRCWH_PCI_HOST) { 151 #if defined(CONFIG_83XX_CLKIN) 152 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); 153 #else 154 pci_sync_in = 0xDEADBEEF; 155 #endif 156 } else { 157 #if defined(CONFIG_83XX_PCICLK) 158 pci_sync_in = CONFIG_83XX_PCICLK; 159 #else 160 pci_sync_in = 0xDEADBEEF; 161 #endif 162 } 163 164 spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); 165 csb_clk = pci_sync_in * (1 + clkin_div) * spmf; 166 167 sccr = im->clk.sccr; 168 169 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 170 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 171 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { 172 case 0: 173 tsec1_clk = 0; 174 break; 175 case 1: 176 tsec1_clk = csb_clk; 177 break; 178 case 2: 179 tsec1_clk = csb_clk / 2; 180 break; 181 case 3: 182 tsec1_clk = csb_clk / 3; 183 break; 184 default: 185 /* unkown SCCR_TSEC1CM value */ 186 return -2; 187 } 188 189 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { 190 case 0: 191 usbdr_clk = 0; 192 break; 193 case 1: 194 usbdr_clk = csb_clk; 195 break; 196 case 2: 197 usbdr_clk = csb_clk / 2; 198 break; 199 case 3: 200 usbdr_clk = csb_clk / 3; 201 break; 202 default: 203 /* unkown SCCR_USBDRCM value */ 204 return -3; 205 } 206 #endif 207 208 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \ 209 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 210 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { 211 case 0: 212 tsec2_clk = 0; 213 break; 214 case 1: 215 tsec2_clk = csb_clk; 216 break; 217 case 2: 218 tsec2_clk = csb_clk / 2; 219 break; 220 case 3: 221 tsec2_clk = csb_clk / 3; 222 break; 223 default: 224 /* unkown SCCR_TSEC2CM value */ 225 return -4; 226 } 227 #elif defined(CONFIG_MPC8313) 228 tsec2_clk = tsec1_clk; 229 230 if (!(sccr & SCCR_TSEC1ON)) 231 tsec1_clk = 0; 232 if (!(sccr & SCCR_TSEC2ON)) 233 tsec2_clk = 0; 234 #endif 235 236 #if defined(CONFIG_MPC834x) 237 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { 238 case 0: 239 usbmph_clk = 0; 240 break; 241 case 1: 242 usbmph_clk = csb_clk; 243 break; 244 case 2: 245 usbmph_clk = csb_clk / 2; 246 break; 247 case 3: 248 usbmph_clk = csb_clk / 3; 249 break; 250 default: 251 /* unkown SCCR_USBMPHCM value */ 252 return -5; 253 } 254 255 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) { 256 /* if USB MPH clock is not disabled and 257 * USB DR clock is not disabled then 258 * USB MPH & USB DR must have the same rate 259 */ 260 return -6; 261 } 262 #endif 263 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { 264 case 0: 265 enc_clk = 0; 266 break; 267 case 1: 268 enc_clk = csb_clk; 269 break; 270 case 2: 271 enc_clk = csb_clk / 2; 272 break; 273 case 3: 274 enc_clk = csb_clk / 3; 275 break; 276 default: 277 /* unkown SCCR_ENCCM value */ 278 return -7; 279 } 280 281 #if defined(CONFIG_FSL_ESDHC) 282 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { 283 case 0: 284 sdhc_clk = 0; 285 break; 286 case 1: 287 sdhc_clk = csb_clk; 288 break; 289 case 2: 290 sdhc_clk = csb_clk / 2; 291 break; 292 case 3: 293 sdhc_clk = csb_clk / 3; 294 break; 295 default: 296 /* unkown SCCR_SDHCCM value */ 297 return -8; 298 } 299 #endif 300 #if defined(CONFIG_MPC8315) 301 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { 302 case 0: 303 tdm_clk = 0; 304 break; 305 case 1: 306 tdm_clk = csb_clk; 307 break; 308 case 2: 309 tdm_clk = csb_clk / 2; 310 break; 311 case 3: 312 tdm_clk = csb_clk / 3; 313 break; 314 default: 315 /* unkown SCCR_TDMCM value */ 316 return -8; 317 } 318 #endif 319 320 #if defined(CONFIG_MPC834x) 321 i2c1_clk = tsec2_clk; 322 #elif defined(CONFIG_MPC8360) 323 i2c1_clk = csb_clk; 324 #elif defined(CONFIG_MPC832x) 325 i2c1_clk = enc_clk; 326 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) 327 i2c1_clk = enc_clk; 328 #elif defined(CONFIG_FSL_ESDHC) 329 i2c1_clk = sdhc_clk; 330 #endif 331 #if !defined(CONFIG_MPC832x) 332 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ 333 #endif 334 335 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 336 defined(CONFIG_MPC837x) 337 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { 338 case 0: 339 pciexp1_clk = 0; 340 break; 341 case 1: 342 pciexp1_clk = csb_clk; 343 break; 344 case 2: 345 pciexp1_clk = csb_clk / 2; 346 break; 347 case 3: 348 pciexp1_clk = csb_clk / 3; 349 break; 350 default: 351 /* unkown SCCR_PCIEXP1CM value */ 352 return -9; 353 } 354 355 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) { 356 case 0: 357 pciexp2_clk = 0; 358 break; 359 case 1: 360 pciexp2_clk = csb_clk; 361 break; 362 case 2: 363 pciexp2_clk = csb_clk / 2; 364 break; 365 case 3: 366 pciexp2_clk = csb_clk / 3; 367 break; 368 default: 369 /* unkown SCCR_PCIEXP2CM value */ 370 return -10; 371 } 372 #endif 373 374 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 375 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { 376 case 0: 377 sata_clk = 0; 378 break; 379 case 1: 380 sata_clk = csb_clk; 381 break; 382 case 2: 383 sata_clk = csb_clk / 2; 384 break; 385 case 3: 386 sata_clk = csb_clk / 3; 387 break; 388 default: 389 /* unkown SCCR_SATACM value */ 390 return -11; 391 } 392 #endif 393 394 lbiu_clk = csb_clk * 395 (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); 396 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; 397 switch (lcrr) { 398 case 2: 399 case 4: 400 case 8: 401 lclk_clk = lbiu_clk / lcrr; 402 break; 403 default: 404 /* unknown lcrr */ 405 return -12; 406 } 407 408 mem_clk = csb_clk * 409 (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); 410 corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; 411 #if defined(CONFIG_MPC8360) 412 mem_sec_clk = csb_clk * (1 + 413 ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); 414 #endif 415 416 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); 417 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { 418 /* corecnf_tab_index is too high, possibly worng value */ 419 return -11; 420 } 421 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { 422 case _byp: 423 case _x1: 424 case _1x: 425 core_clk = csb_clk; 426 break; 427 case _1_5x: 428 core_clk = (3 * csb_clk) / 2; 429 break; 430 case _2x: 431 core_clk = 2 * csb_clk; 432 break; 433 case _2_5x: 434 core_clk = (5 * csb_clk) / 2; 435 break; 436 case _3x: 437 core_clk = 3 * csb_clk; 438 break; 439 default: 440 /* unkown core to csb ratio */ 441 return -13; 442 } 443 444 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 445 qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; 446 qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; 447 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); 448 brg_clk = qe_clk / 2; 449 #endif 450 451 gd->csb_clk = csb_clk; 452 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 453 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 454 gd->tsec1_clk = tsec1_clk; 455 gd->tsec2_clk = tsec2_clk; 456 gd->usbdr_clk = usbdr_clk; 457 #endif 458 #if defined(CONFIG_MPC834x) 459 gd->usbmph_clk = usbmph_clk; 460 #endif 461 #if defined(CONFIG_MPC8315) 462 gd->tdm_clk = tdm_clk; 463 #endif 464 #if defined(CONFIG_FSL_ESDHC) 465 gd->sdhc_clk = sdhc_clk; 466 #endif 467 gd->core_clk = core_clk; 468 gd->i2c1_clk = i2c1_clk; 469 #if !defined(CONFIG_MPC832x) 470 gd->i2c2_clk = i2c2_clk; 471 #endif 472 gd->enc_clk = enc_clk; 473 gd->lbiu_clk = lbiu_clk; 474 gd->lclk_clk = lclk_clk; 475 gd->mem_clk = mem_clk; 476 #if defined(CONFIG_MPC8360) 477 gd->mem_sec_clk = mem_sec_clk; 478 #endif 479 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 480 gd->qe_clk = qe_clk; 481 gd->brg_clk = brg_clk; 482 #endif 483 #if defined(CONFIG_MPC837x) 484 gd->pciexp1_clk = pciexp1_clk; 485 gd->pciexp2_clk = pciexp2_clk; 486 #endif 487 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 488 gd->sata_clk = sata_clk; 489 #endif 490 gd->pci_clk = pci_sync_in; 491 gd->cpu_clk = gd->core_clk; 492 gd->bus_clk = gd->csb_clk; 493 return 0; 494 495 } 496 497 /******************************************** 498 * get_bus_freq 499 * return system bus freq in Hz 500 *********************************************/ 501 ulong get_bus_freq(ulong dummy) 502 { 503 return gd->csb_clk; 504 } 505 506 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 507 { 508 char buf[32]; 509 510 printf("Clock configuration:\n"); 511 printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk)); 512 printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); 513 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 514 printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); 515 printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); 516 #endif 517 printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk)); 518 printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk)); 519 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk)); 520 #if defined(CONFIG_MPC8360) 521 printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk)); 522 #endif 523 printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk)); 524 printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk)); 525 #if !defined(CONFIG_MPC832x) 526 printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk)); 527 #endif 528 #if defined(CONFIG_MPC8315) 529 printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk)); 530 #endif 531 #if defined(CONFIG_FSL_ESDHC) 532 printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk)); 533 #endif 534 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 535 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 536 printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk)); 537 printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk)); 538 printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); 539 #endif 540 #if defined(CONFIG_MPC834x) 541 printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); 542 #endif 543 #if defined(CONFIG_MPC837x) 544 printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); 545 printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); 546 #endif 547 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 548 printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk)); 549 #endif 550 return 0; 551 } 552 553 U_BOOT_CMD(clocks, 1, 0, do_clocks, 554 "print clock configuration", 555 " clocks" 556 ); 557