1 /* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <mpc83xx.h> 28 #include <command.h> 29 #include <asm/processor.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* ----------------------------------------------------------------- */ 34 35 typedef enum { 36 _unk, 37 _off, 38 _byp, 39 _x8, 40 _x4, 41 _x2, 42 _x1, 43 _1x, 44 _1_5x, 45 _2x, 46 _2_5x, 47 _3x 48 } mult_t; 49 50 typedef struct { 51 mult_t core_csb_ratio; 52 mult_t vco_divider; 53 } corecnf_t; 54 55 corecnf_t corecnf_tab[] = { 56 {_byp, _byp}, /* 0x00 */ 57 {_byp, _byp}, /* 0x01 */ 58 {_byp, _byp}, /* 0x02 */ 59 {_byp, _byp}, /* 0x03 */ 60 {_byp, _byp}, /* 0x04 */ 61 {_byp, _byp}, /* 0x05 */ 62 {_byp, _byp}, /* 0x06 */ 63 {_byp, _byp}, /* 0x07 */ 64 {_1x, _x2}, /* 0x08 */ 65 {_1x, _x4}, /* 0x09 */ 66 {_1x, _x8}, /* 0x0A */ 67 {_1x, _x8}, /* 0x0B */ 68 {_1_5x, _x2}, /* 0x0C */ 69 {_1_5x, _x4}, /* 0x0D */ 70 {_1_5x, _x8}, /* 0x0E */ 71 {_1_5x, _x8}, /* 0x0F */ 72 {_2x, _x2}, /* 0x10 */ 73 {_2x, _x4}, /* 0x11 */ 74 {_2x, _x8}, /* 0x12 */ 75 {_2x, _x8}, /* 0x13 */ 76 {_2_5x, _x2}, /* 0x14 */ 77 {_2_5x, _x4}, /* 0x15 */ 78 {_2_5x, _x8}, /* 0x16 */ 79 {_2_5x, _x8}, /* 0x17 */ 80 {_3x, _x2}, /* 0x18 */ 81 {_3x, _x4}, /* 0x19 */ 82 {_3x, _x8}, /* 0x1A */ 83 {_3x, _x8}, /* 0x1B */ 84 }; 85 86 /* ----------------------------------------------------------------- */ 87 88 /* 89 * 90 */ 91 int get_clocks(void) 92 { 93 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 94 u32 pci_sync_in; 95 u8 spmf; 96 u8 clkin_div; 97 u32 sccr; 98 u32 corecnf_tab_index; 99 u8 corepll; 100 u32 lcrr; 101 102 u32 csb_clk; 103 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 104 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 105 u32 tsec1_clk; 106 u32 tsec2_clk; 107 u32 usbdr_clk; 108 #endif 109 #ifdef CONFIG_MPC834x 110 u32 usbmph_clk; 111 #endif 112 u32 core_clk; 113 u32 i2c1_clk; 114 #if !defined(CONFIG_MPC832x) 115 u32 i2c2_clk; 116 #endif 117 #if defined(CONFIG_MPC8315) 118 u32 tdm_clk; 119 #endif 120 #if defined(CONFIG_FSL_ESDHC) 121 u32 sdhc_clk; 122 #endif 123 u32 enc_clk; 124 u32 lbiu_clk; 125 u32 lclk_clk; 126 u32 mem_clk; 127 #if defined(CONFIG_MPC8360) 128 u32 mem_sec_clk; 129 #endif 130 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 131 u32 qepmf; 132 u32 qepdf; 133 u32 qe_clk; 134 u32 brg_clk; 135 #endif 136 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 137 defined(CONFIG_MPC837x) 138 u32 pciexp1_clk; 139 u32 pciexp2_clk; 140 #endif 141 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 142 u32 sata_clk; 143 #endif 144 145 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 146 return -1; 147 148 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); 149 150 if (im->reset.rcwh & HRCWH_PCI_HOST) { 151 #if defined(CONFIG_83XX_CLKIN) 152 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); 153 #else 154 pci_sync_in = 0xDEADBEEF; 155 #endif 156 } else { 157 #if defined(CONFIG_83XX_PCICLK) 158 pci_sync_in = CONFIG_83XX_PCICLK; 159 #else 160 pci_sync_in = 0xDEADBEEF; 161 #endif 162 } 163 164 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; 165 csb_clk = pci_sync_in * (1 + clkin_div) * spmf; 166 167 sccr = im->clk.sccr; 168 169 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 170 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 171 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { 172 case 0: 173 tsec1_clk = 0; 174 break; 175 case 1: 176 tsec1_clk = csb_clk; 177 break; 178 case 2: 179 tsec1_clk = csb_clk / 2; 180 break; 181 case 3: 182 tsec1_clk = csb_clk / 3; 183 break; 184 default: 185 /* unkown SCCR_TSEC1CM value */ 186 return -2; 187 } 188 189 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { 190 case 0: 191 usbdr_clk = 0; 192 break; 193 case 1: 194 usbdr_clk = csb_clk; 195 break; 196 case 2: 197 usbdr_clk = csb_clk / 2; 198 break; 199 case 3: 200 usbdr_clk = csb_clk / 3; 201 break; 202 default: 203 /* unkown SCCR_USBDRCM value */ 204 return -3; 205 } 206 #endif 207 208 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \ 209 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 210 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { 211 case 0: 212 tsec2_clk = 0; 213 break; 214 case 1: 215 tsec2_clk = csb_clk; 216 break; 217 case 2: 218 tsec2_clk = csb_clk / 2; 219 break; 220 case 3: 221 tsec2_clk = csb_clk / 3; 222 break; 223 default: 224 /* unkown SCCR_TSEC2CM value */ 225 return -4; 226 } 227 #elif defined(CONFIG_MPC8313) 228 tsec2_clk = tsec1_clk; 229 230 if (!(sccr & SCCR_TSEC1ON)) 231 tsec1_clk = 0; 232 if (!(sccr & SCCR_TSEC2ON)) 233 tsec2_clk = 0; 234 #endif 235 236 #if defined(CONFIG_MPC834x) 237 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { 238 case 0: 239 usbmph_clk = 0; 240 break; 241 case 1: 242 usbmph_clk = csb_clk; 243 break; 244 case 2: 245 usbmph_clk = csb_clk / 2; 246 break; 247 case 3: 248 usbmph_clk = csb_clk / 3; 249 break; 250 default: 251 /* unkown SCCR_USBMPHCM value */ 252 return -5; 253 } 254 255 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) { 256 /* if USB MPH clock is not disabled and 257 * USB DR clock is not disabled then 258 * USB MPH & USB DR must have the same rate 259 */ 260 return -6; 261 } 262 #endif 263 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { 264 case 0: 265 enc_clk = 0; 266 break; 267 case 1: 268 enc_clk = csb_clk; 269 break; 270 case 2: 271 enc_clk = csb_clk / 2; 272 break; 273 case 3: 274 enc_clk = csb_clk / 3; 275 break; 276 default: 277 /* unkown SCCR_ENCCM value */ 278 return -7; 279 } 280 281 #if defined(CONFIG_FSL_ESDHC) 282 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { 283 case 0: 284 sdhc_clk = 0; 285 break; 286 case 1: 287 sdhc_clk = csb_clk; 288 break; 289 case 2: 290 sdhc_clk = csb_clk / 2; 291 break; 292 case 3: 293 sdhc_clk = csb_clk / 3; 294 break; 295 default: 296 /* unkown SCCR_SDHCCM value */ 297 return -8; 298 } 299 #endif 300 #if defined(CONFIG_MPC8315) 301 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { 302 case 0: 303 tdm_clk = 0; 304 break; 305 case 1: 306 tdm_clk = csb_clk; 307 break; 308 case 2: 309 tdm_clk = csb_clk / 2; 310 break; 311 case 3: 312 tdm_clk = csb_clk / 3; 313 break; 314 default: 315 /* unkown SCCR_TDMCM value */ 316 return -8; 317 } 318 #endif 319 320 #if defined(CONFIG_MPC834x) 321 i2c1_clk = tsec2_clk; 322 #elif defined(CONFIG_MPC8360) 323 i2c1_clk = csb_clk; 324 #elif defined(CONFIG_MPC832x) 325 i2c1_clk = enc_clk; 326 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) 327 i2c1_clk = enc_clk; 328 #elif defined(CONFIG_FSL_ESDHC) 329 i2c1_clk = sdhc_clk; 330 #elif defined(CONFIG_MPC837x) 331 i2c1_clk = enc_clk; 332 #endif 333 #if !defined(CONFIG_MPC832x) 334 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ 335 #endif 336 337 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 338 defined(CONFIG_MPC837x) 339 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { 340 case 0: 341 pciexp1_clk = 0; 342 break; 343 case 1: 344 pciexp1_clk = csb_clk; 345 break; 346 case 2: 347 pciexp1_clk = csb_clk / 2; 348 break; 349 case 3: 350 pciexp1_clk = csb_clk / 3; 351 break; 352 default: 353 /* unkown SCCR_PCIEXP1CM value */ 354 return -9; 355 } 356 357 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) { 358 case 0: 359 pciexp2_clk = 0; 360 break; 361 case 1: 362 pciexp2_clk = csb_clk; 363 break; 364 case 2: 365 pciexp2_clk = csb_clk / 2; 366 break; 367 case 3: 368 pciexp2_clk = csb_clk / 3; 369 break; 370 default: 371 /* unkown SCCR_PCIEXP2CM value */ 372 return -10; 373 } 374 #endif 375 376 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 377 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { 378 case 0: 379 sata_clk = 0; 380 break; 381 case 1: 382 sata_clk = csb_clk; 383 break; 384 case 2: 385 sata_clk = csb_clk / 2; 386 break; 387 case 3: 388 sata_clk = csb_clk / 3; 389 break; 390 default: 391 /* unkown SCCR_SATACM value */ 392 return -11; 393 } 394 #endif 395 396 lbiu_clk = csb_clk * 397 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); 398 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; 399 switch (lcrr) { 400 case 2: 401 case 4: 402 case 8: 403 lclk_clk = lbiu_clk / lcrr; 404 break; 405 default: 406 /* unknown lcrr */ 407 return -12; 408 } 409 410 mem_clk = csb_clk * 411 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); 412 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT; 413 414 #if defined(CONFIG_MPC8360) 415 mem_sec_clk = csb_clk * (1 + 416 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); 417 #endif 418 419 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); 420 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { 421 /* corecnf_tab_index is too high, possibly worng value */ 422 return -11; 423 } 424 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { 425 case _byp: 426 case _x1: 427 case _1x: 428 core_clk = csb_clk; 429 break; 430 case _1_5x: 431 core_clk = (3 * csb_clk) / 2; 432 break; 433 case _2x: 434 core_clk = 2 * csb_clk; 435 break; 436 case _2_5x: 437 core_clk = (5 * csb_clk) / 2; 438 break; 439 case _3x: 440 core_clk = 3 * csb_clk; 441 break; 442 default: 443 /* unkown core to csb ratio */ 444 return -13; 445 } 446 447 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 448 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT; 449 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT; 450 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); 451 brg_clk = qe_clk / 2; 452 #endif 453 454 gd->csb_clk = csb_clk; 455 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 456 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 457 gd->tsec1_clk = tsec1_clk; 458 gd->tsec2_clk = tsec2_clk; 459 gd->usbdr_clk = usbdr_clk; 460 #endif 461 #if defined(CONFIG_MPC834x) 462 gd->usbmph_clk = usbmph_clk; 463 #endif 464 #if defined(CONFIG_MPC8315) 465 gd->tdm_clk = tdm_clk; 466 #endif 467 #if defined(CONFIG_FSL_ESDHC) 468 gd->sdhc_clk = sdhc_clk; 469 #endif 470 gd->core_clk = core_clk; 471 gd->i2c1_clk = i2c1_clk; 472 #if !defined(CONFIG_MPC832x) 473 gd->i2c2_clk = i2c2_clk; 474 #endif 475 gd->enc_clk = enc_clk; 476 gd->lbiu_clk = lbiu_clk; 477 gd->lclk_clk = lclk_clk; 478 gd->mem_clk = mem_clk; 479 #if defined(CONFIG_MPC8360) 480 gd->mem_sec_clk = mem_sec_clk; 481 #endif 482 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 483 gd->qe_clk = qe_clk; 484 gd->brg_clk = brg_clk; 485 #endif 486 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 487 defined(CONFIG_MPC837x) 488 gd->pciexp1_clk = pciexp1_clk; 489 gd->pciexp2_clk = pciexp2_clk; 490 #endif 491 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 492 gd->sata_clk = sata_clk; 493 #endif 494 gd->pci_clk = pci_sync_in; 495 gd->cpu_clk = gd->core_clk; 496 gd->bus_clk = gd->csb_clk; 497 return 0; 498 499 } 500 501 /******************************************** 502 * get_bus_freq 503 * return system bus freq in Hz 504 *********************************************/ 505 ulong get_bus_freq(ulong dummy) 506 { 507 return gd->csb_clk; 508 } 509 510 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) 511 { 512 char buf[32]; 513 514 printf("Clock configuration:\n"); 515 printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk)); 516 printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); 517 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 518 printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); 519 printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); 520 #endif 521 printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk)); 522 printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk)); 523 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk)); 524 #if defined(CONFIG_MPC8360) 525 printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk)); 526 #endif 527 printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk)); 528 printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk)); 529 #if !defined(CONFIG_MPC832x) 530 printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk)); 531 #endif 532 #if defined(CONFIG_MPC8315) 533 printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk)); 534 #endif 535 #if defined(CONFIG_FSL_ESDHC) 536 printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk)); 537 #endif 538 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 539 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) 540 printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk)); 541 printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk)); 542 printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); 543 #endif 544 #if defined(CONFIG_MPC834x) 545 printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); 546 #endif 547 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 548 defined(CONFIG_MPC837x) 549 printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); 550 printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); 551 #endif 552 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) 553 printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk)); 554 #endif 555 return 0; 556 } 557 558 U_BOOT_CMD(clocks, 1, 0, do_clocks, 559 "print clock configuration", 560 " clocks" 561 ); 562